KR910007131A - 마스터 슬라이스 집적 회로 장치 - Google Patents

마스터 슬라이스 집적 회로 장치 Download PDF

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Publication number
KR910007131A
KR910007131A KR1019900014033A KR900014033A KR910007131A KR 910007131 A KR910007131 A KR 910007131A KR 1019900014033 A KR1019900014033 A KR 1019900014033A KR 900014033 A KR900014033 A KR 900014033A KR 910007131 A KR910007131 A KR 910007131A
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KR
South Korea
Prior art keywords
integrated circuit
master slice
slice integrated
circuit device
circuit region
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KR1019900014033A
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English (en)
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KR0154121B1 (ko
Inventor
야스히로 오구찌
다까시 사꾸다
가즈히꼬 오까와
Original Assignee
야마무라 가쯔미
세이꼬 엡슨 가부시끼가이샤
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Application filed by 야마무라 가쯔미, 세이꼬 엡슨 가부시끼가이샤 filed Critical 야마무라 가쯔미
Publication of KR910007131A publication Critical patent/KR910007131A/ko
Application granted granted Critical
Publication of KR0154121B1 publication Critical patent/KR0154121B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음

Description

마스터 슬라이스 집적 회로 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명의 제 1 실시예를 따라서 게이트 어레이의 와이어링(wi ring)패턴을 도시한 부분 평면도.
제 2 도는 제 1 도의 실시예에서 상이한 전원선 형성 방식을 도시한 개요도.

Claims (6)

  1. 내부 셀 어레이 및 상기 내부 셀 어레이로부터 외향으로 형성된 외부 셀 어레이, 외부 셀 어레이에 형성되는 주 전원 회로 영역, 주 전원 회로 영역과 전기적으로 접속하며 내부 어레이 영역에 형성된 다수의 전원선, 내부 및 외부 셀의 규정된 접촉 부재를 전기적으로 상호 접속하기 위한 다수의 신호선을 구비하는 마스터 슬라이스 집적회로 장치에 있어서, 각 전원선은 중간 회로 영역을 경유하여 주 전원 회로 영역과 접속되며, 상기 중간 회로 영역은 주 전원 회로 영역의 위치에서 시작하며 관련된 하나의 전원선 방향으로 연장되는 고정된 위치 분기부 및 상기 고정된 위치 분기부에 부착되는 규정된 길이의 교차 접속 허용부를 포함하여 이루어지는 점이 개량된 마스터 슬라이스 집적 회로 장치.
  2. 제 1 항에 있어서, 중간 회로 영역은 실질적으로 T형으로 구성되는 마스터 슬라이스 집적 회로 장치.
  3. 제 1 항에 있어서, 중간 회로 영역은 실질적으로 L형으로 구성되는 마스터 슬라이스 집적 회로 장치.
  4. 제 1 항에 있어서, 각 전원선이 인접한 내부 셀의 쌍 사이의 경계를 따라서 형성되는 마스터 슬라이스 집적 회로 장치.
  5. 제 1 항에 있어서, 외부 셀의 피치(POUT) 및 내부 셀의 피치(PIN)사이의 관계는
    (여기서, j 및 k는 양의 정수)로 표현되는 마스터 슬라이스 집적 회로 장치.
  6. 제 1 내지 5 항의 어느 한 항에 있어서, 외부 셀의 피치 POUT,내부 셀의 피치 PIN및 교차한 접속 허용부의 길이 h간의 관계는
    로 표현되는 마스터 슬라이스 집적 회로 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임
KR1019900014033A 1989-09-08 1990-09-06 마스터 슬라이스 집적 회로 장치 KR0154121B1 (ko)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP1-233326 1989-09-08
JP23332689 1989-09-08
JP233326 1989-09-08
JP2166115A JP2917434B2 (ja) 1989-09-08 1990-06-25 マスタースライス集積回路装置
JP166115 1990-06-25
JP2-166115 1990-06-25

Publications (2)

Publication Number Publication Date
KR910007131A true KR910007131A (ko) 1991-04-30
KR0154121B1 KR0154121B1 (ko) 1998-10-15

Family

ID=26490608

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900014033A KR0154121B1 (ko) 1989-09-08 1990-09-06 마스터 슬라이스 집적 회로 장치

Country Status (7)

Country Link
US (2) US5153698A (ko)
EP (1) EP0416456B1 (ko)
JP (1) JP2917434B2 (ko)
KR (1) KR0154121B1 (ko)
DE (1) DE69033641T2 (ko)
HK (1) HK1014295A1 (ko)
SG (1) SG87731A1 (ko)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05308136A (ja) * 1992-04-01 1993-11-19 Nec Corp マスタスライス集積回路
US5416431A (en) * 1994-03-21 1995-05-16 At&T Corp. Integrated circuit clock driver having improved layout
EP0791930B1 (en) * 1995-10-02 2004-02-18 Matsushita Electric Industrial Co., Ltd. Electric signal supply circuit and semiconductor memory device
JP2001053155A (ja) * 1999-06-04 2001-02-23 Seiko Epson Corp 半導体集積回路装置
JP3964295B2 (ja) * 2002-09-18 2007-08-22 松下電器産業株式会社 集積回路設計における電源経路構造
US20070090385A1 (en) * 2005-10-21 2007-04-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
KR100763108B1 (ko) * 2005-11-24 2007-10-04 주식회사 하이닉스반도체 파워 라인의 폭을 선택적으로 조절하는 반도체 장치의 파워라인 제어 회로
JPWO2016129109A1 (ja) * 2015-02-13 2017-11-24 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
CN109755279B (zh) * 2019-01-09 2020-11-17 昆山国显光电有限公司 Oled显示面板及oled显示装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5835963A (ja) * 1981-08-28 1983-03-02 Fujitsu Ltd 集積回路装置
EP0074805B2 (en) * 1981-09-10 1992-03-11 Fujitsu Limited Semiconductor integrated circuit comprising a semiconductor substrate and interconnecting layers
JPS6017932A (ja) * 1983-07-09 1985-01-29 Fujitsu Ltd ゲ−ト・アレイ
JPS60101951A (ja) * 1983-11-08 1985-06-06 Sanyo Electric Co Ltd ゲ−トアレイ
JPS6120349A (ja) * 1984-07-06 1986-01-29 Hitachi Ltd Ｌｓｉ集合体
JPS61241964A (ja) * 1985-04-19 1986-10-28 Hitachi Ltd 半導体装置
JPH0785490B2 (ja) * 1986-01-22 1995-09-13 日本電気株式会社 集積回路装置
JPH0828421B2 (ja) * 1987-08-27 1996-03-21 株式会社東芝 半導体集積回路装置
DE4433617C2 (de) * 1994-09-21 1997-04-24 Kostal Leopold Gmbh & Co Kg Elektrisches Steckverbindungsteil
JP3456768B2 (ja) * 1994-09-28 2003-10-14 株式会社東芝 アドレス変換装置

Also Published As

Publication number Publication date
SG87731A1 (en) 2002-04-16
DE69033641T2 (de) 2001-05-03
EP0416456B1 (en) 2000-10-04
US5345098A (en) 1994-09-06
HK1014295A1 (en) 1999-09-24
JPH03174770A (ja) 1991-07-29
KR0154121B1 (ko) 1998-10-15
JP2917434B2 (ja) 1999-07-12
US5153698A (en) 1992-10-06
EP0416456A1 (en) 1991-03-13
DE69033641D1 (de) 2000-11-09

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