DE3750674D1 - Halbleiterintegrierte Schaltung mit Prüffunktion. - Google Patents

Halbleiterintegrierte Schaltung mit Prüffunktion.

Info

Publication number
DE3750674D1
DE3750674D1 DE3750674T DE3750674T DE3750674D1 DE 3750674 D1 DE3750674 D1 DE 3750674D1 DE 3750674 T DE3750674 T DE 3750674T DE 3750674 T DE3750674 T DE 3750674T DE 3750674 D1 DE3750674 D1 DE 3750674D1
Authority
DE
Germany
Prior art keywords
integrated circuit
semiconductor integrated
test function
test
function
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3750674T
Other languages
English (en)
Other versions
DE3750674T2 (de
Inventor
Koichi Yamashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE3750674D1 publication Critical patent/DE3750674D1/de
Application granted granted Critical
Publication of DE3750674T2 publication Critical patent/DE3750674T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318335—Test pattern compression or decompression
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318385—Random or pseudo-random test pattern
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/318547—Data generators or compressors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/27—Built-in tests

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE3750674T 1986-12-17 1987-12-15 Halbleiterintegrierte Schaltung mit Prüffunktion. Expired - Fee Related DE3750674T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61302112A JP2628154B2 (ja) 1986-12-17 1986-12-17 半導体集積回路

Publications (2)

Publication Number Publication Date
DE3750674D1 true DE3750674D1 (de) 1994-11-24
DE3750674T2 DE3750674T2 (de) 1995-03-09

Family

ID=17905071

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3750674T Expired - Fee Related DE3750674T2 (de) 1986-12-17 1987-12-15 Halbleiterintegrierte Schaltung mit Prüffunktion.

Country Status (5)

Country Link
US (1) US4910735A (de)
EP (1) EP0273821B1 (de)
JP (1) JP2628154B2 (de)
KR (1) KR900004252B1 (de)
DE (1) DE3750674T2 (de)

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2673298B2 (ja) * 1987-12-17 1997-11-05 三菱電機株式会社 セルフテスト機能付半導体集積回路
US6304987B1 (en) * 1995-06-07 2001-10-16 Texas Instruments Incorporated Integrated test circuit
DE68928600T2 (de) * 1988-09-07 1998-07-02 Texas Instruments Inc Erweiterte Prüfschaltung
KR910006241B1 (ko) * 1988-12-14 1991-08-17 삼성전자 주식회사 복수 테스트모드 선택회로
US5051996A (en) * 1989-03-27 1991-09-24 The United States Of America As Represented By The United States Department Of Energy Built-in-test by signature inspection (bitsi)
JPH0394183A (ja) * 1989-05-19 1991-04-18 Fujitsu Ltd 半導体集積回路の試験方法及び回路
US5280487A (en) * 1989-06-16 1994-01-18 Telefonaktiebolaget L M Ericsson Method and arrangement for detecting and localizing errors or faults in a multi-plane unit incorporated in a digital time switch
JP3005250B2 (ja) * 1989-06-30 2000-01-31 テキサス インスツルメンツ インコーポレイテツド バスモニター集積回路
US5119378A (en) * 1990-03-02 1992-06-02 General Electric Company Testing of integrated circuits including internal test circuitry and using token passing to select testing ports
US6675333B1 (en) 1990-03-30 2004-01-06 Texas Instruments Incorporated Integrated circuit with serial I/O controller
JPH0719217B2 (ja) * 1990-04-24 1995-03-06 株式会社東芝 情報処理装置
DE59010092D1 (de) * 1990-05-31 1996-03-07 Siemens Ag Integrierter Halbleiterspeicher
EP0481097B1 (de) 1990-09-15 1995-06-14 International Business Machines Corporation Procédé et appareil pour tester des circuits intégrés à grande integration
US5222066A (en) * 1990-12-26 1993-06-22 Motorola, Inc. Modular self-test for embedded SRAMS
US5515383A (en) * 1991-05-28 1996-05-07 The Boeing Company Built-in self-test system and method for self test of an integrated circuit
JP2770617B2 (ja) * 1991-09-05 1998-07-02 日本電気株式会社 テスト回路
US5453991A (en) * 1992-03-18 1995-09-26 Kabushiki Kaisha Toshiba Integrated circuit device with internal inspection circuitry
JPH063424A (ja) * 1992-06-22 1994-01-11 Mitsubishi Electric Corp 集積回路装置、および集積回路装置に組込まれるテストデータ発生回路
JP3247937B2 (ja) * 1992-09-24 2002-01-21 株式会社日立製作所 論理集積回路
JPH06249919A (ja) * 1993-03-01 1994-09-09 Fujitsu Ltd 半導体集積回路装置の端子間接続試験方法
GB2282244B (en) * 1993-09-23 1998-01-14 Advanced Risc Mach Ltd Integrated circuit
US5583786A (en) * 1993-12-30 1996-12-10 Intel Corporation Apparatus and method for testing integrated circuits
US5638382A (en) * 1994-06-29 1997-06-10 Intel Corporation Built-in self test function for a processor including intermediate test results
US5724502A (en) * 1995-08-07 1998-03-03 International Business Machines Corporation Test mode matrix circuit for an embedded microprocessor core
US5831992A (en) * 1995-08-17 1998-11-03 Northern Telecom Limited Methods and apparatus for fault diagnosis in self-testable systems
US5969538A (en) 1996-10-31 1999-10-19 Texas Instruments Incorporated Semiconductor wafer with interconnect between dies for testing and a process of testing
JPH1070243A (ja) * 1996-05-30 1998-03-10 Toshiba Corp 半導体集積回路装置およびその検査方法およびその検査装置
US6750527B1 (en) * 1996-05-30 2004-06-15 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device having a plurality of wells, test method of testing the semiconductor integrated circuit device, and test device which executes the test method
JP3592885B2 (ja) * 1997-03-31 2004-11-24 シャープ株式会社 半導体集積回路装置
TW380344B (en) * 1998-02-04 2000-01-21 Admtek Co Multiple output single crystal device for not generating simultaneous switch output
US6405335B1 (en) 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
US7058862B2 (en) * 2000-05-26 2006-06-06 Texas Instruments Incorporated Selecting different 1149.1 TAP domains from update-IR state
US8533547B2 (en) * 1999-11-23 2013-09-10 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
US7493540B1 (en) 1999-11-23 2009-02-17 Jansuz Rajski Continuous application and decompression of test patterns to a circuit-under-test
US9664739B2 (en) 1999-11-23 2017-05-30 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
US9134370B2 (en) 1999-11-23 2015-09-15 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
US6557129B1 (en) 1999-11-23 2003-04-29 Janusz Rajski Method and apparatus for selectively compacting test responses
US6684358B1 (en) * 1999-11-23 2004-01-27 Janusz Rajski Decompressor/PRPG for applying pseudo-random and deterministic test patterns
US6874109B1 (en) * 1999-11-23 2005-03-29 Janusz Rajski Phase shifter with reduced linear dependency
US6353842B1 (en) * 1999-11-23 2002-03-05 Janusz Rajski Method for synthesizing linear finite state machines
WO2001039254A2 (en) * 1999-11-23 2001-05-31 Mentor Graphics Corporation Continuous application and decompression of test patterns to a circuit-under-test
US6327687B1 (en) 1999-11-23 2001-12-04 Janusz Rajski Test pattern compression for an integrated circuit test environment
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
JP2004325233A (ja) 2003-04-24 2004-11-18 Matsushita Electric Ind Co Ltd 半導体装置
WO2006061668A1 (en) 2004-12-07 2006-06-15 Infineon Technologies Ag Test time reduction for multi-chip modules (mcm) and for system-in-packages (sip)
KR100631925B1 (ko) * 2005-01-28 2006-10-04 삼성전자주식회사 반도체 메모리 장치의 테스트 회로
US7260760B2 (en) * 2005-04-27 2007-08-21 International Business Machines Corporation Method and apparatus to disable compaction of test responses in deterministic test-set embedding-based BIST
JP2007322150A (ja) * 2006-05-30 2007-12-13 Matsushita Electric Ind Co Ltd 半導体装置
CA2664620A1 (en) 2009-05-07 2009-07-20 Avalon Microelectronics, Inc. Pseudo-random bit sequence generator
CN104535919B (zh) * 2015-01-20 2018-04-03 山东华芯半导体有限公司 一种正常工作模式下芯片调试方法及调试电路

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5479569A (en) * 1977-12-07 1979-06-25 Nec Corp Intergrated circuit
JPS5676854A (en) * 1979-11-28 1981-06-24 Nec Corp Integrated circuit device
JPS609136A (ja) * 1983-06-29 1985-01-18 Fujitsu Ltd 自己試験タイプｌｓｉ
JPS6068624A (ja) * 1983-09-26 1985-04-19 Toshiba Corp Ｌｓｉの自己検査装置
US4598401A (en) * 1984-05-03 1986-07-01 Siemens Corporate Research & Support, Inc. Circuit testing apparatus employing signature analysis
GB8432533D0 (en) * 1984-12-21 1985-02-06 Plessey Co Plc Integrated circuits
JPS61204744A (ja) * 1985-02-05 1986-09-10 Hitachi Ltd 診断機能を有するｒａｍ内蔵ｌｓｉおよびその診断方法
US4682329A (en) * 1985-03-28 1987-07-21 Kluth Daniel J Test system providing testing sites for logic circuits
US4701921A (en) * 1985-10-23 1987-10-20 Texas Instruments Incorporated Modularized scan path for serially tested logic circuit

Also Published As

Publication number Publication date
JPS63153483A (ja) 1988-06-25
KR880008342A (ko) 1988-08-30
EP0273821A2 (de) 1988-07-06
DE3750674T2 (de) 1995-03-09
EP0273821B1 (de) 1994-10-19
EP0273821A3 (en) 1990-03-28
JP2628154B2 (ja) 1997-07-09
US4910735A (en) 1990-03-20
KR900004252B1 (en) 1990-06-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee