DE3675666D1 - Integrierte halbleiterschaltungsanordnung. - Google Patents

Integrierte halbleiterschaltungsanordnung.

Info

Publication number
DE3675666D1
DE3675666D1 DE8686100798T DE3675666T DE3675666D1 DE 3675666 D1 DE3675666 D1 DE 3675666D1 DE 8686100798 T DE8686100798 T DE 8686100798T DE 3675666 T DE3675666 T DE 3675666T DE 3675666 D1 DE3675666 D1 DE 3675666D1
Authority
DE
Germany
Prior art keywords
circuit arrangement
semiconductor circuit
integrated semiconductor
integrated
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686100798T
Other languages
English (en)
Inventor
Yasunaga Suzuki
Toshiaki Matsubara
Haruo Mamyoda
Akira Uragami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP60010832A external-priority patent/JPH0815209B2/ja
Priority claimed from JP60103727A external-priority patent/JPH0828483B2/ja
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of DE3675666D1 publication Critical patent/DE3675666D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11896—Masterslice integrated circuits using combined field effect/bipolar technology

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE8686100798T 1985-01-25 1986-01-22 Integrierte halbleiterschaltungsanordnung. Expired - Lifetime DE3675666D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP60010832A JPH0815209B2 (ja) 1985-01-25 1985-01-25 半導体集積回路装置
JP60103727A JPH0828483B2 (ja) 1985-05-17 1985-05-17 半導体集積回路装置

Publications (1)

Publication Number Publication Date
DE3675666D1 true DE3675666D1 (de) 1991-01-03

Family

ID=26346175

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686100798T Expired - Lifetime DE3675666D1 (de) 1985-01-25 1986-01-22 Integrierte halbleiterschaltungsanordnung.

Country Status (7)

Country Link
US (1) US5001487A (de)
EP (1) EP0189183B1 (de)
KR (1) KR930005497B1 (de)
CN (1) CN1003549B (de)
DE (1) DE3675666D1 (de)
HK (1) HK20893A (de)
SG (1) SG102692G (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62261144A (ja) * 1986-05-07 1987-11-13 Mitsubishi Electric Corp 半導体集積回路
JPH0831581B2 (ja) * 1988-02-19 1996-03-27 株式会社東芝 半導体装置
JPH01256149A (ja) * 1988-04-06 1989-10-12 Hitachi Ltd ゲートアレイ集積回路
US5281835A (en) * 1989-06-14 1994-01-25 Fujitsu Limited Semi-custom integrated circuit device
JP3030778B2 (ja) * 1989-06-14 2000-04-10 富士通株式会社 セミカスタム集積回路装置
US5410173A (en) * 1991-01-28 1995-04-25 Kikushima; Ken'ichi Semiconductor integrated circuit device
JP2505910B2 (ja) * 1990-05-24 1996-06-12 株式会社東芝 半導体集積回路用セルライブラリ
US5963057A (en) * 1997-08-05 1999-10-05 Lsi Logic Corporation Chip level bias for buffers driving voltages greater than transistor tolerance
US6300800B1 (en) 1999-11-24 2001-10-09 Lsi Logic Corporation Integrated circuit I/O buffer with series P-channel and floating well

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4414547A (en) * 1981-08-05 1983-11-08 General Instrument Corporation Storage logic array having two conductor data column
US4556947A (en) * 1982-08-23 1985-12-03 Motorola, Inc. Bi-directional switching circuit
US4568961A (en) * 1983-03-11 1986-02-04 Rca Corporation Variable geometry automated universal array
JPH0669142B2 (ja) * 1983-04-15 1994-08-31 株式会社日立製作所 半導体集積回路装置
US4593205A (en) * 1983-07-01 1986-06-03 Motorola, Inc. Macrocell array having an on-chip clock generator
US4617479B1 (en) * 1984-05-03 1993-09-21 Altera Semiconductor Corp. Programmable logic array device using eprom technology

Also Published As

Publication number Publication date
CN85108621A (zh) 1986-07-23
KR930005497B1 (ko) 1993-06-22
KR860006136A (ko) 1986-08-18
US5001487A (en) 1991-03-19
EP0189183B1 (de) 1990-11-22
CN1003549B (zh) 1989-03-08
EP0189183A1 (de) 1986-07-30
HK20893A (en) 1993-03-19
SG102692G (en) 1992-12-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee