KR900004014A - 게이트 어레이 - Google Patents
게이트 어레이 Download PDFInfo
- Publication number
- KR900004014A KR900004014A KR1019890011807A KR890011807A KR900004014A KR 900004014 A KR900004014 A KR 900004014A KR 1019890011807 A KR1019890011807 A KR 1019890011807A KR 890011807 A KR890011807 A KR 890011807A KR 900004014 A KR900004014 A KR 900004014A
- Authority
- KR
- South Korea
- Prior art keywords
- conductor layer
- same time
- impurity regions
- substrate
- insulating films
- Prior art date
Links
- 239000004020 conductor Substances 0.000 claims 10
- 239000012535 impurity Substances 0.000 claims 6
- 239000000758 substrate Substances 0.000 claims 3
- 238000002955 isolation Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Geometry (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 이 발명에 관한 게이트 아이소레이션(gate isolation)을 사용한 SOG 방식의 마스터칩(master chip)를 표시하는 평면도.
제2a도는 게이트 아이소레이션을 사용한 SOG 방식의 마스터칩 상에 3NAND 게이트의 회로를 구성한 경우의 마스크 패턴(mask patterm)도.
제2b도는 제2a도의 ⅡB-ⅡB선으로 표시하는 부분의 단면도.
제2c도는 제2a도의 ⅡC-ⅡC선으로 표시하는 부분의 단면도.
제3도는 논리회로가 구성된 SOG의 실제의 레이아웃패턴을 매트로(macro)적으로 본 평면도.
Claims (1)
- 기판과 상기 기판의 주표면상에 간격을 두고 제1의 방향에 연재(延在)하여 형성되고 동시에 소정의 폭을 가지는 복수의 제1도전형의 불순물 영역과, 상기 복수의 제1도 전형의 불순물 영역이 형성되지 않는 영역에서 동시에 상기 기판의 주표면상에 상기 제1의 방향에 연재하여 형성되어, 동시에 소정의 폭을 가지는 복수의 제2도 전형의 불순물영역과 상기 제1도전형의 불순물 영역상에 절연막을 끼워 동시에 상호간격을 두고 상기 제1의 방향에 형성된 복수의 제1도체층과, 상기 제2도전형의 불순물 여역상에 절연막을 끼워 동시에 상호간격을 두고 상기 제1의 방향에 형성된 복수의 제2도체층과, 상기 제1의도체층과 상기 제2의 도체층은 상기 제1방향과 교차하는 제2의 방향에 정열하여 형성되어 인접하여 형성된 상기 제1의 도체층과 상기 제2의 도체층 및 상기 제1 및 제2의 도체층의 양측에 설정된 제1 및 제2의 불순물영역과는 1개의 유닛을 구성하고 각각이 상기 유닛을 포함하는 북수의 논리 셀 유닛과, 상기 논리셀 유닛은 적어도 상기 제2의 방향에 연속하여 형성되고, 상기 복수의 논리셀 유닛간을 상호접속하기 위해 상기 제2의 방향에 연속하여 형성된 도체층을 포함하는 게이트 어레이.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63205571A JPH0254576A (ja) | 1988-08-18 | 1988-08-18 | ゲートアレイ |
JP88-205571 | 1988-08-18 | ||
JP63-205571 | 1988-08-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR900004014A true KR900004014A (ko) | 1990-03-27 |
KR920010436B1 KR920010436B1 (ko) | 1992-11-27 |
Family
ID=16509097
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019890011807A KR920010436B1 (ko) | 1988-08-18 | 1989-08-18 | 게이트 어레이(gate array) |
Country Status (4)
Country | Link |
---|---|
US (1) | US4999698A (ko) |
JP (1) | JPH0254576A (ko) |
KR (1) | KR920010436B1 (ko) |
DE (1) | DE3927143C2 (ko) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5367208A (en) | 1986-09-19 | 1994-11-22 | Actel Corporation | Reconfigurable programmable interconnect architecture |
JPH02222572A (ja) * | 1989-02-23 | 1990-09-05 | Sharp Corp | 半導体集積回路装置 |
US5073729A (en) * | 1990-06-22 | 1991-12-17 | Actel Corporation | Segmented routing architecture |
JPH06509911A (ja) * | 1992-06-10 | 1994-11-02 | アスペック テクノロジー インコーポレイテッド | 連続基板タップを備えた対称な多層金属論理アレイ |
US5384472A (en) * | 1992-06-10 | 1995-01-24 | Aspec Technology, Inc. | Symmetrical multi-layer metal logic array with continuous substrate taps and extension portions for increased gate density |
US5308798A (en) * | 1992-11-12 | 1994-05-03 | Vlsi Technology, Inc. | Preplacement method for weighted net placement integrated circuit design layout tools |
JP3488735B2 (ja) * | 1994-03-03 | 2004-01-19 | 三菱電機株式会社 | 半導体装置 |
IL111708A (en) * | 1994-11-21 | 1998-03-10 | Chip Express Israel Ltd | Array mapping goes |
JP3432963B2 (ja) * | 1995-06-15 | 2003-08-04 | 沖電気工業株式会社 | 半導体集積回路 |
US7389487B1 (en) | 1998-04-28 | 2008-06-17 | Actel Corporation | Dedicated interface architecture for a hybrid integrated circuit |
JP4279955B2 (ja) * | 1998-12-08 | 2009-06-17 | 富士通マイクロエレクトロニクス株式会社 | 半導体集積回路装置及びその製造方法 |
US6856022B2 (en) * | 2003-03-31 | 2005-02-15 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
JP4543061B2 (ja) * | 2007-05-15 | 2010-09-15 | 株式会社東芝 | 半導体集積回路 |
JP2010177268A (ja) * | 2009-01-27 | 2010-08-12 | Asahi Kasei Electronics Co Ltd | 接合型fet、半導体装置およびその製造方法 |
US11290109B1 (en) * | 2020-09-23 | 2022-03-29 | Qualcomm Incorporated | Multibit multi-height cell to improve pin accessibility |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5843905B2 (ja) * | 1979-07-31 | 1983-09-29 | 富士通株式会社 | 半導体集積回路の製造方法 |
JPS5720447A (en) * | 1980-07-11 | 1982-02-02 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor integrated circuit device |
DE3143565A1 (de) * | 1981-11-03 | 1983-05-11 | International Microcircuits Inc., 95051 Santa Clara, Calif. | Integrierte schaltung |
JPS5972742A (ja) * | 1982-10-20 | 1984-04-24 | Hitachi Ltd | マスタスライスlsiのマスタ方法 |
JPS6056292A (ja) * | 1983-09-08 | 1985-04-01 | 財団法人電力中央研究所 | 高速増殖炉 |
EP0154346B1 (en) * | 1984-03-08 | 1991-09-18 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device |
EP0177336B1 (en) * | 1984-10-03 | 1992-07-22 | Fujitsu Limited | Gate array integrated device |
JPS61100947A (ja) * | 1984-10-22 | 1986-05-19 | Toshiba Corp | 半導体集積回路装置 |
JPH0628305B2 (ja) * | 1986-05-14 | 1994-04-13 | 三菱電機株式会社 | マスタスライスlsi |
US4884118A (en) * | 1986-05-19 | 1989-11-28 | Lsi Logic Corporation | Double metal HCMOS compacted array |
JPH0831578B2 (ja) * | 1986-06-19 | 1996-03-27 | 日本電気株式会社 | マスタ−スライス方式のゲ−トアレ−半導体集積回路装置 |
-
1988
- 1988-08-18 JP JP63205571A patent/JPH0254576A/ja active Pending
-
1989
- 1989-08-16 US US07/394,329 patent/US4999698A/en not_active Expired - Lifetime
- 1989-08-17 DE DE3927143A patent/DE3927143C2/de not_active Expired - Fee Related
- 1989-08-18 KR KR1019890011807A patent/KR920010436B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
DE3927143A1 (de) | 1990-02-22 |
KR920010436B1 (ko) | 1992-11-27 |
DE3927143C2 (de) | 1994-03-10 |
US4999698A (en) | 1991-03-12 |
JPH0254576A (ja) | 1990-02-23 |
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GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20011122 Year of fee payment: 10 |
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LAPS | Lapse due to unpaid annual fee |