KR920010922A - 반도체기억장치 및 그 제조방법 - Google Patents

반도체기억장치 및 그 제조방법 Download PDF

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Publication number
KR920010922A
KR920010922A KR1019910018031A KR910018031A KR920010922A KR 920010922 A KR920010922 A KR 920010922A KR 1019910018031 A KR1019910018031 A KR 1019910018031A KR 910018031 A KR910018031 A KR 910018031A KR 920010922 A KR920010922 A KR 920010922A
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South Korea
Prior art keywords
peripheral circuit
transistor
gate electrode
resist
region
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KR1019910018031A
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English (en)
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KR960001335B1 (ko
Inventor
도모요시 마메다니
Original Assignee
시기 모리야
미쓰비시 뎅끼 가부시끼가이샤
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Publication of KR920010922A publication Critical patent/KR920010922A/ko
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Publication of KR960001335B1 publication Critical patent/KR960001335B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

내용 없음

Description

반도체기억장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시예에 의한 DRAM의 배선패턴을 표시한 단면도, 제2도는 제1도에 표시한 DRAM의 단면구조도, 제3A도 내지 제3D도는 제1도에 표시한 DRAM의 배선패턴의 형성프로세스를 설명하기 위한 단면도.

Claims (2)

  1. 트랜지스터와 커패시터로 이루어지는 복수의 메모리셀이 형성되는 적어도 1개의 메모리셀 어레이영역과 복수의 주변회로용 트랜지스터가 형성되는 주변회로영역과를 가지는 반도체기판상에 형성되는 반도체기억장치이고 상기 메모리셀어레이영역에 소정의 간격을 띠어서 평행으로 배치되고 각각이 상기 트랜지스터를 구성하는 1조의 게이트전극층과 각각이 상기 주변회로영역에 소정의 간격을 띠어서 평행으로 배치되고 상기 주변회로용 트랜지스터를 구성하는 게이트 전극층 및 더미배선층과를 포함하고 상기 메모리셀 어레이 영역에 형성되는 1조의 게이트전극층의 간격과 상기 주변회로영역에 형성되는 게이트전극층 및 더미배선층의 간격과를 거의 똑같게 되도록 형성한 것을 특징으로 하는 반도체 기억장치.
  2. 트랜지스터와 커패시터로 이루어지는 복수의 메모리셀이 형성되는 적어도 1개의 메모리셀 어레이영역과 복수의 주변회로용 트랜지스터가 형성되는 주변회로영역과를 가지는 반도체기판상에 형성되는 반도체기억장치의 제조방법이고 상기 반도체기판상에 도전층 및 해당 도전층상에 레지스트를 형성하는 스텝과 상기 트랜지스터 및 상기 주변회로용 트랜지스터를 구성하는 게이트전극층으로 되는 도전층상의 레지스트가 남고 상기 주변회로영역에 상기 게이트전극층과 소정의 간격을 띠어서 형성되는 더미배선층으로 되는 도전층상의 레지스트가 남도록 다른 영역의 레지스트를 마스크로하여 상기 도전층을 에칭하여 패터닝하는 스텝과 상기 남겨진 레지스트를 제거하는 스텝과를 포함하는 반도체기억장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910018031A 1990-11-01 1991-10-14 반도체기억장치 및 그 제조방법 KR960001335B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP90-296233 1990-11-01
JP2296233A JP2528737B2 (ja) 1990-11-01 1990-11-01 半導体記憶装置およびその製造方法

Publications (2)

Publication Number Publication Date
KR920010922A true KR920010922A (ko) 1992-06-27
KR960001335B1 KR960001335B1 (ko) 1996-01-26

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KR1019910018031A KR960001335B1 (ko) 1990-11-01 1991-10-14 반도체기억장치 및 그 제조방법

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Country Link
US (1) US5289422A (ko)
JP (1) JP2528737B2 (ko)
KR (1) KR960001335B1 (ko)
DE (1) DE4135826A1 (ko)

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JP3249317B2 (ja) * 1994-12-12 2002-01-21 富士通株式会社 パターン作成方法
JP2658959B2 (ja) * 1995-03-31 1997-09-30 日本電気株式会社 半導体装置およびその製造方法
JP2923912B2 (ja) * 1996-12-25 1999-07-26 日本電気株式会社 半導体装置
KR100219533B1 (ko) * 1997-01-31 1999-09-01 윤종용 임베디드 메모리소자 및 그 제조방법
KR100230421B1 (ko) * 1997-04-22 1999-11-15 윤종용 반도체장치의 더미패턴 형성방법
US6258671B1 (en) 1997-05-13 2001-07-10 Micron Technology, Inc. Methods of providing spacers over conductive line sidewalls, methods of forming sidewall spacers over etched line sidewalls, and methods of forming conductive lines
US6184083B1 (en) 1997-06-30 2001-02-06 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US5899706A (en) * 1997-06-30 1999-05-04 Siemens Aktiengesellschaft Method of reducing loading variation during etch processing
JP3097627B2 (ja) * 1997-11-05 2000-10-10 日本電気株式会社 半導体記憶装置
JPH11219922A (ja) * 1998-02-03 1999-08-10 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2000114246A (ja) * 1998-08-07 2000-04-21 Ulvac Seimaku Kk ドライエッチング方法および装置、フォトマスクおよびその作製方法、ならびに半導体回路およびその製作方法
KR100291384B1 (ko) * 1998-12-31 2001-07-12 윤종용 반도체장치의레이아웃방법
JP2000232207A (ja) 1999-02-10 2000-08-22 Nec Corp 半導体装置およびその製造方法
JP4688343B2 (ja) 2001-05-16 2011-05-25 ルネサスエレクトロニクス株式会社 強誘電体メモリ装置
DE10128933A1 (de) * 2001-06-18 2003-01-02 Infineon Technologies Ag Verfahren zum Herstellen eines Speicherbauelements
CN1901194A (zh) * 2005-07-20 2007-01-24 松下电器产业株式会社 半导体装置及其制造方法
US10522492B2 (en) * 2017-06-05 2019-12-31 Advanced Semiconductor Engineering, Inc. Semiconductor package and semiconductor process

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JPH0658947B2 (ja) * 1984-02-24 1994-08-03 株式会社日立製作所 半導体メモリ装置の製法
JPS61263130A (ja) * 1985-05-15 1986-11-21 Toshiba Corp 半導体装置の製造方法
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JPH0265254A (ja) * 1988-08-31 1990-03-05 Toshiba Corp 半導体装置
JPH0828473B2 (ja) * 1988-09-29 1996-03-21 三菱電機株式会社 半導体装置およびその製造方法

Also Published As

Publication number Publication date
JPH04168765A (ja) 1992-06-16
JP2528737B2 (ja) 1996-08-28
US5289422A (en) 1994-02-22
DE4135826A1 (de) 1992-05-07
KR960001335B1 (ko) 1996-01-26

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