DE68924452D1 - Packungsstruktur für integrierte Schaltungen. - Google Patents

Packungsstruktur für integrierte Schaltungen.

Info

Publication number
DE68924452D1
DE68924452D1 DE68924452T DE68924452T DE68924452D1 DE 68924452 D1 DE68924452 D1 DE 68924452D1 DE 68924452 T DE68924452 T DE 68924452T DE 68924452 T DE68924452 T DE 68924452T DE 68924452 D1 DE68924452 D1 DE 68924452D1
Authority
DE
Germany
Prior art keywords
integrated circuits
packing structure
packing
circuits
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68924452T
Other languages
English (en)
Other versions
DE68924452T2 (de
Inventor
Toshio C O Fujitsu L Matsuzaki
Hiroaki C O Fujitsu Li Toshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP1260589A external-priority patent/JPH02192148A/ja
Priority claimed from JP1117126A external-priority patent/JPH07105465B2/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE68924452D1 publication Critical patent/DE68924452D1/de
Application granted granted Critical
Publication of DE68924452T2 publication Critical patent/DE68924452T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
DE68924452T 1988-07-11 1989-07-10 Packungsstruktur für integrierte Schaltungen. Expired - Fee Related DE68924452T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP17243388 1988-07-11
JP331889 1989-01-10
JP1260589A JPH02192148A (ja) 1989-01-19 1989-01-19 集積回路装置
JP1117126A JPH07105465B2 (ja) 1989-01-10 1989-05-09 ハイブリッド型集積回路装置

Publications (2)

Publication Number Publication Date
DE68924452D1 true DE68924452D1 (de) 1995-11-09
DE68924452T2 DE68924452T2 (de) 1996-03-28

Family

ID=27453837

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68924452T Expired - Fee Related DE68924452T2 (de) 1988-07-11 1989-07-10 Packungsstruktur für integrierte Schaltungen.

Country Status (3)

Country Link
US (1) US4994895A (de)
EP (1) EP0350833B1 (de)
DE (1) DE68924452T2 (de)

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JPH0777256B2 (ja) * 1989-08-25 1995-08-16 株式会社東芝 樹脂封止型半導体装置
US5264730A (en) * 1990-01-06 1993-11-23 Fujitsu Limited Resin mold package structure of integrated circuit
US5334872A (en) * 1990-01-29 1994-08-02 Mitsubishi Denki Kabushiki Kaisha Encapsulated semiconductor device having a hanging heat spreading plate electrically insulated from the die pad
JP2890662B2 (ja) * 1990-04-25 1999-05-17 ソニー株式会社 樹脂封止型半導体装置の製造方法とそれに用いるリードフレーム
US5175610A (en) * 1990-05-09 1992-12-29 Kabushiki Kaisha Toshiba Resin molded type semiconductor device having a metallic plate support
US5202288A (en) * 1990-06-01 1993-04-13 Robert Bosch Gmbh Method of manufacturing an electronic circuit component incorporating a heat sink
US5053852A (en) * 1990-07-05 1991-10-01 At&T Bell Laboratories Molded hybrid IC package and lead frame therefore
DE69131784T2 (de) * 1990-07-21 2000-05-18 Mitsui Chemicals Inc Halbleiteranordnung mit einer Packung
US5250842A (en) * 1990-09-07 1993-10-05 Nec Corporation Semiconductor devices using tab tape
JP2501953B2 (ja) * 1991-01-18 1996-05-29 株式会社東芝 半導体装置
KR920020685A (ko) * 1991-04-22 1992-11-21 빈센트 죠셉 로너 반도체 패캐이지 및 그 부착방법
US5214846A (en) * 1991-04-24 1993-06-01 Sony Corporation Packaging of semiconductor chips
US5250847A (en) * 1991-06-27 1993-10-05 Motorola, Inc. Stress isolating signal path for integrated circuits
JPH0582696A (ja) * 1991-09-19 1993-04-02 Mitsubishi Electric Corp 半導体装置のリードフレーム
JPH0582685A (ja) * 1991-09-24 1993-04-02 Mitsubishi Electric Corp 混成集積部品の放熱部および端子部用構造体とその構造体を用いた混成集積部品の製造方法
US5197183A (en) * 1991-11-05 1993-03-30 Lsi Logic Corporation Modified lead frame for reducing wire wash in transfer molding of IC packages
US5233222A (en) * 1992-07-27 1993-08-03 Motorola, Inc. Semiconductor device having window-frame flag with tapered edge in opening
US5283717A (en) * 1992-12-04 1994-02-01 Sgs-Thomson Microelectronics, Inc. Circuit assembly having interposer lead frame
US5309019A (en) * 1993-02-26 1994-05-03 Motorola, Inc. Low inductance lead frame for a semiconductor package
TW276357B (de) * 1993-03-22 1996-05-21 Motorola Inc
US5327008A (en) * 1993-03-22 1994-07-05 Motorola Inc. Semiconductor device having universal low-stress die support and method for making the same
JPH06291234A (ja) * 1993-04-01 1994-10-18 Mitsubishi Electric Corp 半導体装置用リードフレームおよびこれを使用した半導体装置の製造方法
US5381599A (en) * 1993-04-12 1995-01-17 Delco Electronics Corp. Liquid crystal polymer encapsulated electronic devices and methods of making the same
US5714792A (en) * 1994-09-30 1998-02-03 Motorola, Inc. Semiconductor device having a reduced die support area and method for making the same
US5633785A (en) * 1994-12-30 1997-05-27 University Of Southern California Integrated circuit component package with integral passive component
JPH0964240A (ja) * 1995-08-25 1997-03-07 Toshiba Corp 半導体装置および半導体装置の製造方法
US5683944A (en) * 1995-09-01 1997-11-04 Motorola, Inc. Method of fabricating a thermally enhanced lead frame
US5859387A (en) * 1996-11-29 1999-01-12 Allegro Microsystems, Inc. Semiconductor device leadframe die attach pad having a raised bond pad
JP2915892B2 (ja) * 1997-06-27 1999-07-05 松下電子工業株式会社 樹脂封止型半導体装置およびその製造方法
US6861735B2 (en) * 1997-06-27 2005-03-01 Matsushita Electric Industrial Co., Ltd. Resin molded type semiconductor device and a method of manufacturing the same
TW393748B (en) * 1997-08-22 2000-06-11 Enomoto Kk Manufacturing of semiconductor devices and semiconductor lead frame
TW434760B (en) * 1998-02-20 2001-05-16 United Microelectronics Corp Interlaced grid type package structure and its manufacturing method
DE19808193B4 (de) * 1998-02-27 2007-11-08 Robert Bosch Gmbh Leadframevorrichtung und entsprechendes Herstellungsverfahren
JP3420057B2 (ja) * 1998-04-28 2003-06-23 株式会社東芝 樹脂封止型半導体装置
US6329705B1 (en) 1998-05-20 2001-12-11 Micron Technology, Inc. Leadframes including offsets extending from a major plane thereof, packaged semiconductor devices including same, and method of designing and fabricating such leadframes
JP2000031343A (ja) * 1998-07-09 2000-01-28 Texas Instr Japan Ltd 半導体装置
JP4349541B2 (ja) 2000-05-09 2009-10-21 大日本印刷株式会社 樹脂封止型半導体装置用フレーム
US6583505B2 (en) * 2001-05-04 2003-06-24 Ixys Corporation Electrically isolated power device package
DE10339939B4 (de) * 2003-08-29 2010-02-11 Infineon Technologies Ag Intergierte Schaltungsanordnung und Verfahren zur Herstellung und Beurteilung derselben
DE102006045415A1 (de) * 2006-09-26 2008-04-03 Infineon Technologies Ag Bauelementanordnung mit einem Träger
JP2008085002A (ja) * 2006-09-27 2008-04-10 Sanyo Electric Co Ltd 半導体装置およびその製造方法
US8816482B2 (en) * 2007-12-11 2014-08-26 United Test And Assembly Center Ltd. Flip-chip leadframe semiconductor package
JP2011023458A (ja) * 2009-07-14 2011-02-03 Toshiba Corp 半導体装置およびその製造方法
DE102011083002A1 (de) * 2011-09-20 2013-03-21 Robert Bosch Gmbh Elektrisches Steuergerät mit Moldgehäuse
DE102013217892A1 (de) * 2012-12-20 2014-06-26 Continental Teves Ag & Co. Ohg Elektronische Vorrichtung und Verfahren zur Herstellung einer elektronischen Vorrichtung
US9978669B2 (en) * 2016-06-30 2018-05-22 Nxp Usa, Inc. Packaged semiconductor device having a lead frame and inner and outer leads and method for forming
US10566269B2 (en) * 2017-12-18 2020-02-18 Texas Instruments Incorporated Low stress integrated circuit package
US20220221353A1 (en) * 2021-01-12 2022-07-14 Texas Instruments Incorporated Semiconductor force sensors

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JPS61102054A (ja) * 1984-10-25 1986-05-20 Toshiba Corp リ−ドフレ−ム
JPS61108160A (ja) * 1984-11-01 1986-05-26 Nec Corp コンデンサ内蔵型半導体装置及びその製造方法
JP2596542B2 (ja) * 1986-05-12 1997-04-02 株式会社日立製作所 リードフレームおよびそれを用いた半導体装置
US4816427A (en) * 1986-09-02 1989-03-28 Dennis Richard K Process for connecting lead frame to semiconductor device
EP0261324A1 (de) * 1986-09-26 1988-03-30 Texas Instruments Incorporated Plastikhülle für integrierte Schaltung in Form eines grossen Chips

Also Published As

Publication number Publication date
US4994895A (en) 1991-02-19
EP0350833A2 (de) 1990-01-17
EP0350833B1 (de) 1995-10-04
EP0350833A3 (de) 1991-11-27
DE68924452T2 (de) 1996-03-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: SHINKO ELECTRIC INDUSTRIES CO. LTD., NAGANO, JP

8339 Ceased/non-payment of the annual fee