DE69017140D1 - Isolation für integrierte Schaltungsanordnung. - Google Patents

Isolation für integrierte Schaltungsanordnung.

Info

Publication number
DE69017140D1
DE69017140D1 DE69017140T DE69017140T DE69017140D1 DE 69017140 D1 DE69017140 D1 DE 69017140D1 DE 69017140 T DE69017140 T DE 69017140T DE 69017140 T DE69017140 T DE 69017140T DE 69017140 D1 DE69017140 D1 DE 69017140D1
Authority
DE
Germany
Prior art keywords
isolation
integrated circuit
circuit arrangement
arrangement
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69017140T
Other languages
English (en)
Other versions
DE69017140T2 (de
Inventor
Larry Bruce Fritzinger
Kuo-Hua Lee
Chih-Yuan Lu
Janmye Sung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Publication of DE69017140D1 publication Critical patent/DE69017140D1/de
Application granted granted Critical
Publication of DE69017140T2 publication Critical patent/DE69017140T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
DE69017140T 1989-10-19 1990-10-10 Isolation für integrierte Schaltungsanordnung. Expired - Fee Related DE69017140T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/423,992 US5002898A (en) 1989-10-19 1989-10-19 Integrated-circuit device isolation

Publications (2)

Publication Number Publication Date
DE69017140D1 true DE69017140D1 (de) 1995-03-30
DE69017140T2 DE69017140T2 (de) 1995-06-14

Family

ID=23681028

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69017140T Expired - Fee Related DE69017140T2 (de) 1989-10-19 1990-10-10 Isolation für integrierte Schaltungsanordnung.

Country Status (4)

Country Link
US (1) US5002898A (de)
EP (1) EP0424011B1 (de)
JP (1) JPH0748491B2 (de)
DE (1) DE69017140T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5106772A (en) * 1990-01-09 1992-04-21 Intel Corporation Method for improving the electrical erase characteristics of floating gate memory cells by immediately depositing a protective polysilicon layer following growth of the tunnel or gate oxide
US5102814A (en) * 1990-11-02 1992-04-07 Intel Corporation Method for improving device scalability of buried bit line flash EPROM devices having short reoxidation beaks and shallower junctions
US5248350A (en) * 1990-11-30 1993-09-28 Ncr Corporation Structure for improving gate oxide integrity for a semiconductor formed by a recessed sealed sidewall field oxidation process
US5192707A (en) * 1991-07-31 1993-03-09 Sgs-Thomson Microelectronics, Inc. Method of forming isolated regions of oxide
US5215930A (en) * 1991-10-23 1993-06-01 At&T Bell Laboratories Integrated circuit etching of silicon nitride and polysilicon using phosphoric acid
US5310457A (en) * 1992-09-30 1994-05-10 At&T Bell Laboratories Method of integrated circuit fabrication including selective etching of silicon and silicon compounds
US5338750A (en) * 1992-11-27 1994-08-16 Industrial Technology Research Institute Fabrication method to produce pit-free polysilicon buffer local oxidation isolation
US5397732A (en) * 1993-07-22 1995-03-14 Industrial Technology Research Institute PBLOCOS with sandwiched thin silicon nitride layer
KR0148602B1 (ko) * 1994-11-23 1998-12-01 양승택 반도체 장치의 소자 격리방법
US5696020A (en) * 1994-11-23 1997-12-09 Electronics And Telecommunications Research Institute Method for fabricating semiconductor device isolation region using a trench mask
US5607543A (en) * 1995-04-28 1997-03-04 Lucent Technologies Inc. Integrated circuit etching
US6087241A (en) * 1997-09-05 2000-07-11 Microchip Technology Incorporated Method of forming side dielectrically isolated semiconductor devices and MOS semiconductor devices fabricated by this method
CN111276389A (zh) * 2020-02-14 2020-06-12 上海华虹宏力半导体制造有限公司 Bcd工艺中形成衬垫氧化层的方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5776856A (en) * 1980-10-30 1982-05-14 Toshiba Corp Manufacture of semiconductor device
US4407696A (en) * 1982-12-27 1983-10-04 Mostek Corporation Fabrication of isolation oxidation for MOS circuit
US4570325A (en) * 1983-12-16 1986-02-18 Kabushiki Kaisha Toshiba Manufacturing a field oxide region for a semiconductor device
US4541167A (en) * 1984-01-12 1985-09-17 Texas Instruments Incorporated Method for integrated circuit device isolation
US4630356A (en) * 1985-09-19 1986-12-23 International Business Machines Corporation Method of forming recessed oxide isolation with reduced steepness of the birds' neck
JPS62290146A (ja) * 1986-06-09 1987-12-17 Toshiba Corp 半導体装置の製造方法
JPS63137457A (ja) * 1986-11-28 1988-06-09 Fujitsu Ltd 半導体装置の製造方法
JP2775765B2 (ja) * 1988-09-02 1998-07-16 ソニー株式会社 半導体装置の製造法

Also Published As

Publication number Publication date
EP0424011B1 (de) 1995-02-22
EP0424011A3 (en) 1993-03-10
US5002898A (en) 1991-03-26
JPH03145730A (ja) 1991-06-20
DE69017140T2 (de) 1995-06-14
EP0424011A2 (de) 1991-04-24
JPH0748491B2 (ja) 1995-05-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee