DE68916784D1 - Integrierte Schaltungspackung. - Google Patents

Integrierte Schaltungspackung.

Info

Publication number
DE68916784D1
DE68916784D1 DE68916784T DE68916784T DE68916784D1 DE 68916784 D1 DE68916784 D1 DE 68916784D1 DE 68916784 T DE68916784 T DE 68916784T DE 68916784 T DE68916784 T DE 68916784T DE 68916784 D1 DE68916784 D1 DE 68916784D1
Authority
DE
Germany
Prior art keywords
integrated circuit
circuit pack
pack
integrated
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68916784T
Other languages
English (en)
Other versions
DE68916784T2 (de
Inventor
Helmut Dipl Ing Schettler
Thomas Dipl Ing Ludwig
Otto M Dipl-Ing Wagner
Werner O Dipl Ing Haug
Erich Klink
Karl E Dipl-Phys Kroell
Rainer Dipl Ing Stahl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE68916784D1 publication Critical patent/DE68916784D1/de
Application granted granted Critical
Publication of DE68916784T2 publication Critical patent/DE68916784T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/916—Narrow band gap semiconductor material, <<1ev
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/901—Capacitive junction

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
DE68916784T 1989-04-20 1989-04-20 Integrierte Schaltungspackung. Expired - Fee Related DE68916784T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP89107094A EP0393220B1 (de) 1989-04-20 1989-04-20 Integrierte Schaltungspackung

Publications (2)

Publication Number Publication Date
DE68916784D1 true DE68916784D1 (de) 1994-08-18
DE68916784T2 DE68916784T2 (de) 1995-01-05

Family

ID=8201258

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68916784T Expired - Fee Related DE68916784T2 (de) 1989-04-20 1989-04-20 Integrierte Schaltungspackung.

Country Status (4)

Country Link
US (2) US5016087A (de)
EP (1) EP0393220B1 (de)
JP (1) JPH0362934A (de)
DE (1) DE68916784T2 (de)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5354695A (en) * 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
US5216280A (en) * 1989-12-02 1993-06-01 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device having pads at periphery of semiconductor chip
JP2960560B2 (ja) * 1991-02-28 1999-10-06 株式会社日立製作所 超小型電子機器
US5434453A (en) * 1991-04-26 1995-07-18 Hitachi, Ltd. Semiconductor integrated circuit device and computer system using the same
KR930008891A (ko) * 1991-10-30 1993-05-22 정몽헌 온-칩 디카플링 캐패시터 구성방법
JPH05183019A (ja) * 1991-12-27 1993-07-23 Hitachi Ltd 半導体装置およびその製造方法
US5404265A (en) * 1992-08-28 1995-04-04 Fujitsu Limited Interconnect capacitors
KR0170456B1 (ko) * 1993-07-16 1999-03-30 세끼사와 다까시 반도체 장치 및 그 제조방법
US5341979A (en) * 1993-09-03 1994-08-30 Motorola, Inc. Method of bonding a semiconductor substrate to a support substrate and structure therefore
US5371403A (en) * 1993-09-24 1994-12-06 Vlsi Technology, Inc. High performance package using high dielectric constant materials for power/ground and low dielectric constant materials for signal lines
US5661336A (en) * 1994-05-03 1997-08-26 Phelps, Jr.; Douglas Wallace Tape application platform and processes therefor
US5534465A (en) * 1995-01-10 1996-07-09 At&T Corp. Method for making multichip circuits using active semiconductor substrates
JP3160198B2 (ja) * 1995-02-08 2001-04-23 インターナショナル・ビジネス・マシーンズ・コーポレ−ション デカップリング・コンデンサが形成された半導体基板及びこれの製造方法
US5620927A (en) * 1995-05-25 1997-04-15 National Semiconductor Corporation Solder ball attachment machine for semiconductor packages
US6111317A (en) * 1996-01-18 2000-08-29 Kabushiki Kaisha Toshiba Flip-chip connection type semiconductor integrated circuit device
US5643818A (en) * 1996-05-02 1997-07-01 International Business Machines Corporation Removal of residues from metallic insert used in manufacture of multi-layer ceramic substrate with cavity for microelectronic chip
US5811868A (en) * 1996-12-20 1998-09-22 International Business Machines Corp. Integrated high-performance decoupling capacitor
TW448524B (en) * 1997-01-17 2001-08-01 Seiko Epson Corp Electronic component, semiconductor device, manufacturing method therefor, circuit board and electronic equipment
US6015955A (en) 1997-06-20 2000-01-18 International Business Machines Corporation Reworkability solution for wirebound chips using high performance capacitor
US6118180A (en) * 1997-11-03 2000-09-12 Lsi Logic Corporation Semiconductor die metal layout for flip chip packaging
US6385565B1 (en) * 1998-06-18 2002-05-07 Sun Microsystems, Inc. System and method for determining the desired decoupling components for power distribution systems using a computer system
US6532439B2 (en) 1998-06-18 2003-03-11 Sun Microsystems, Inc. Method for determining the desired decoupling components for power distribution systems
KR100294449B1 (ko) * 1998-07-15 2001-07-12 윤종용 본딩패드하부에형성되는커패시터를구비한반도체집적회로장치
JP2000100814A (ja) * 1998-09-18 2000-04-07 Hitachi Ltd 半導体装置
US6495442B1 (en) 2000-10-18 2002-12-17 Magic Corporation Post passivation interconnection schemes on top of the IC chips
US6600364B1 (en) * 1999-01-05 2003-07-29 Intel Corporation Active interposer technology for high performance CMOS packaging application
US6137161A (en) * 1999-09-14 2000-10-24 International Business Machines Corporation Interposer array module for capacitive decoupling and filtering
JP2001217242A (ja) * 2000-02-03 2001-08-10 Seiko Epson Corp 半導体装置およびその製造方法
US6827325B2 (en) * 2000-08-28 2004-12-07 Johnson & Johnson Vision Care, Inc. Shape memory polymer or alloy ophthalmic lens mold and methods of forming ophthalmic products
JP2004055628A (ja) * 2002-07-17 2004-02-19 Dainippon Printing Co Ltd ウエハレベルの半導体装置及びその作製方法
US6789241B2 (en) * 2002-10-31 2004-09-07 Sun Microsystems, Inc. Methodology for determining the placement of decoupling capacitors in a power distribution system
US7435627B2 (en) * 2005-08-11 2008-10-14 International Business Machines Corporation Techniques for providing decoupling capacitance
EP2291701A4 (de) * 2008-06-16 2013-11-06 Hardisty Optical Group Llc Nasenauflage für lichtstreuungsbrille
JP5102726B2 (ja) * 2008-09-08 2012-12-19 ラピスセミコンダクタ株式会社 半導体装置の製造方法
US8497564B2 (en) * 2009-08-13 2013-07-30 Broadcom Corporation Method for fabricating a decoupling composite capacitor in a wafer and related structure

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1487945A (en) * 1974-11-20 1977-10-05 Ibm Semiconductor integrated circuit devices
US4453176A (en) * 1981-12-31 1984-06-05 International Business Machines Corporation LSI Chip carrier with buried repairable capacitor with low inductance leads
JPS58158958A (ja) * 1982-03-16 1983-09-21 Seiko Epson Corp 複合型固体装置
NL8202470A (nl) * 1982-06-18 1984-01-16 Philips Nv Hoogfrequentschakelinrichting en halfgeleiderinrichting voor toepassing in een dergelijke inrichting.
US4616655A (en) * 1984-01-20 1986-10-14 Cordis Corporation Implantable pulse generator having a single printed circuit board and a chip carrier
EP0172889A1 (de) * 1984-02-17 1986-03-05 AT&T Corp. Zusammenbau mit integriertem schaltungschip
US4675717A (en) * 1984-10-09 1987-06-23 American Telephone And Telegraph Company, At&T Bell Laboratories Water-scale-integrated assembly
JPS60220939A (ja) * 1985-03-20 1985-11-05 Hitachi Ltd 半導体集積回路装置
JPS6272144A (ja) * 1985-09-25 1987-04-02 Toshiba Corp 半導体装置
US4866507A (en) * 1986-05-19 1989-09-12 International Business Machines Corporation Module for packaging semiconductor integrated circuit chips on a base substrate

Also Published As

Publication number Publication date
EP0393220B1 (de) 1994-07-13
US5162264A (en) 1992-11-10
EP0393220A1 (de) 1990-10-24
US5016087A (en) 1991-05-14
DE68916784T2 (de) 1995-01-05
JPH0362934A (ja) 1991-03-19
JPH0587977B2 (de) 1993-12-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee