DE69710248D1 - Bondverfahren für integrierte Schaltung - Google Patents
Bondverfahren für integrierte SchaltungInfo
- Publication number
- DE69710248D1 DE69710248D1 DE69710248T DE69710248T DE69710248D1 DE 69710248 D1 DE69710248 D1 DE 69710248D1 DE 69710248 T DE69710248 T DE 69710248T DE 69710248 T DE69710248 T DE 69710248T DE 69710248 D1 DE69710248 D1 DE 69710248D1
- Authority
- DE
- Germany
- Prior art keywords
- integrated circuit
- bonding process
- bonding
- integrated
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01051—Antimony [Sb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01061—Promethium [Pm]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/906—Cleaning of wafer as interim step
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US64158596A | 1996-05-01 | 1996-05-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69710248D1 true DE69710248D1 (de) | 2002-03-21 |
DE69710248T2 DE69710248T2 (de) | 2002-08-14 |
Family
ID=24572998
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69710248T Expired - Fee Related DE69710248T2 (de) | 1996-05-01 | 1997-04-22 | Bondverfahren für integrierte Schaltung |
Country Status (7)
Country | Link |
---|---|
US (1) | US6074897A (de) |
EP (1) | EP0805486B1 (de) |
JP (1) | JP3215651B2 (de) |
KR (1) | KR970077381A (de) |
CA (1) | CA2198305A1 (de) |
DE (1) | DE69710248T2 (de) |
TW (1) | TW415057B (de) |
Families Citing this family (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1154658A (ja) * | 1997-07-30 | 1999-02-26 | Hitachi Ltd | 半導体装置及びその製造方法並びにフレーム構造体 |
US6057178A (en) * | 1997-09-26 | 2000-05-02 | Siemens Aktiengesellschaft | Method of padding an electronic component, mounted on a flat substrate, with a liquid filler |
US6495083B2 (en) | 1997-10-29 | 2002-12-17 | Hestia Technologies, Inc. | Method of underfilling an integrated circuit chip |
US6324069B1 (en) | 1997-10-29 | 2001-11-27 | Hestia Technologies, Inc. | Chip package with molded underfill |
US6549105B2 (en) | 1998-06-02 | 2003-04-15 | Matsushita Electric Industrial Co., Ltd. | Millimeter wave module and radio apparatus |
US6778041B2 (en) * | 1998-06-02 | 2004-08-17 | Matsushita Electric Industrial Co., Ltd. | Millimeter wave module and radio apparatus |
JP3331967B2 (ja) * | 1998-06-02 | 2002-10-07 | 松下電器産業株式会社 | ミリ波モジュール |
US6490166B1 (en) * | 1999-06-11 | 2002-12-03 | Intel Corporation | Integrated circuit package having a substrate vent hole |
JP2001044137A (ja) | 1999-08-04 | 2001-02-16 | Hitachi Ltd | 電子装置及びその製造方法 |
US6395097B1 (en) * | 1999-12-16 | 2002-05-28 | Lsi Logic Corporation | Method and apparatus for cleaning and removing flux from an electronic component package |
US6979595B1 (en) * | 2000-08-24 | 2005-12-27 | Micron Technology, Inc. | Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices |
US6734540B2 (en) * | 2000-10-11 | 2004-05-11 | Altera Corporation | Semiconductor package with stress inhibiting intermediate mounting substrate |
US7115986B2 (en) * | 2001-05-02 | 2006-10-03 | Micron Technology, Inc. | Flexible ball grid array chip scale packages |
SG122743A1 (en) * | 2001-08-21 | 2006-06-29 | Micron Technology Inc | Microelectronic devices and methods of manufacture |
SG104293A1 (en) | 2002-01-09 | 2004-06-21 | Micron Technology Inc | Elimination of rdl using tape base flip chip on flex for die stacking |
SG111935A1 (en) * | 2002-03-04 | 2005-06-29 | Micron Technology Inc | Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods |
SG121707A1 (en) * | 2002-03-04 | 2006-05-26 | Micron Technology Inc | Method and apparatus for flip-chip packaging providing testing capability |
US6975035B2 (en) * | 2002-03-04 | 2005-12-13 | Micron Technology, Inc. | Method and apparatus for dielectric filling of flip chip on interposer assembly |
SG115455A1 (en) | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Methods for assembly and packaging of flip chip configured dice with interposer |
SG115459A1 (en) * | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Flip chip packaging using recessed interposer terminals |
SG115456A1 (en) | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Semiconductor die packages with recessed interconnecting structures and methods for assembling the same |
US20040036170A1 (en) * | 2002-08-20 | 2004-02-26 | Lee Teck Kheng | Double bumping of flexible substrate for first and second level interconnects |
JP2004103996A (ja) | 2002-09-12 | 2004-04-02 | Nec Semiconductors Kyushu Ltd | フリップチップbga型半導体装置 |
FR2856517B1 (fr) * | 2003-06-17 | 2005-09-23 | St Microelectronics Sa | Procede de fabrication de composant semi-conducteur et composant semi-conducteur |
KR100541395B1 (ko) * | 2003-09-09 | 2006-01-11 | 삼성전자주식회사 | 반도체칩 적층장치, 이것을 이용한 반도체 패키지의제조방법, 그리고 이러한 방법에 의하여 제조된 반도체패키지 |
US7124931B2 (en) * | 2003-11-18 | 2006-10-24 | Intel Corporation | Via heat sink material |
US6979600B2 (en) * | 2004-01-06 | 2005-12-27 | Intel Corporation | Apparatus and methods for an underfilled integrated circuit package |
US7407085B2 (en) * | 2004-09-22 | 2008-08-05 | Intel Corporation | Apparatus and method for attaching a semiconductor die to a heat spreader |
US7220622B2 (en) * | 2004-09-22 | 2007-05-22 | Intel Corporation | Method for attaching a semiconductor die to a substrate and heat spreader |
US20060099736A1 (en) * | 2004-11-09 | 2006-05-11 | Nagar Mohan R | Flip chip underfilling |
US20060225851A1 (en) * | 2005-04-06 | 2006-10-12 | Hsien-Hsin Chiu | Chip washing apparatus |
US20060234427A1 (en) * | 2005-04-19 | 2006-10-19 | Odegard Charles A | Underfill dispense at substrate aperture |
WO2007015683A1 (en) * | 2005-08-04 | 2007-02-08 | Infineon Technologies Ag | An integrated circuit package and a method for forming an integrated circuit package |
KR100749624B1 (ko) * | 2005-12-28 | 2007-08-14 | 삼성에스디아이 주식회사 | 플라즈마 디스플레이 장치 |
US7592702B2 (en) * | 2006-07-31 | 2009-09-22 | Intel Corporation | Via heat sink material |
JP2009164431A (ja) * | 2008-01-08 | 2009-07-23 | Fujitsu Microelectronics Ltd | 半導体装置の製造方法、半導体装置の洗浄方法および洗浄装置 |
TW201207961A (en) * | 2010-08-04 | 2012-02-16 | Global Unichip Corp | Semiconductor package device using underfill material and packaging method thereof |
US9390945B2 (en) * | 2012-05-08 | 2016-07-12 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of depositing underfill material with uniform flow rate |
KR101211167B1 (ko) * | 2012-05-17 | 2012-12-11 | (주)드림텍 | 잔류용제 배출부를 갖는 기판 및 표면실장 패키지 |
US9184067B1 (en) | 2013-09-27 | 2015-11-10 | Stats Chippac Ltd. | Methods of mitigating defects for semiconductor packages |
US9917068B2 (en) | 2014-03-14 | 2018-03-13 | Taiwan Semiconductor Manufacturing Company | Package substrates, packaged semiconductor devices, and methods of packaging semiconductor devices |
US9362243B2 (en) * | 2014-05-21 | 2016-06-07 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package device and forming the same |
KR102437774B1 (ko) * | 2015-11-17 | 2022-08-30 | 삼성전자주식회사 | 인쇄 회로 기판 |
CN113065416B (zh) * | 2021-03-16 | 2024-07-05 | 深圳供电局有限公司 | 集成于变电站视频监控装置的渗漏监测装置及方法、介质 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4143456A (en) * | 1976-06-28 | 1979-03-13 | Citizen Watch Commpany Ltd. | Semiconductor device insulation method |
US4320047A (en) * | 1980-11-13 | 1982-03-16 | The B. F. Goodrich Company | Curable thixotropic epoxy/amine terminated liquid polymer compositions |
JPS61161743A (ja) * | 1985-01-11 | 1986-07-22 | Seiko Epson Corp | Ic実装構造 |
US5656862A (en) * | 1990-03-14 | 1997-08-12 | International Business Machines Corporation | Solder interconnection structure |
US5218234A (en) * | 1991-12-23 | 1993-06-08 | Motorola, Inc. | Semiconductor device with controlled spread polymeric underfill |
US5311059A (en) * | 1992-01-24 | 1994-05-10 | Motorola, Inc. | Backplane grounding for flip-chip integrated circuit |
US5211764A (en) * | 1992-11-10 | 1993-05-18 | At&T Bell Laboratories | Solder paste and method of using the same |
JP2962385B2 (ja) * | 1993-01-07 | 1999-10-12 | 松下電子工業株式会社 | 半導体装置の製造方法 |
US5477611A (en) * | 1993-09-20 | 1995-12-26 | Tessera, Inc. | Method of forming interface between die and chip carrier |
US5385290A (en) * | 1993-11-24 | 1995-01-31 | At&T Corp. | Soldering material and procedure |
US5534078A (en) * | 1994-01-27 | 1996-07-09 | Breunsbach; Rex | Method for cleaning electronic assemblies |
US5455390A (en) * | 1994-02-01 | 1995-10-03 | Tessera, Inc. | Microelectronics unit mounting with multiple lead bonding |
US5710071A (en) * | 1995-12-04 | 1998-01-20 | Motorola, Inc. | Process for underfilling a flip-chip semiconductor device |
US5855821A (en) * | 1995-12-22 | 1999-01-05 | Johnson Matthey, Inc. | Materials for semiconductor device assemblies |
-
1997
- 1997-02-24 CA CA002198305A patent/CA2198305A1/en not_active Abandoned
- 1997-03-03 TW TW086102508A patent/TW415057B/zh not_active IP Right Cessation
- 1997-04-22 EP EP97302752A patent/EP0805486B1/de not_active Expired - Lifetime
- 1997-04-22 DE DE69710248T patent/DE69710248T2/de not_active Expired - Fee Related
- 1997-04-28 JP JP11067997A patent/JP3215651B2/ja not_active Expired - Fee Related
- 1997-04-30 KR KR1019970016691A patent/KR970077381A/ko not_active Application Discontinuation
-
1999
- 1999-01-28 US US09/238,706 patent/US6074897A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH1041350A (ja) | 1998-02-13 |
JP3215651B2 (ja) | 2001-10-09 |
EP0805486B1 (de) | 2002-02-06 |
EP0805486A1 (de) | 1997-11-05 |
KR970077381A (ko) | 1997-12-12 |
CA2198305A1 (en) | 1997-11-02 |
US6074897A (en) | 2000-06-13 |
TW415057B (en) | 2000-12-11 |
DE69710248T2 (de) | 2002-08-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8339 | Ceased/non-payment of the annual fee |