DE69839906D1 - Herstellungsverfahren für eine integrierte Schaltung - Google Patents

Herstellungsverfahren für eine integrierte Schaltung

Info

Publication number
DE69839906D1
DE69839906D1 DE69839906T DE69839906T DE69839906D1 DE 69839906 D1 DE69839906 D1 DE 69839906D1 DE 69839906 T DE69839906 T DE 69839906T DE 69839906 T DE69839906 T DE 69839906T DE 69839906 D1 DE69839906 D1 DE 69839906D1
Authority
DE
Germany
Prior art keywords
manufacturing
integrated circuit
integrated
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69839906T
Other languages
English (en)
Inventor
Sunil V Hattangady
George R Misium
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE69839906D1 publication Critical patent/DE69839906D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE69839906T 1997-10-22 1998-10-22 Herstellungsverfahren für eine integrierte Schaltung Expired - Lifetime DE69839906D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US6262797P 1997-10-22 1997-10-22

Publications (1)

Publication Number Publication Date
DE69839906D1 true DE69839906D1 (de) 2008-10-02

Family

ID=22043747

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69839906T Expired - Lifetime DE69839906D1 (de) 1997-10-22 1998-10-22 Herstellungsverfahren für eine integrierte Schaltung

Country Status (4)

Country Link
US (1) US5970345A (de)
EP (1) EP0921564B1 (de)
AU (1) AU750612B2 (de)
DE (1) DE69839906D1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6261978B1 (en) * 1999-02-22 2001-07-17 Motorola, Inc. Process for forming semiconductor device with thick and thin films
US6297082B1 (en) * 1999-08-25 2001-10-02 United Microelectronics Corp. Method of fabricating a MOS transistor with local channel ion implantation regions
US6262455B1 (en) * 1999-11-02 2001-07-17 Philips Semiconductor, Inc. Method of forming dual gate oxide layers of varying thickness on a single substrate
US6147008A (en) * 1999-11-19 2000-11-14 Chartered Semiconductor Manufacturing Ltd. Creation of multiple gate oxide with high thickness ratio in flash memory process
US6686298B1 (en) 2000-06-22 2004-02-03 Micron Technology, Inc. Methods of forming structures over semiconductor substrates, and methods of forming transistors associated with semiconductor substrates
US6833329B1 (en) 2000-06-22 2004-12-21 Micron Technology, Inc. Methods of forming oxide regions over semiconductor substrates
US6649543B1 (en) * 2000-06-22 2003-11-18 Micron Technology, Inc. Methods of forming silicon nitride, methods of forming transistor devices, and transistor devices
US6268251B1 (en) * 2000-07-12 2001-07-31 Chartered Semiconductor Manufacturing Inc. Method of forming MOS/CMOS devices with dual or triple gate oxide
US6660657B1 (en) 2000-08-07 2003-12-09 Micron Technology, Inc. Methods of incorporating nitrogen into silicon-oxide-containing layers
US6878585B2 (en) 2001-08-29 2005-04-12 Micron Technology, Inc. Methods of forming capacitors
US6723599B2 (en) 2001-12-03 2004-04-20 Micron Technology, Inc. Methods of forming capacitors and methods of forming capacitor dielectric layers
KR100417461B1 (ko) * 2002-07-12 2004-02-05 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US6670248B1 (en) 2002-08-07 2003-12-30 Chartered Semiconductor Manufacturing Ltd. Triple gate oxide process with high-k gate dielectric
US6846714B1 (en) * 2002-10-03 2005-01-25 Lattice Semiconductor Corporation Voltage limited EEPROM device and process for fabricating the device
KR101092317B1 (ko) * 2009-04-10 2011-12-09 주식회사 하이닉스반도체 반도체 소자의 제조방법
CN104952734B (zh) * 2015-07-16 2020-01-24 矽力杰半导体技术(杭州)有限公司 半导体结构及其制造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4851370A (en) * 1987-12-28 1989-07-25 American Telephone And Telegraph Company, At&T Bell Laboratories Fabricating a semiconductor device with low defect density oxide
JPH07183409A (ja) * 1993-12-24 1995-07-21 Seiko Epson Corp 半導体装置とその製造方法
US5665620A (en) * 1994-08-01 1997-09-09 Motorola, Inc. Method for forming concurrent top oxides using reoxidized silicon in an EPROM
TW344897B (en) * 1994-11-30 1998-11-11 At&T Tcorporation A process for forming gate oxides possessing different thicknesses on a semiconductor substrate
JP3243151B2 (ja) * 1995-06-01 2002-01-07 東芝マイクロエレクトロニクス株式会社 半導体装置の製造方法
DE69528970D1 (de) * 1995-06-30 2003-01-09 St Microelectronics Srl Herstellungsverfahren eines Schaltkreises, der nichtflüchtige Speicherzellen und Randtransistoren enthält, und entsprechender IC

Also Published As

Publication number Publication date
EP0921564B1 (de) 2008-08-20
AU8945198A (en) 1999-05-13
EP0921564A1 (de) 1999-06-09
US5970345A (en) 1999-10-19
AU750612B2 (en) 2002-07-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition