DE69611632D1 - Planare Isolation für integrierte Schaltungen - Google Patents

Planare Isolation für integrierte Schaltungen

Info

Publication number
DE69611632D1
DE69611632D1 DE69611632T DE69611632T DE69611632D1 DE 69611632 D1 DE69611632 D1 DE 69611632D1 DE 69611632 T DE69611632 T DE 69611632T DE 69611632 T DE69611632 T DE 69611632T DE 69611632 D1 DE69611632 D1 DE 69611632D1
Authority
DE
Germany
Prior art keywords
integrated circuits
planar insulation
planar
insulation
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69611632T
Other languages
English (en)
Other versions
DE69611632T2 (de
Inventor
Philippe Gayet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Application granted granted Critical
Publication of DE69611632D1 publication Critical patent/DE69611632D1/de
Publication of DE69611632T2 publication Critical patent/DE69611632T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
DE69611632T 1995-05-19 1996-05-15 Planare Isolation für integrierte Schaltungen Expired - Fee Related DE69611632T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9506266A FR2734403B1 (fr) 1995-05-19 1995-05-19 Isolement plan dans des circuits integres

Publications (2)

Publication Number Publication Date
DE69611632D1 true DE69611632D1 (de) 2001-03-01
DE69611632T2 DE69611632T2 (de) 2001-08-16

Family

ID=9479395

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69611632T Expired - Fee Related DE69611632T2 (de) 1995-05-19 1996-05-15 Planare Isolation für integrierte Schaltungen

Country Status (5)

Country Link
US (2) US5736451A (de)
EP (1) EP0743678B1 (de)
JP (1) JPH08330299A (de)
DE (1) DE69611632T2 (de)
FR (1) FR2734403B1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5895257A (en) * 1996-08-01 1999-04-20 Taiwan Semiconductor Manfacturing Company, Ltd. LOCOS field oxide and field oxide process using silicon nitride spacers
US5923991A (en) * 1996-11-05 1999-07-13 International Business Machines Corporation Methods to prevent divot formation in shallow trench isolation areas
US5897356A (en) * 1997-02-27 1999-04-27 Micron Technology, Inc. Methods of forming field oxide and active area regions on a semiconductive substrate
JP3751469B2 (ja) * 1999-04-26 2006-03-01 沖電気工業株式会社 Ｓｏｉ構造の半導体装置の製造方法
US6440818B1 (en) * 2001-04-10 2002-08-27 United Microelectronics Corp. Method of reducing leakage current of a semiconductor wafer
JP4054557B2 (ja) * 2001-10-10 2008-02-27 沖電気工業株式会社 半導体素子の製造方法
US6960510B2 (en) * 2002-07-01 2005-11-01 International Business Machines Corporation Method of making sub-lithographic features
JP2005332996A (ja) * 2004-05-20 2005-12-02 Oki Electric Ind Co Ltd 半導体装置、及びその製造方法
US7851362B2 (en) 2008-02-11 2010-12-14 Infineon Technologies Ag Method for reducing an unevenness of a surface and method for making a semiconductor device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61226942A (ja) * 1985-04-01 1986-10-08 Matsushita Electronics Corp 半導体集積回路の素子間分離方法
NL8501720A (nl) * 1985-06-14 1987-01-02 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij een siliciumplak plaatselijk wordt voorzien van veldoxide met kanaalonderbreker.
JPH01220467A (ja) * 1988-02-29 1989-09-04 Nec Corp 半導体集積回路装置
US5118641A (en) * 1990-09-13 1992-06-02 Micron Technology, Inc. Methods for reducing encroachment of the field oxide into the active area on a silicon integrated circuit
US5372951A (en) * 1993-10-01 1994-12-13 Advanced Micro Devices, Inc. Method of making a semiconductor having selectively enhanced field oxide areas
US5374585A (en) * 1994-05-09 1994-12-20 Motorola, Inc. Process for forming field isolation
US5554560A (en) * 1994-09-30 1996-09-10 United Microelectronics Corporation Method for forming a planar field oxide (fox) on substrates for integrated circuit
US6008526A (en) * 1995-05-30 1999-12-28 Samsung Electronics Co., Ltd. Device isolation layer for a semiconductor device

Also Published As

Publication number Publication date
EP0743678A1 (de) 1996-11-20
JPH08330299A (ja) 1996-12-13
FR2734403B1 (fr) 1997-08-01
FR2734403A1 (fr) 1996-11-22
DE69611632T2 (de) 2001-08-16
US5736451A (en) 1998-04-07
EP0743678B1 (de) 2001-01-24
US6525393B1 (en) 2003-02-25

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee