DE69600633T2 - Eingangsschaltung für Halbleiterspeicher - Google Patents

Eingangsschaltung für Halbleiterspeicher

Info

Publication number
DE69600633T2
DE69600633T2 DE69600633T DE69600633T DE69600633T2 DE 69600633 T2 DE69600633 T2 DE 69600633T2 DE 69600633 T DE69600633 T DE 69600633T DE 69600633 T DE69600633 T DE 69600633T DE 69600633 T2 DE69600633 T2 DE 69600633T2
Authority
DE
Germany
Prior art keywords
semiconductor memory
input circuit
input
circuit
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69600633T
Other languages
English (en)
Other versions
DE69600633D1 (de
Inventor
Shigeru Yamaoka
Yutaka Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE69600633D1 publication Critical patent/DE69600633D1/de
Application granted granted Critical
Publication of DE69600633T2 publication Critical patent/DE69600633T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
    • H03K19/01742—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
DE69600633T 1996-05-24 1996-10-30 Eingangsschaltung für Halbleiterspeicher Expired - Fee Related DE69600633T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12992196A JP3859766B2 (ja) 1996-05-24 1996-05-24 半導体記憶装置の入力回路

Publications (2)

Publication Number Publication Date
DE69600633D1 DE69600633D1 (de) 1998-10-15
DE69600633T2 true DE69600633T2 (de) 1999-03-18

Family

ID=15021704

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69600633T Expired - Fee Related DE69600633T2 (de) 1996-05-24 1996-10-30 Eingangsschaltung für Halbleiterspeicher

Country Status (7)

Country Link
US (1) US5894229A (de)
EP (1) EP0809249B1 (de)
JP (1) JP3859766B2 (de)
KR (1) KR100227059B1 (de)
CN (1) CN1101081C (de)
DE (1) DE69600633T2 (de)
TW (1) TW311300B (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6239620B1 (en) * 1999-11-29 2001-05-29 International Business Machines Corporation Method and apparatus for generating true/complement signals
US6753705B1 (en) * 2000-07-27 2004-06-22 Sigmatel, Inc. Edge sensitive detection circuit
JP3813538B2 (ja) 2001-11-28 2006-08-23 富士通株式会社 レベルシフタ
JP4145565B2 (ja) * 2002-05-17 2008-09-03 株式会社ルネサステクノロジ 半導体装置
JP4320413B2 (ja) * 2002-09-11 2009-08-26 日本電気株式会社 半導体集積回路およびレイアウト設計装置
DE10244516B4 (de) * 2002-09-25 2006-11-16 Infineon Technologies Ag Integrierte Schaltung mit einer Eingangsschaltung
KR102118570B1 (ko) 2018-03-08 2020-06-03 경창산업주식회사 캠을 이용한 페달 답력 발생장치

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2596595B1 (fr) * 1986-03-28 1988-05-13 Radiotechnique Compelec Porte logique mos du type domino
US4891792A (en) * 1987-09-04 1990-01-02 Hitachi, Ltd. Static type semiconductor memory with multi-stage sense amplifier
JPH01183217A (ja) * 1988-01-14 1989-07-21 Nec Corp 入力バッファ回路
EP0365720B1 (de) * 1988-10-24 1996-04-03 Kabushiki Kaisha Toshiba Programmierbarer Halbleiterspeicher
JPH02309810A (ja) * 1989-05-25 1990-12-25 Seiko Epson Corp 半導体装置
US5019724A (en) * 1989-12-20 1991-05-28 Sgs-Thomson Microelectronics, Inc. Noise tolerant input buffer
JPH03253114A (ja) * 1990-03-02 1991-11-12 Nec Corp 半導体装置
JPH04219012A (ja) * 1990-12-19 1992-08-10 Toshiba Corp 半導体集積回路
JP3055223B2 (ja) * 1991-07-04 2000-06-26 日本電気株式会社 バッファ回路
JP3055236B2 (ja) * 1991-08-27 2000-06-26 日本電気株式会社 入力回路
JP2737475B2 (ja) * 1991-08-29 1998-04-08 日本電気株式会社 半導体記憶装置
JPH05335898A (ja) * 1992-05-28 1993-12-17 Mitsubishi Electric Corp 入力バッファ回路
JPH06303123A (ja) * 1993-04-19 1994-10-28 Hitachi Ltd 半導体集積回路
US5467038A (en) * 1994-02-15 1995-11-14 Hewlett-Packard Company Quick resolving latch
US5459437A (en) * 1994-05-10 1995-10-17 Integrated Device Technology Logic gate with controllable hysteresis and high frequency voltage controlled oscillator
KR0179786B1 (ko) * 1995-12-23 1999-04-01 문정환 출력버퍼

Also Published As

Publication number Publication date
JPH09312096A (ja) 1997-12-02
CN1166725A (zh) 1997-12-03
EP0809249B1 (de) 1998-09-09
JP3859766B2 (ja) 2006-12-20
TW311300B (en) 1997-07-21
EP0809249A1 (de) 1997-11-26
DE69600633D1 (de) 1998-10-15
US5894229A (en) 1999-04-13
CN1101081C (zh) 2003-02-05
KR970076845A (ko) 1997-12-12
KR100227059B1 (ko) 1999-10-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee