DE69830878D1 - Integrierte Halbleiterschaltungsanordnung - Google Patents

Integrierte Halbleiterschaltungsanordnung

Info

Publication number
DE69830878D1
DE69830878D1 DE69830878T DE69830878T DE69830878D1 DE 69830878 D1 DE69830878 D1 DE 69830878D1 DE 69830878 T DE69830878 T DE 69830878T DE 69830878 T DE69830878 T DE 69830878T DE 69830878 D1 DE69830878 D1 DE 69830878D1
Authority
DE
Germany
Prior art keywords
circuit arrangement
semiconductor circuit
integrated semiconductor
integrated
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69830878T
Other languages
English (en)
Inventor
Taketo Maesako
Kouki Yamamoto
Yoshinori Matsui
Kenichi Sakakibara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
NEC Corp
Original Assignee
NEC Electronics Corp
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp, NEC Corp filed Critical NEC Electronics Corp
Application granted granted Critical
Publication of DE69830878D1 publication Critical patent/DE69830878D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
DE69830878T 1997-09-16 1998-09-11 Integrierte Halbleiterschaltungsanordnung Expired - Lifetime DE69830878D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29023397A JP3161383B2 (ja) 1997-09-16 1997-09-16 半導体記憶装置

Publications (1)

Publication Number Publication Date
DE69830878D1 true DE69830878D1 (de) 2005-08-25

Family

ID=17753486

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69830878T Expired - Lifetime DE69830878D1 (de) 1997-09-16 1998-09-11 Integrierte Halbleiterschaltungsanordnung

Country Status (7)

Country Link
US (1) US6339817B1 (de)
EP (1) EP0908888B1 (de)
JP (1) JP3161383B2 (de)
KR (1) KR100366838B1 (de)
CN (1) CN1144229C (de)
DE (1) DE69830878D1 (de)
TW (1) TW397990B (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3178423B2 (ja) 1998-07-03 2001-06-18 日本電気株式会社 バーチャルチャネルｓｄｒａｍ
JP3248617B2 (ja) 1998-07-14 2002-01-21 日本電気株式会社 半導体記憶装置
US6530045B1 (en) * 1999-12-03 2003-03-04 Micron Technology, Inc. Apparatus and method for testing rambus DRAMs
JP3871853B2 (ja) * 2000-05-26 2007-01-24 株式会社ルネサステクノロジ 半導体装置及びその動作方法
US6862654B1 (en) * 2000-08-17 2005-03-01 Micron Technology, Inc. Method and system for using dynamic random access memory as cache memory
US6779076B1 (en) 2000-10-05 2004-08-17 Micron Technology, Inc. Method and system for using dynamic random access memory as cache memory
US6452865B1 (en) * 2001-08-09 2002-09-17 International Business Machines Corporation Method and apparatus for supporting N-bit width DDR memory interface using a common symmetrical read data path with 2N-bit internal bus width
US7290109B2 (en) * 2002-01-09 2007-10-30 Renesas Technology Corp. Memory system and memory card
US7149824B2 (en) * 2002-07-10 2006-12-12 Micron Technology, Inc. Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction
JP2004192694A (ja) * 2002-12-10 2004-07-08 Renesas Technology Corp 半導体記憶装置
KR100582357B1 (ko) * 2003-12-29 2006-05-22 주식회사 하이닉스반도체 로우디코딩을 효율적으로 할 수 있는 태그블럭을 구비하는반도체 메모리 장치
KR100640783B1 (ko) * 2004-10-30 2006-11-01 주식회사 하이닉스반도체 노이즈를 줄일 수 있는 데이터 출력 드라이버
KR100660871B1 (ko) * 2005-07-15 2006-12-26 삼성전자주식회사 연결된 비트라인을 구비하는 반도체 메모리 장치 및 데이터쉬프팅 방법
US8246790B2 (en) 2007-10-23 2012-08-21 Lg Chem, Ltd. Method for collecting (meth)acrylic acid and apparatus for collecting (meth)acrylic acid
JP5390337B2 (ja) * 2009-10-26 2014-01-15 株式会社東芝 半導体記憶装置
US10365851B2 (en) 2015-03-12 2019-07-30 Micron Technology, Inc. Apparatuses and methods for data movement
US10048888B2 (en) 2016-02-10 2018-08-14 Micron Technology, Inc. Apparatuses and methods for partitioned parallel data movement
US10074416B2 (en) 2016-03-28 2018-09-11 Micron Technology, Inc. Apparatuses and methods for data movement
US10658026B2 (en) * 2017-05-26 2020-05-19 Taiwan Semiconductor Manufacturing Company Limited Word line pulse width control circuit in static random access memory
US11380372B1 (en) * 2020-12-17 2022-07-05 Micron Technology, Inc. Transferring data between DRAM and SRAM

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5720983A (en) 1980-07-15 1982-02-03 Hitachi Ltd Memory chip
JPH069114B2 (ja) 1983-06-24 1994-02-02 株式会社東芝 半導体メモリ
JPS6238590A (ja) 1985-08-13 1987-02-19 Fujitsu Ltd 半導体記憶装置
JPH01146187A (ja) 1987-12-02 1989-06-08 Mitsubishi Electric Corp キヤッシュメモリ内蔵半導体記憶装置
US4873665A (en) * 1988-06-07 1989-10-10 Dallas Semiconductor Corporation Dual storage cell memory including data transfer circuits
JP2938511B2 (ja) * 1990-03-30 1999-08-23 三菱電機株式会社 半導体記憶装置
JP3035995B2 (ja) 1990-06-29 2000-04-24 ソニー株式会社 マルチポートメモリ
JP3238717B2 (ja) 1991-04-16 2001-12-17 三菱電機株式会社 半導体記憶装置におけるデータ転送装置
EP1199639A3 (de) * 1990-12-25 2004-12-08 Mitsubishi Denki Kabushiki Kaisha Halbleiterspeichervorrichtung mit einem grossen Speicher und einem Hochgeschwindigkeitsspeicher
JP3268785B2 (ja) * 1990-12-25 2002-03-25 三菱電機株式会社 半導体記憶装置
JPH04307495A (ja) * 1991-04-04 1992-10-29 Mitsubishi Electric Corp 半導体記憶装置
US5652723A (en) * 1991-04-18 1997-07-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device
JP3240161B2 (ja) 1991-04-18 2001-12-17 三菱電機エンジニアリング株式会社 半導体記憶装置
CA2079690A1 (en) * 1991-10-03 1993-04-04 Frank M. Wanlass Architecture and method for combining static cache memory and dynamic main memory on the same chip (cdram)
JP3304413B2 (ja) * 1992-09-17 2002-07-22 三菱電機株式会社 半導体記憶装置
JP3400824B2 (ja) * 1992-11-06 2003-04-28 三菱電機株式会社 半導体記憶装置
JPH07169262A (ja) 1993-12-14 1995-07-04 Matsushita Electric Ind Co Ltd 半導体記憶装置
JP3426693B2 (ja) * 1994-03-07 2003-07-14 株式会社日立製作所 半導体記憶装置
JPH08272691A (ja) * 1995-04-04 1996-10-18 Hitachi Ltd キャッシュ記憶システム
US6006310A (en) * 1995-09-20 1999-12-21 Micron Electronics, Inc. Single memory device that functions as a multi-way set associative cache memory
JP2853636B2 (ja) 1996-01-30 1999-02-03 日本電気株式会社 デュアルポート型画像用半導体記憶装置
US6088760A (en) * 1997-03-07 2000-07-11 Mitsubishi Semiconductor America, Inc. Addressing system in a multi-port RAM having main and cache memories

Also Published As

Publication number Publication date
EP0908888A2 (de) 1999-04-14
KR100366838B1 (ko) 2003-02-19
EP0908888B1 (de) 2005-07-20
KR19990029787A (ko) 1999-04-26
JP3161383B2 (ja) 2001-04-25
CN1211799A (zh) 1999-03-24
TW397990B (en) 2000-07-11
CN1144229C (zh) 2004-03-31
US6339817B1 (en) 2002-01-15
JPH1186559A (ja) 1999-03-30
EP0908888A3 (de) 1999-04-28

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Legal Events

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