DE69838660D1 - Integrierte Halbleiterschaltungsanordnung - Google Patents

Integrierte Halbleiterschaltungsanordnung

Info

Publication number
DE69838660D1
DE69838660D1 DE69838660T DE69838660T DE69838660D1 DE 69838660 D1 DE69838660 D1 DE 69838660D1 DE 69838660 T DE69838660 T DE 69838660T DE 69838660 T DE69838660 T DE 69838660T DE 69838660 D1 DE69838660 D1 DE 69838660D1
Authority
DE
Germany
Prior art keywords
circuit arrangement
semiconductor circuit
integrated semiconductor
integrated
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69838660T
Other languages
English (en)
Other versions
DE69838660T2 (de
Inventor
Taketo Maesako
Kouki Yamamoto
Yoshinori Matsui
Kenichi Sakakibara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Publication of DE69838660D1 publication Critical patent/DE69838660D1/de
Application granted granted Critical
Publication of DE69838660T2 publication Critical patent/DE69838660T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE69838660T 1997-09-16 1998-09-11 Integrierte Halbleiterschaltungsvorrichtung Expired - Fee Related DE69838660T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP29023697A JP3161385B2 (ja) 1997-09-16 1997-09-16 半導体記憶装置
JP29023697 1997-09-16

Publications (2)

Publication Number Publication Date
DE69838660D1 true DE69838660D1 (de) 2007-12-20
DE69838660T2 DE69838660T2 (de) 2008-10-30

Family

ID=17753527

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69838660T Expired - Fee Related DE69838660T2 (de) 1997-09-16 1998-09-11 Integrierte Halbleiterschaltungsvorrichtung

Country Status (7)

Country Link
US (1) US6101146A (de)
EP (1) EP0908886B1 (de)
JP (1) JP3161385B2 (de)
KR (1) KR100352311B1 (de)
CN (1) CN1212431A (de)
DE (1) DE69838660T2 (de)
TW (1) TW436801B (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6965974B1 (en) * 1997-11-14 2005-11-15 Agere Systems Inc. Dynamic partitioning of memory banks among multiple agents
JP2000268559A (ja) * 1999-03-12 2000-09-29 Nec Corp 半導体集積回路装置
JP3319421B2 (ja) * 1999-03-15 2002-09-03 日本電気株式会社 半導体集積回路装置
JP3358612B2 (ja) 1999-03-15 2002-12-24 日本電気株式会社 半導体集積回路
US6288923B1 (en) * 1999-09-14 2001-09-11 Kabushiki Kaisha Toshiba Semiconductor memory mounted with cache memory
GB0123416D0 (en) * 2001-09-28 2001-11-21 Memquest Ltd Non-volatile memory control
JP2003132683A (ja) * 2001-10-23 2003-05-09 Hitachi Ltd 半導体装置
KR100408421B1 (ko) * 2002-01-16 2003-12-03 삼성전자주식회사 서브-어레이의 개수에 관계없이 계층형 입출력 라인구조를 가지는 반도체 메모리 장치
JP4160556B2 (ja) * 2002-06-03 2008-10-01 富士通株式会社 半導体集積回路
KR100655375B1 (ko) 2005-11-11 2006-12-08 삼성전자주식회사 메모리 코어 및 이를 구비한 반도체 메모리 장치
US8045363B2 (en) * 2008-11-06 2011-10-25 Samsung Electronics Co., Ltd. Variable resistance memory devices including arrays of different sizes
KR20110131721A (ko) 2010-05-31 2011-12-07 주식회사 하이닉스반도체 반도체 메모리 장치
KR102638791B1 (ko) * 2018-09-03 2024-02-22 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템
KR102553855B1 (ko) * 2019-03-05 2023-07-12 에스케이하이닉스 주식회사 시프트레지스터
CN116705132B (zh) * 2022-02-24 2024-05-14 长鑫存储技术有限公司 数据传输电路、数据传输方法和存储器

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5720983A (en) * 1980-07-15 1982-02-03 Hitachi Ltd Memory chip
US4541076A (en) * 1982-05-13 1985-09-10 Storage Technology Corporation Dual port CMOS random access memory
JPH069114B2 (ja) * 1983-06-24 1994-02-02 株式会社東芝 半導体メモリ
JPS6238590A (ja) * 1985-08-13 1987-02-19 Fujitsu Ltd 半導体記憶装置
JPH01146187A (ja) * 1987-12-02 1989-06-08 Mitsubishi Electric Corp キヤッシュメモリ内蔵半導体記憶装置
JP2938511B2 (ja) * 1990-03-30 1999-08-23 三菱電機株式会社 半導体記憶装置
JPH0453083A (ja) * 1990-06-20 1992-02-20 Hitachi Ltd 半導体メモリ
JP3238717B2 (ja) * 1991-04-16 2001-12-17 三菱電機株式会社 半導体記憶装置におけるデータ転送装置
JP3268785B2 (ja) * 1990-12-25 2002-03-25 三菱電機株式会社 半導体記憶装置
JP3240161B2 (ja) * 1991-04-18 2001-12-17 三菱電機エンジニアリング株式会社 半導体記憶装置
JPH05210974A (ja) * 1991-10-03 1993-08-20 Smc Standard Microsyst Corp 同一チップ上でのスタティックキャッシュメモリとダイナミックメインメモリとの結合システム
US5291444A (en) * 1991-12-23 1994-03-01 Texas Instruments Incorporated Combination DRAM and SRAM memory array
JP3304413B2 (ja) * 1992-09-17 2002-07-22 三菱電機株式会社 半導体記憶装置
JP3400824B2 (ja) * 1992-11-06 2003-04-28 三菱電機株式会社 半導体記憶装置
JPH09147598A (ja) * 1995-11-28 1997-06-06 Mitsubishi Electric Corp 半導体記憶装置およびアドレス変化検出回路
US5844856A (en) * 1996-06-19 1998-12-01 Cirrus Logic, Inc. Dual port memories and systems and methods using the same
EP0935252B1 (de) * 1996-10-28 2004-04-21 Mitsubishi Denki Kabushiki Kaisha Integrierte speicherschaltungsanordnung mit logischer schaltungskompatibler struktur

Also Published As

Publication number Publication date
TW436801B (en) 2001-05-28
EP0908886B1 (de) 2007-11-07
EP0908886A2 (de) 1999-04-14
JPH1186533A (ja) 1999-03-30
EP0908886A3 (de) 1999-04-28
JP3161385B2 (ja) 2001-04-25
KR19990029790A (ko) 1999-04-26
US6101146A (en) 2000-08-08
DE69838660T2 (de) 2008-10-30
CN1212431A (zh) 1999-03-31
KR100352311B1 (ko) 2002-11-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee