JPS61226942A - 半導体集積回路の素子間分離方法 - Google Patents

半導体集積回路の素子間分離方法

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Publication number
JPS61226942A
JPS61226942A JP60068727A JP6872785A JPS61226942A JP S61226942 A JPS61226942 A JP S61226942A JP 60068727 A JP60068727 A JP 60068727A JP 6872785 A JP6872785 A JP 6872785A JP S61226942 A JPS61226942 A JP S61226942A
Authority
JP
Japan
Prior art keywords
film
silicon nitride
silicon
nitride film
shaped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60068727A
Other languages
English (en)
Inventor
Takamichi Takebayashi
竹林　孝路
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP60068727A priority Critical patent/JPS61226942A/ja
Priority to EP86104272A priority patent/EP0197454B1/en
Priority to DE86104272T priority patent/DE3688757T2/de
Priority to US06/846,736 priority patent/US4682408A/en
Publication of JPS61226942A publication Critical patent/JPS61226942A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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  • Engineering & Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Spectroscopy & Molecular Physics (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、ＭＯ８形半導体集積回路での素子間の相互干
渉を防止するための厚いフィールド絶縁膜を形成すると
ともに、この直下にチャネルストッパ領域を形成し、素
子間を分離する半導体集積回路の素子間分離方法に関す
る。
従来の技術 絶縁ゲート形半導体集積回路、特に集積度の高い超ＬＳ
Ｉでは、第３図ａ、ｂの工程順断面図に示すように、単
一の半導体基板１内へ作り込捷れる素子間を分離するに
あたり、窒化シリコン膜２をマスクとして、フィールド
絶縁膜と呼ばれる素子間分離領域上の絶縁膜３の厚みを
選択酸化法（ＬＯＣＯＳ法：　Ｌｏｃａｌ　０ｘｉｄａ
ｔｉｏｎ　ｏｆ　５ｉｌｉｃｏｎ）によって厚くすると
ともに、このフィールド絶縁膜３下の半導体基板表面層
に高不純物濃度のチャネルストッパ領域４を形成し、ゲ
ート閾値電圧を高める方法が採用されている。なお、図
中、符号６は酸化シリコン膜である。しかしながら、こ
の素子間分離方法では、選択酸化によるフィールド絶縁
膜の形成ならびにチャネルストッパ領域形成用の不純物
元素の導入が自己整合方式によってなされるため、形成
されたチャネルストッパ領域が、絶縁ゲート形電界効果
トランジスタ、たとえばＭＯ３形トランジスタの能動領
域形成部に１でくい込むところとなる。
第４図は、以上説明した従来の素子間分離方法によって
、素子分離がなされたＬＳＩの断面構造を示す図であり
、図中、１はたとえばＰ形のシリコン基板、１２はゲー
ト酸化膜、１３は多結晶シリコンゲート電極、１４はＭ
Ｏ８形トランジスタのドレインとなるｎ＋形領領域１５
はソース領域となるｎ″−影領域、３は選択酸化法で形
成したフィールド酸化膜、そして４は例えばイオン注入
法で不純物元素の導入がなされ、上記の選択酸化の＋ ための高温の熱処理を経て形成されたＰ　形のチャネル
ストッパ領域である。
発明が解決しようとする問題点 上記の構造のＬＳＩでは、図示するように、チャネルス
トッパ領域４のくい込みによって、ｎ十形ドレイン領域
１４ならびにｎ＋十形−ス領域１５の一部分とチャネル
ストッパ領域４との間に重り部１８が形成され、この部
分には　ｐ　−１−ｎ＋接合が存在するところとなり、
寄生接合容量が増加する不都合があった。′また第６図
の平面図で示すように、チャネルストッパ領域４は、多
結晶シＩＪ　コンゲート電極１３の下部にもくい込むた
め、本来、ゲートの幅Ｗと等しい値であるべきチャネル
幅Ｗ１が狭くなる、いわゆる、狭チャネル効果も生じる
。このチャネル幅の狭小化により電流駆動能力が低下す
る不都合もあった。
問題点を解決するための手段 本発明は、酸化シリコン膜ならひに窒化シリコン膜を一
導電形の半導体基板上に順次積層形成する工程、前記窒
化シリコン膜を選択的に食刻除去して開孔を形成する工
程、シリコンのオキシ誘導体による塗布被膜を形成した
後、前記半導体基板を除去し、同窒化シリコン膜をマス
クにして半導５　ヘー。
体基板部分を選択的に酸化する工程を経て選択酸化層下
のみにチャネルストッパ領域が重なり合う素子分離領域
を形成するものである。
作用 この方法によれば、イオン注入層の形成域が、窒化シリ
コン膜の開孔内で、かつ開孔の端縁から離れた部分に特
定されるため、従来の方法のようにチャネルストッパ領
域が素子の能動領域形成部へくい込むことはなく、この
ことに起因する不都合を排除することができ、超ＬＳＩ
の高性能化に必要とされる素子間の分離が可能になる。
実施例 以下に、ＭＯ８形大規模集積回路（ＭＯ８ＬＳＩ）の製
作に本発明を適用した場合を第１図ａ　−ｃの工程断面
図および第２図の断面図によシ、詳しく説明する。
まず第１図ａで示すように、シリコン基板１０表面を熱
酸化し、厚さが約５０ｎｍの酸化シリコン膜３を形成し
た後、周知のｃｖｎ法によって、酸化防止膜となる窒化
シリコン膜２を約１２０ｎｍ６１、− の厚さに形成する。次いで通常のホトエツチング法を用
いて、レジスト６をマスクにして、窒化シリコン膜２を
パターニングする。次にレジス］・６を残存させたま丑
シラノール主体の塗布被膜７を形成する。シラノール（
Ｈ３ＳｉＯＨ）　ｌｄアルコール（／Ｃ可溶で、その粘
度が約ＩＣｐであれば、回転塗布法により塗布被膜７を
開口部の側壁部で厚く、他の部分で薄くなるように形成
することができる。
そしてこのシラノール被膜７は約３０ｏ′Ｃで２０分間
の熱処理を施すことによって、二酸化シリコン膜に転化
される。
この時形成された二酸化シリコン膜は、第１図すに示す
ように側壁部では厚く形成され、開孔中心部に向かって
薄くなり、平坦部では約０゜１μｍの厚みとなる。この
のち開孔を通して半導体基板１と同一導電形の不純物を
イオン注入する。すなわち前記の開孔を通過した不純物
は開孔中央部の平坦な領域では、厚さ約１５０ｎｍの酸
化シリコン膜（７，３）を通過して半導体基板１の中へ
注入されるが、開口部端においては、シラノール被膜が
厚く形成されるため、酸化シリコン膜の厚みが厚くなり
、したがって第１図すに示すように開口部の外側部分へ
はイオン注入層が形成されず、能動領域へイオン注入層
４の伸びが抑制される。
次に第１図Ｃのように周知の酸化シリコン膜エッチ、お
よびレジスト除去を施したのち、最終処理として残存す
る窒化シリコン膜２を酸化防止膜として用い、周知の方
法で選択酸化を実施して、選択酸化層６および、この直
下にのみチャネルストッパ領域４を形成した後、通常の
ＭＯ３ＬＳＩ製造工程を経て、第２図に示すようにチャ
ネルストッパ領域４とドレイン領域１４ならびにソース
領域１６とが離間し、捷た、ゲート電極下へのチャネル
ストッパ領域４のくい込みがないＭＯ３ＬＳＩが完成す
る。
発明の効果 本発明の半導体集積回路の素子分離方法によれば、チャ
ネルストッパ領域形成用のイオン注入層の形成がセルフ
ァラインでなされ、しかも、このイオン注入層をシリコ
ン基板の選択酸化域内に、これよりも狭い面積で作り込
むことができる。このため、素子の能動領域内へのチャ
ネルストッパ領域がくい込むことがなく、チャネルスト
ッパ領域のくい込みに起因する狭チャネル効果の発生お
よび寄生接合容量の増加を防止でき、超ＬＳＩの性能を
高めることが可能になる。
【図面の簡単な説明】
第１図ａ　−ｃは本発明実施例の工程順断面図、第２図
は本実施例で得られた装置断面図、第３図ａ、ｂは従来
の素子間分離方法により素子間分離領域を形成する工程
順断面図、第４図ならびに第６図は従来の素子分離方法
を採用して形成したＬＳＩの断面図ならびに平面図であ
る。 １・・・・・・半導体基板、２・・・・・・窒化シリコ
ン膜、３゜５・・・・・・酸化シリコン膜、４・・・・
・チャネルストッパ領域、６・・・・・・レジスト、７
・・・・・・シラノール被膜、１２・・・・・ゲート絶
縁膜、１３・・・・多結晶シリコンゲート電極、１４・
・・・・ｎ＋形トドレイン領域１５＋ ・・・・・・ｎ　形ソース領域、１８・・・・・・重な
り部。

Claims (2)

    【特許請求の範囲】
  1. （１）一導電形の半導体基板上に酸化シリコン膜ならび
    に窒化シリコン膜を順次形成する工程、前記窒化シリコ
    ン膜を選択的に食刻除去して開孔を形成する工程、シリ
    コンのオキシ誘導体による塗布被膜を形成した後、前記
    半導体基板内にこれと同一導電形の不純物をイオン注入
    してイオン注入層を形成する工程、および前記塗布被膜
    を除去し、同窒化シリコン膜をマスクにして半導体基板
    部分を選択的に酸化する工程を経て選択酸化層下にのみ
    チャネルストッパ領域が重り合う素子分離領域を形成す
    ることを特徴とする半導体集積回路の素子間分離方法。
  2. （２）シリコンのオキシ誘導体がシラノール主体でなる
    特許請求の範囲第１項に記載の半導体集積回路の素子間
    分離方法。
JP60068727A 1985-04-01 1985-04-01 半導体集積回路の素子間分離方法 Pending JPS61226942A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP60068727A JPS61226942A (ja) 1985-04-01 1985-04-01 半導体集積回路の素子間分離方法
EP86104272A EP0197454B1 (en) 1985-04-01 1986-03-27 Method for making semiconductor devices comprising insulating regions
DE86104272T DE3688757T2 (de) 1985-04-01 1986-03-27 Verfahren zur Herstellung von Halbleiteranordnungen mit Isolationszonen.
US06/846,736 US4682408A (en) 1985-04-01 1986-04-01 Method for making field oxide region with self-aligned channel stop implantation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60068727A JPS61226942A (ja) 1985-04-01 1985-04-01 半導体集積回路の素子間分離方法

Publications (1)

Publication Number Publication Date
JPS61226942A true JPS61226942A (ja) 1986-10-08

Family

ID=13382114

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60068727A Pending JPS61226942A (ja) 1985-04-01 1985-04-01 半導体集積回路の素子間分離方法

Country Status (4)

Country Link
US (1) US4682408A (ja)
EP (1) EP0197454B1 (ja)
JP (1) JPS61226942A (ja)
DE (1) DE3688757T2 (ja)

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US5378650A (en) * 1990-10-12 1995-01-03 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and a manufacturing method thereof
EP0482829A1 (en) * 1990-10-26 1992-04-29 AT&T Corp. Method for forming a composite oxide over a heavily doped region
JP3134344B2 (ja) * 1991-05-17 2001-02-13 日本電気株式会社 半導体装置
JP3277533B2 (ja) * 1992-01-08 2002-04-22 ソニー株式会社 半導体装置の製造方法
US5322804A (en) * 1992-05-12 1994-06-21 Harris Corporation Integration of high voltage lateral MOS devices in low voltage CMOS architecture using CMOS-compatible process steps
US5675165A (en) * 1994-08-02 1997-10-07 Lien; Chuen-Der Stable SRAM cell using low backgate biased threshold voltage select transistors
JP3335060B2 (ja) * 1995-02-21 2002-10-15 シャープ株式会社 半導体装置の製造方法
FR2734403B1 (fr) * 1995-05-19 1997-08-01 Sgs Thomson Microelectronics Isolement plan dans des circuits integres
DE19959346B4 (de) * 1999-12-09 2004-08-26 Micronas Gmbh Verfahren zum Herstellen eines eine Mikrostruktur aufweisenden Festkörpers
DE50014168D1 (de) * 2000-12-21 2007-04-26 Micronas Gmbh Verfahren zum herstellen eines eine mikrostruktur aufweisenden festkörpers

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JPS60161671A (ja) * 1984-02-01 1985-08-23 Sanyo Electric Co Ltd Ｍｏｓ半導体装置の製造方法

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JPS58134443A (ja) * 1982-02-04 1983-08-10 Toshiba Corp 半導体装置の製造方法
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JPS60161671A (ja) * 1984-02-01 1985-08-23 Sanyo Electric Co Ltd Ｍｏｓ半導体装置の製造方法

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* Cited by examiner, † Cited by third party
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JP2013247300A (ja) * 2012-05-28 2013-12-09 Canon Inc 半導体装置、半導体装置の製造方法及び液体吐出装置

Also Published As

Publication number Publication date
DE3688757T2 (de) 1993-10-28
DE3688757D1 (de) 1993-09-02
EP0197454A2 (en) 1986-10-15
EP0197454B1 (en) 1993-07-28
US4682408A (en) 1987-07-28
EP0197454A3 (en) 1990-11-07

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