JP5260837B2 - 半導体集積回路の設計方法及び半導体集積回路の設計装置 - Google Patents
半導体集積回路の設計方法及び半導体集積回路の設計装置 Download PDFInfo
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- JP5260837B2 JP5260837B2 JP2006083336A JP2006083336A JP5260837B2 JP 5260837 B2 JP5260837 B2 JP 5260837B2 JP 2006083336 A JP2006083336 A JP 2006083336A JP 2006083336 A JP2006083336 A JP 2006083336A JP 5260837 B2 JP5260837 B2 JP 5260837B2
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- power supply
- supply voltage
- temperature
- semiconductor integrated
- integrated circuit
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/18—Manufacturability analysis or optimisation for manufacturability
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
11 プロセスばらつきにより変動する回路特性
12 温度及び電源電圧の許容範囲
60 システム
61 半導体装置
62 温度センサ・電源ユニット制御回路
63 ペルチェ素子用コントローラ/電源
64 プリント基板
510 コンピュータ
511 CPU
512 RAM
513 ROM
514 二次記憶装置
515 可換媒体記憶装置
516 インターフェース
520 ディスプレイ装置
521 キーボード
522 マウス
523 通信装置
Claims (2)
- 半導体集積回路の動作時の動作温度及び動作電源電圧について変動可能な許容範囲についての情報を入手する段階、
該半導体集積回路のプロセスばらつきに応じた各回路特性に対して、最大動作速度と最小動作速度との中間である速度の動作を実現するのに必要とされる電源電圧及び温度を計算して求め、該プロセスばらつきによる回路特性の変動をキャンセルする目標温度及び目標電源電圧として、前記求めた電源電圧及び温度を該プロセスばらつきに応じた各回路特性と対応付けてメモリに格納する段階、
該半導体集積回路が該メモリに格納された該目標温度及び目標電源電圧を略中心とした該許容範囲内で動作すると仮定して、計算機シミュレーションにより最大速度条件の回路特性の値と最小速度条件の回路特性の値とをライブラリとして作成する段階、
該ライブラリを用いて該許容範囲内の任意の温度と電源電圧とで正常に動作するように回路設計する段階
を含む、半導体集積回路の設計方法。 - データとプログラムを格納するメモリと、
該メモリの該プログラムを実行して該メモリの該データを処理する処理ユニット
を含み、該処理ユニットは、
半導体集積回路のプロセスばらつきに応じた各回路特性に対して、最大動作速度と最小動作速度との中間である速度の動作を実現するのに必要とされる電源電圧及び温度を計算して求め、該プロセスばらつきによる回路特性の変動をキャンセルする目標温度及び目標電源電圧として、前記求めた電源電圧及び温度を該プロセスばらつきに応じた各回路特性と対応付けてメモリに格納する段階と、
該半導体集積回路が該メモリに格納された該目標温度及び目標電源電圧を略中心とした許容範囲内で動作すると仮定して、計算機シミュレーションにより最大速度条件の回路特性の値と最小速度条件の回路特性の値とをライブラリとして作成する段階を実行し、
前記ライブラリを用いて該許容範囲内の任意の温度と電源電圧とで正常に動作するように回路設計することを可能にする、半導体集積回路の設計装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006083336A JP5260837B2 (ja) | 2006-03-24 | 2006-03-24 | 半導体集積回路の設計方法及び半導体集積回路の設計装置 |
US11/525,895 US7661079B2 (en) | 2006-03-24 | 2006-09-25 | Designing and operating of semiconductor integrated circuit by taking into account process variation |
Applications Claiming Priority (1)
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JP2006083336A JP5260837B2 (ja) | 2006-03-24 | 2006-03-24 | 半導体集積回路の設計方法及び半導体集積回路の設計装置 |
Related Child Applications (1)
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JP2013061894A Division JP5682647B2 (ja) | 2013-03-25 | 2013-03-25 | 半導体集積回路の動作の制御方法及び半導体集積回路の制御システム |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007258569A JP2007258569A (ja) | 2007-10-04 |
JP5260837B2 true JP5260837B2 (ja) | 2013-08-14 |
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JP2006083336A Expired - Fee Related JP5260837B2 (ja) | 2006-03-24 | 2006-03-24 | 半導体集積回路の設計方法及び半導体集積回路の設計装置 |
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US (1) | US7661079B2 (ja) |
JP (1) | JP5260837B2 (ja) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080147373A1 (en) * | 2006-12-14 | 2008-06-19 | Thomas Roessler | Method for analyzing the design of an integrated circuit |
JP4964685B2 (ja) * | 2007-06-21 | 2012-07-04 | ルネサスエレクトロニクス株式会社 | 半導体集積回路の電源変動検証装置及び方法並びにそのプログラム |
US8016482B2 (en) * | 2007-07-20 | 2011-09-13 | International Business Machines Corporation | Method and systems of powering on integrated circuit |
US8022535B2 (en) | 2008-06-06 | 2011-09-20 | Coolsilicon Llc | Systems, devices, and methods for semiconductor device temperature management |
WO2010019147A1 (en) * | 2008-08-14 | 2010-02-18 | Lsi Corporation | System and method for designing integrated circuits that employ adaptive voltage scaling optimization |
US8181144B2 (en) * | 2008-10-14 | 2012-05-15 | Lsi Corporation | Circuit timing analysis incorporating the effects of temperature inversion |
GB2484442B (en) | 2009-07-28 | 2013-12-25 | Skyworks Solutions Inc | Process, voltage, and temperature sensor |
JP5524568B2 (ja) * | 2009-10-23 | 2014-06-18 | ルネサスエレクトロニクス株式会社 | 半導体装置、及び半導体装置の設計方法 |
JP5401376B2 (ja) * | 2010-03-29 | 2014-01-29 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の設計方法 |
US8418107B2 (en) * | 2010-11-10 | 2013-04-09 | International Business Machines Corporation | Performing statistical timing analysis with non-separable statistical and deterministic variations |
US8533645B2 (en) * | 2011-04-29 | 2013-09-10 | Apple Inc. | Reducing narrow gate width effects in an integrated circuit design |
US8352900B1 (en) * | 2012-01-24 | 2013-01-08 | International Business Machines Corporation | Analytic experimental estimator for impact of voltage-overshoot of voltage waveform on dielectric failure/breakdown |
US10796977B2 (en) * | 2019-03-04 | 2020-10-06 | Intel Corporation | Method and apparatus to control temperature of a semiconductor die in a computer system |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH0338862A (ja) * | 1989-07-05 | 1991-02-19 | Ricoh Co Ltd | 半導体集積回路装置の電源調節方法 |
JP4014708B2 (ja) * | 1997-08-21 | 2007-11-28 | 株式会社ルネサステクノロジ | 半導体集積回路装置の設計方法 |
JP2002324097A (ja) | 2001-04-25 | 2002-11-08 | Hitachi Ltd | Cmosオペアンプの設計システムおよび設計方法 |
JP2002353083A (ja) | 2001-05-23 | 2002-12-06 | Hitachi Ltd | 半導体集積回路の製造方法 |
JP2004326654A (ja) * | 2003-04-28 | 2004-11-18 | Renesas Technology Corp | 配線構造決定方法 |
US7475366B2 (en) * | 2006-08-04 | 2009-01-06 | International Business Machines Corporation | Integrated circuit design closure method for selective voltage binning |
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2006
- 2006-03-24 JP JP2006083336A patent/JP5260837B2/ja not_active Expired - Fee Related
- 2006-09-25 US US11/525,895 patent/US7661079B2/en not_active Expired - Fee Related
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Publication number | Publication date |
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JP2007258569A (ja) | 2007-10-04 |
US20070226660A1 (en) | 2007-09-27 |
US7661079B2 (en) | 2010-02-09 |
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