JP4318511B2 - 昇圧回路 - Google Patents
昇圧回路 Download PDFInfo
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- JP4318511B2 JP4318511B2 JP2003301499A JP2003301499A JP4318511B2 JP 4318511 B2 JP4318511 B2 JP 4318511B2 JP 2003301499 A JP2003301499 A JP 2003301499A JP 2003301499 A JP2003301499 A JP 2003301499A JP 4318511 B2 JP4318511 B2 JP 4318511B2
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- Prior art keywords
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- mos transistor
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- capacitor
- drain
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- Expired - Fee Related
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- 239000003990 capacitor Substances 0.000 claims description 31
- 230000003071 parasitic effect Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Dc-Dc Converters (AREA)
- Manipulation Of Pulses (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
Claims (6)
- Pウェル内に一対のN領域を形成しソース電極が接続されたソース領域およびドレイン電極が接続されたドレイン領域とし、ソース、ドレイン領域間のチャネル領域に絶縁膜を介し対向するゲート電極を形成して形成したNMOSトランジスタを有する昇圧回路であって、
前記ソース電極を電源に接続するとともに、前記Pウェルは、電気的抵抗素子を介し、電源に接続することを特徴とする昇圧回路。 - Nウェル内にPウェルを形成し、このPウェル内に一対のN領域を形成しソース電極が接続されたソース領域およびドレイン電極が接続されたドレイン領域とし、ソース、ドレイン領域間のチャネル領域に絶縁膜を介し対向するゲート電極を形成して形成したNMOSトランジスタを有する昇圧回路であって、
前記ソース電極を電源に接続するとともに、前記Nウェルを電気的抵抗素子を介し回路出力に接続することを特徴とする昇圧回路。 - 請求項1または2に記載の回路において、
前記電気的抵抗素子は、オン状態のPMOSであることを特徴とする昇圧回路。 - 請求項1または2に記載の回路において、
前記電気的抵抗素子は、抵抗素子であることを特徴とする昇圧回路。 - 一端が入力電源に接続された第1MOSトランジスタと、
この第1MOSトランジスタの他端に一端が接続された第2MOSトランジスタと、
第1および第2MOSトランジスタの接続点に第1コンデンサを介し接続されたパルス信号供給手段と、
前記第2MOSトランジスタの他端に接続され、電圧を保持する第2コンデンサと、
を有し、第1MOSトランジスタをオンして入力電源の電圧を第1コンデンサに保持し、第1MOSトランジスタをオフして、パルス信号によって、第1および第2MOSトランジスタの接続点の電位をシフトさせ、その状態で第2MOSトランジスタをオンしてシフトした電圧を第2コンデンサに保持して出力する昇圧回路であって、
前記第1MOSトランジスタは、Pウェルを形成し、このPウェル中に一対のN領域を形成しソース電極が接続されたソース領域およびドレイン電極が接続されたドレイン領域とし、ソース、ドレイン領域間のチャネル領域に絶縁膜を介し対向するゲート電極を形成して形成したNMOSトランジスタであって、前記ソース電極を電源に接続するとともに、前記Pウェルは、電気的抵抗素子を介し、電源に接続することを特徴とする昇圧回路。 - 一端が入力電源に接続された第1MOSトランジスタと、
この第1MOSトランジスタの他端に一端が接続された第2MOSトランジスタと、
第1および第2MOSトランジスタの接続点に第1コンデンサを介し接続されたパルス信号供給手段と、
前記第2MOSトランジスタの他端に接続され、電圧を保持する第2コンデンサと、
を有し、第1MOSトランジスタをオンして入力電源の電圧を第1コンデンサに保持し、第1MOSトランジスタをオフして、パルス信号によって、第1および第2MOSトランジスタの接続点の電位をシフトさせ、その状態で第2MOSトランジスタをオンしてシフトした電圧を第2コンデンサに保持して出力する昇圧回路であって、
前記第1MOSトランジスタは、Nウェル内にPウェルを形成し、このPウェル中に一対のN領域を形成しソース電極が接続されたソース領域およびドレイン電極が接続されたドレイン領域とし、ソース、ドレイン領域間のチャネル領域に絶縁膜を介し対向するゲート電極を形成して形成したNMOSトランジスタであって、
前記Nウェルを電気的抵抗素子を介し前記第2MOSトランジスタの第2コンデンサが接続された出力端に接続することを特徴とする昇圧回路。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003301499A JP4318511B2 (ja) | 2003-08-26 | 2003-08-26 | 昇圧回路 |
TW093112150A TWI255092B (en) | 2003-08-26 | 2004-04-30 | Transistor circuit and booster circuit |
CNB200410045850XA CN100350728C (zh) | 2003-08-26 | 2004-05-20 | 晶体管电路和升压电路 |
US10/924,507 US7323753B2 (en) | 2003-08-26 | 2004-08-24 | MOS transistor circuit and voltage-boosting booster circuit |
KR1020040067226A KR100611296B1 (ko) | 2003-08-26 | 2004-08-25 | 트랜지스터 회로 및 승압 회로 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003301499A JP4318511B2 (ja) | 2003-08-26 | 2003-08-26 | 昇圧回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005072353A JP2005072353A (ja) | 2005-03-17 |
JP4318511B2 true JP4318511B2 (ja) | 2009-08-26 |
Family
ID=34213898
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003301499A Expired - Fee Related JP4318511B2 (ja) | 2003-08-26 | 2003-08-26 | 昇圧回路 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7323753B2 (ja) |
JP (1) | JP4318511B2 (ja) |
KR (1) | KR100611296B1 (ja) |
CN (1) | CN100350728C (ja) |
TW (1) | TWI255092B (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4387119B2 (ja) * | 2003-03-27 | 2009-12-16 | 三菱電機株式会社 | 半導体装置 |
US7825473B2 (en) * | 2005-07-21 | 2010-11-02 | Industrial Technology Research Institute | Initial-on SCR device for on-chip ESD protection |
JP4832841B2 (ja) * | 2005-09-22 | 2011-12-07 | 三菱電機株式会社 | 半導体装置 |
JP5211355B2 (ja) | 2007-11-01 | 2013-06-12 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 電源回路及び携帯機器 |
DE102008047850B4 (de) * | 2008-09-18 | 2015-08-20 | Austriamicrosystems Ag | Halbleiterkörper mit einer Schutzstruktur und Verfahren zum Herstellen derselben |
US8378422B2 (en) * | 2009-02-06 | 2013-02-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrostatic discharge protection device comprising a plurality of highly doped areas within a well |
WO2017001535A1 (de) * | 2015-06-30 | 2017-01-05 | Fronius International Gmbh | Schaltungsanordnung zur ansteuerung eines transistors |
TWI666859B (zh) * | 2017-12-29 | 2019-07-21 | 新唐科技股份有限公司 | 電壓保持電路及使用其之電子裝置 |
US11558019B2 (en) * | 2018-11-15 | 2023-01-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and circuit to isolate body capacitance in semiconductor devices |
CN111193478A (zh) * | 2018-11-15 | 2020-05-22 | 台湾积体电路制造股份有限公司 | 放大电路 |
CN110676323B (zh) * | 2019-09-17 | 2023-04-28 | 长江存储科技有限责任公司 | Nmos晶体管及其形成方法、电荷泵电路 |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4647956A (en) * | 1985-02-12 | 1987-03-03 | Cypress Semiconductor Corp. | Back biased CMOS device with means for eliminating latchup |
US5270565A (en) * | 1989-05-12 | 1993-12-14 | Western Digital Corporation | Electro-static discharge protection circuit with bimodal resistance characteristics |
JP3074003B2 (ja) * | 1990-08-21 | 2000-08-07 | 株式会社日立製作所 | 半導体集積回路装置 |
JP3184298B2 (ja) * | 1992-05-28 | 2001-07-09 | 沖電気工業株式会社 | Cmos出力回路 |
JP3246807B2 (ja) * | 1993-07-07 | 2002-01-15 | 株式会社東芝 | 半導体集積回路装置 |
US5594611A (en) * | 1994-01-12 | 1997-01-14 | Lsi Logic Corporation | Integrated circuit input/output ESD protection circuit with gate voltage regulation and parasitic zener and junction diode |
US5477413A (en) * | 1994-01-26 | 1995-12-19 | Cypress Semiconductor Corp. | ESD protection structure for P-well technology |
JP3354709B2 (ja) * | 1994-04-20 | 2002-12-09 | 新日本製鐵株式会社 | 半導体昇圧回路 |
JP2976903B2 (ja) * | 1996-10-08 | 1999-11-10 | 日本電気株式会社 | 半導体記憶装置 |
JP4014708B2 (ja) * | 1997-08-21 | 2007-11-28 | 株式会社ルネサステクノロジ | 半導体集積回路装置の設計方法 |
JP3196714B2 (ja) * | 1998-03-05 | 2001-08-06 | 日本電気株式会社 | トリプルウェル構造の半導体集積回路の製造方法 |
TW396542B (en) * | 1998-07-07 | 2000-07-01 | Winbond Electronics Corp | Decreasing the latch sensitivity in CMOS circuit |
US6501137B1 (en) * | 1998-12-30 | 2002-12-31 | Winbond Electronics Corp. | Electrostatic discharge protection circuit triggered by PNP bipolar action |
JP3928837B2 (ja) * | 1999-09-13 | 2007-06-13 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
JP3810246B2 (ja) * | 2000-03-15 | 2006-08-16 | 株式会社ルネサステクノロジ | 半導体装置および半導体装置の製造方法 |
TW511268B (en) * | 2000-04-21 | 2002-11-21 | Winbond Electronics Corp | Output buffer with excellent electrostatic discharge protection effect |
JP4149637B2 (ja) * | 2000-05-25 | 2008-09-10 | 株式会社東芝 | 半導体装置 |
US6917095B1 (en) * | 2000-05-30 | 2005-07-12 | Altera Corporation | Integrated radio frequency circuits |
US6299185B1 (en) * | 2000-10-26 | 2001-10-09 | Dwaine R. Lewis | Device for single-handedly moving large objects |
US6437407B1 (en) * | 2000-11-07 | 2002-08-20 | Industrial Technology Research Institute | Charged device model electrostatic discharge protection for integrated circuits |
US6833590B2 (en) * | 2001-01-11 | 2004-12-21 | Renesas Technology Corp. | Semiconductor device |
TW529178B (en) * | 2001-02-06 | 2003-04-21 | Sanyo Electric Co | Charge pump device |
JP2003197790A (ja) * | 2001-12-28 | 2003-07-11 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
JP3742597B2 (ja) * | 2002-01-31 | 2006-02-08 | 寛治 大塚 | 信号伝送システム |
US6582997B1 (en) * | 2002-05-17 | 2003-06-24 | Taiwan Semiconductor Manufacturing Company | ESD protection scheme for outputs with resistor loading |
JP3883114B2 (ja) * | 2002-05-30 | 2007-02-21 | 株式会社ルネサステクノロジ | 半導体装置 |
US6756642B2 (en) * | 2002-11-07 | 2004-06-29 | Taiwan Semiconductor Manufacturing Co., Ltd | Integrated circuit having improved ESD protection |
WO2004077081A1 (en) * | 2003-02-20 | 2004-09-10 | International Business Machines Corporation | Integrated circuit testing methods using well bias modification |
US6982406B2 (en) * | 2003-04-03 | 2006-01-03 | Pao Jung Chen | Simple CMOS light-to-current sensor |
-
2003
- 2003-08-26 JP JP2003301499A patent/JP4318511B2/ja not_active Expired - Fee Related
-
2004
- 2004-04-30 TW TW093112150A patent/TWI255092B/zh not_active IP Right Cessation
- 2004-05-20 CN CNB200410045850XA patent/CN100350728C/zh not_active Expired - Fee Related
- 2004-08-24 US US10/924,507 patent/US7323753B2/en active Active
- 2004-08-25 KR KR1020040067226A patent/KR100611296B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
US7323753B2 (en) | 2008-01-29 |
TW200509506A (en) | 2005-03-01 |
TWI255092B (en) | 2006-05-11 |
KR20050021280A (ko) | 2005-03-07 |
US20050045964A1 (en) | 2005-03-03 |
CN1592055A (zh) | 2005-03-09 |
JP2005072353A (ja) | 2005-03-17 |
KR100611296B1 (ko) | 2006-08-10 |
CN100350728C (zh) | 2007-11-21 |
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