JPS55135837A - Manufacture of photomask - Google Patents

Manufacture of photomask

Info

Publication number
JPS55135837A
JPS55135837A JP4449279A JP4449279A JPS55135837A JP S55135837 A JPS55135837 A JP S55135837A JP 4449279 A JP4449279 A JP 4449279A JP 4449279 A JP4449279 A JP 4449279A JP S55135837 A JPS55135837 A JP S55135837A
Authority
JP
Japan
Prior art keywords
pattern
chip
reticle
master
name
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4449279A
Other languages
Japanese (ja)
Other versions
JPS6223862B2 (en
Inventor
Takao Shida
Takashi Ariga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4449279A priority Critical patent/JPS55135837A/en
Publication of JPS55135837A publication Critical patent/JPS55135837A/en
Publication of JPS6223862B2 publication Critical patent/JPS6223862B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)

Abstract

PURPOSE:To prevent appearance of an inferior master mask by forming a master mask using a reticle with a chip name pattern within its scribed line and by referring the mask name pattern of the master mask to the chip name pattern of each chip. CONSTITUTION:Using primary reticle 7 having chip region 2 except wiring pattern regions 1, chip name pattern 4 and dummy region 5 within scribed line 3, and a light shielding layer in peripheral region 6, secondary reticle 8 whose pattern is the laternal inverse of the pattern of reticle 7 is formed. A negative resist is coated onto a blank sheet for a master mask with visible master name pattern 9 corresponding to a chip pattern to be used, and the chip pattern is exposed on the sheet by a step- and-repeat method using reticle 8. The exposed sheet is developed and etched to form master 10. Each pattern 4 and pattern 9 are then confirmed by reference.
JP4449279A 1979-04-12 1979-04-12 Manufacture of photomask Granted JPS55135837A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4449279A JPS55135837A (en) 1979-04-12 1979-04-12 Manufacture of photomask

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4449279A JPS55135837A (en) 1979-04-12 1979-04-12 Manufacture of photomask

Publications (2)

Publication Number Publication Date
JPS55135837A true JPS55135837A (en) 1980-10-23
JPS6223862B2 JPS6223862B2 (en) 1987-05-26

Family

ID=12693043

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4449279A Granted JPS55135837A (en) 1979-04-12 1979-04-12 Manufacture of photomask

Country Status (1)

Country Link
JP (1) JPS55135837A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0277744A (en) * 1988-09-13 1990-03-16 Fujitsu Ltd Production of photomask
US7163870B2 (en) 1997-03-31 2007-01-16 Renesas Technology Corp. Semiconductor integrated circuit device
US7541647B2 (en) 1997-08-21 2009-06-02 Renesas Technology Corp. Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02133949A (en) * 1988-11-14 1990-05-23 Hitachi Cable Ltd Spot plating of lead frame
JPH0734930Y2 (en) * 1990-06-26 1995-08-09 富士プラント工業株式会社 Masking material for partial plating for lead frames that requires plating on the island

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50150259U (en) * 1974-05-30 1975-12-13
JPS5311958U (en) * 1976-07-13 1978-01-31

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5311958B2 (en) * 1974-02-08 1978-04-25

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50150259U (en) * 1974-05-30 1975-12-13
JPS5311958U (en) * 1976-07-13 1978-01-31

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0277744A (en) * 1988-09-13 1990-03-16 Fujitsu Ltd Production of photomask
US7474003B2 (en) 1997-03-31 2009-01-06 Renesas Technology Corp. Semiconductor integrated circuit device
US7187039B2 (en) 1997-03-31 2007-03-06 Renesas Technology Corp. Semiconductor integrated circuit device
US7199432B2 (en) 1997-03-31 2007-04-03 Renesas Technology Corp. Semiconductor integrated circuit device
US7250682B2 (en) 1997-03-31 2007-07-31 Renesas Technology Corp. Semiconductor integrated circuit device
US7274074B2 (en) 1997-03-31 2007-09-25 Renesas Technology Corp. Semiconductor integrated circuit device
US7163870B2 (en) 1997-03-31 2007-01-16 Renesas Technology Corp. Semiconductor integrated circuit device
US7554202B2 (en) 1997-03-31 2009-06-30 Renesas Technology Corp Semiconductor integrated circuit device
US7626267B2 (en) 1997-03-31 2009-12-01 Renesas Technology Corporation Semiconductor integrated circuit device including wiring lines and interconnections
US7678684B2 (en) 1997-03-31 2010-03-16 Renesas Technology Corp. Semiconductor integrated circuit device
US8022550B2 (en) 1997-03-31 2011-09-20 Renesas Electronics Corporation Semiconductor integrated circuit device
US8420527B2 (en) 1997-03-31 2013-04-16 Renesas Electronics Corporation Semiconductor integrated circuit device
US7541647B2 (en) 1997-08-21 2009-06-02 Renesas Technology Corp. Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device

Also Published As

Publication number Publication date
JPS6223862B2 (en) 1987-05-26

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