JP2012256847A - メモリ装置、及びメモリ装置の作製方法 - Google Patents
メモリ装置、及びメモリ装置の作製方法 Download PDFInfo
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- JP2012256847A JP2012256847A JP2012049030A JP2012049030A JP2012256847A JP 2012256847 A JP2012256847 A JP 2012256847A JP 2012049030 A JP2012049030 A JP 2012049030A JP 2012049030 A JP2012049030 A JP 2012049030A JP 2012256847 A JP2012256847 A JP 2012256847A
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- semiconductor
- transistor
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- capacitor
- insulating layer
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/08—Oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
【解決手段】メモリ装置内のメモリ素子のセルトランジスタとして、リーク電流の極めて小さいトランジスタを用いる。さらにメモリセルの占有面積を縮小するために、ビット線とワード線とが交差する領域に、当該トランジスタのソース及びドレインが縦方向に積層されるように形成すればよい。さらにキャパシタは、当該トランジスタの上方に積層すればよい。
【選択図】図1
Description
本実施の形態では、本発明の一態様である半導体メモリ装置の構成例について、図1及び図6を用いて説明する。
本実施の形態では、実施の形態1で例示したメモリ装置100の作製方法について、図2及び図3を用いて説明する。
結晶性部分と非結晶性部分とを有し、結晶性部分の配向がc軸配向に揃っている酸化物半導体であるCAAC−OS(C Axis Aligned Crystalline Oxide Semiconductor)について説明する。
酸化物半導体に限らず、実際に測定される絶縁ゲート型トランジスタの電界効果移動度は、さまざまな理由によって本来の移動度よりも低くなる。
In、Sn、Znを含有する酸化物半導体を用いたトランジスタは、酸化物半導体を形成する際に基板を加熱して成膜すること、或いは酸化物半導体膜を形成した後に熱処理を行うことで良好な特性を得ることができる。
組成比としてIn:Sn:Zn=1:1:1のターゲットを用いて、ガス流量比をAr/O2=6/9sccm、成膜圧力を0.4Pa、成膜電力100Wとして、15nmの厚さとなるように基板上に酸化物半導体膜を成膜した。
サンプルAは酸化物半導体膜の成膜中に基板に意図的な加熱を施さなかった。
サンプルBは基板を200℃になるように加熱した状態で酸化物半導体膜の成膜を行った。
サンプルCは基板を200℃になるように加熱した状態で酸化物半導体膜の成膜を行った。
図14(A)にサンプルAのトランジスタの初期特性を示す。
サンプルB(成膜後加熱処理なし)及びサンプルC(成膜後加熱処理あり)に対してゲートBTストレス試験を行った。
本実施の形態では、半導体回路が形成された基板上にメモリ素子が積層されたメモリ装置の例について図4及び図5を用いて説明する。
101 基板
103 ビット線
105 ワード線
107 容量電極
109 半導体層
111 ゲート絶縁層
113 下地絶縁層
115 絶縁層
117 絶縁層
119 容量線
129 半導体膜
141 レジスト
143 絶縁膜
145 ハードマスク
147 絶縁膜
150 セルトランジスタ
160 キャパシタ
200 メモリ装置
201 単結晶半導体基板
203 駆動回路
205 セルトランジスタ層
205a セルトランジスタ層
205b セルトランジスタ層
207 キャパシタ層
207a キャパシタ層
207b キャパシタ層
220 メモリ装置
Claims (5)
- セルトランジスタと、キャパシタとが積層されたメモリ装置であって、
前記セルトランジスタは、
ビット線上に半導体層と、
前記半導体層の側面と接するゲート絶縁層と、を有し、
前記半導体層の側面の少なくとも一部は、前記ゲート絶縁層を介してワード線に覆われ、
前記キャパシタは、
前記半導体層の上面に接する容量電極と、
前記容量電極上に絶縁層と、
前記絶縁層上に容量配線と、を有し、
前記半導体層は、シリコンよりもバンドギャップの広い半導体材料で構成されている、メモリ装置。 - 前記半導体層は、バンドギャップが2.5電子ボルト以上4電子ボルト以下の材料から構成される、請求項1に記載のメモリ装置。
- 前記半導体層は、酸化物半導体から構成される、請求項1又は請求項2に記載のメモリ装置。
- 前記ビット線の下に、前記セルトランジスタを駆動する駆動回路を有することを特徴とする、請求項1乃至請求項3のいずれか一に記載のメモリ装置。
- 絶縁表面上にビット線を形成する工程と、
前記ビット線上に、シリコンよりもバンドギャップの広い半導体材料からなる半導体層を形成する工程と、
前記ビット線及び前記半導体層を覆うゲート絶縁層を形成する工程と、
前記ゲート絶縁層を介して前記半導体層の側面の少なくとも一部を覆うワード線を形成する工程と、
前記半導体層の上面を露出させるように前記ゲート絶縁層の一部を除去する工程と、
前記半導体層の上面に接する容量電極を形成する工程と、
前記容量電極上に、絶縁層と容量配線とを積層して形成する工程と、を有する、メモリ装置の作製方法。
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JP6059439B2 (ja) | 2017-01-11 |
WO2012121265A1 (en) | 2012-09-13 |
US9425107B2 (en) | 2016-08-23 |
CN103415921A (zh) | 2013-11-27 |
JP2015233155A (ja) | 2015-12-24 |
JP6174637B2 (ja) | 2017-08-02 |
JP2017157866A (ja) | 2017-09-07 |
US9812458B2 (en) | 2017-11-07 |
US10079238B2 (en) | 2018-09-18 |
JP6898497B2 (ja) | 2021-07-07 |
US20180076204A1 (en) | 2018-03-15 |
JP2020150282A (ja) | 2020-09-17 |
TW201304073A (zh) | 2013-01-16 |
US20120228688A1 (en) | 2012-09-13 |
TWI570850B (zh) | 2017-02-11 |
JP2019062241A (ja) | 2019-04-18 |
US20160358923A1 (en) | 2016-12-08 |
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