JP2011151796A - 記憶装置、半導体装置、及び電子機器 - Google Patents
記憶装置、半導体装置、及び電子機器 Download PDFInfo
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- JP2011151796A JP2011151796A JP2010285261A JP2010285261A JP2011151796A JP 2011151796 A JP2011151796 A JP 2011151796A JP 2010285261 A JP2010285261 A JP 2010285261A JP 2010285261 A JP2010285261 A JP 2010285261A JP 2011151796 A JP2011151796 A JP 2011151796A
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- oxide semiconductor
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- phase inverting
- capacitor
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Images
Classifications
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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Abstract
【解決手段】インバータまたはクロックドインバータなどの、入力された信号の位相を反転させて出力する位相反転素子を用いた記憶素子内に、データを保持するための容量素子と、当該容量素子における電荷の蓄積及び放出を制御するスイッチング素子とを設ける。上記スイッチング素子には、酸化物半導体をチャネル形成領域に含むトランジスタを用いる。位相反転素子への電源電圧の印加を停止する場合、データを容量素子に記憶させることで、位相反転素子への電源電圧の供給を停止しても、容量素子においてデータを保持させる。
【選択図】図1
Description
本発明の一態様に係る記憶装置は、1ビットのデータを記憶することができる記憶素子を、単数または複数有する。図1に、本発明の記憶装置が有する記憶素子の、回路図の一例を示す。図1に示す記憶素子100は、入力された信号の位相を反転させて出力する第1の位相反転素子101及び第2の位相反転素子102と、スイッチング素子103と、スイッチング素子104と、容量素子105と、容量用スイッチング素子106とを、少なくとも有する。
本実施の形態では、本発明の記憶装置が有する記憶素子の、別の一例について説明する。図3に、本実施の形態の記憶素子の回路図を、一例として示す。
本実施の形態では、本発明の記憶装置が有する記憶素子の、別の一例について説明する。図5に、本実施の形態の記憶素子の回路図を、一例として示す。
本発明の一態様に係る半導体装置は、シリコンを用いたトランジスタと、酸化物半導体を用いたトランジスタとを有する。シリコンを用いたトランジスタは、シリコンウェハ、SOI(Silicon on Insulator)基板、絶縁表面上のシリコン薄膜などを用いて形成することができる。
本実施の形態では、酸化物半導体膜を用いたトランジスタの構造が、実施の形態4とは異なるトランジスタの構成について説明する。
本実施の形態では、記憶素子への電源電位の供給を制御するスイッチング素子に、高純度化された酸化物半導体をチャネル形成領域に有するトランジスタを用いた、本発明の一態様に係る記憶装置の構成について説明する。
本実施の形態では、実施の形態4とは異なる、酸化物半導体膜の形成方法について図15を用いて説明する。
本実施の形態では、本発明の一態様に係る半導体装置の一つである、CPUの構成について説明する。
101 位相反転素子
102 位相反転素子
103 スイッチング素子
104 スイッチング素子
105 容量素子
106 容量用スイッチング素子
107 pチャネル型トランジスタ
108 nチャネル型トランジスタ
109 pチャネル型トランジスタ
110 nチャネル型トランジスタ
200 記憶素子
201 位相反転素子
202 位相反転素子
203 スイッチング素子
204 スイッチング素子
205 容量素子
206 容量用スイッチング素子
207 位相反転素子
208 スイッチング素子
209 スイッチング素子
210 pチャネル型トランジスタ
211 nチャネル型トランジスタ
212 pチャネル型トランジスタ
213 nチャネル型トランジスタ
214 pチャネル型トランジスタ
215 nチャネル型トランジスタ
300 記憶素子
301 位相反転素子
302 位相反転素子
303 スイッチング素子
304 スイッチング素子
305 容量素子
306 容量用スイッチング素子
307 容量素子
308 容量用スイッチング素子
309 pチャネル型トランジスタ
310 nチャネル型トランジスタ
311 pチャネル型トランジスタ
312 nチャネル型トランジスタ
401 スイッチング素子
402 記憶素子
403 記憶素子群
420 トランジスタ
421 第1の電極
422 酸化物半導体膜
423 第2の電極
424 ゲート絶縁膜
425 ゲート電極
426 絶縁膜
431 コンタクトホール
432 コンタクトホール
433 コンタクトホール
434 配線
435 配線
436 配線
440 配線
441 コンタクトホール
500 ボンド基板
501 絶縁膜
502 脆化層
503 ベース基板
504 半導体膜
505 半導体膜
506 半導体膜
507 半導体膜
508 ゲート絶縁膜
509 電極
510 不純物領域
511 不純物領域
512 サイドウォール
513 高濃度不純物領域
514 低濃度不純物領域
515 チャネル形成領域
516 高濃度不純物領域
517 低濃度不純物領域
518 チャネル形成領域
520 nチャネル型トランジスタ
521 pチャネル型トランジスタ
530 絶縁膜
531 絶縁膜
532 絶縁膜
601 ゲート電極
602 電極
603 ゲート絶縁膜
605 酸化物半導体膜
607 ソース電極
608 ドレイン電極
609 配線
610 配線
611 配線
612 絶縁膜
620 トランジスタ
623 容量素子
630 トランジスタ
631 ゲート電極
632 ゲート絶縁膜
633 酸化物半導体膜
634 チャネル保護膜
635 ソース電極
636 ドレイン電極
637 絶縁膜
640 トランジスタ
641 ゲート電極
642 ゲート絶縁膜
643 ソース電極
644 ドレイン電極
645 酸化物半導体膜
646 絶縁膜
650 トランジスタ
651 ソース電極
652 ドレイン電極
653 酸化物半導体膜
654 ゲート絶縁膜
655 ゲート電極
656 絶縁膜
660 半導体基板
661 nチャネル型トランジスタ
662 pチャネル型トランジスタ
663 絶縁膜
664 トランジスタ
665 容量素子
666 素子分離用絶縁膜
701 ゲート電極
702 ゲート電極
703 ゲート絶縁膜
730 酸化物半導体膜
731 酸化物半導体膜
732 酸化物半導体膜
733 酸化物半導体膜
734 酸化物半導体膜
735 酸化物半導体膜
736 酸化物半導体膜
900 基板
901 ALU
902 ALU Controller
903 Instruction Decoder
904 Interrupt Controller
905 Timing Controller
906 Register
907 Register Controller
908 Bus I/F
909 ROM
920 ROM I/F
1300 レジスタ
1301 インバータ
1302 インバータ
1303 スイッチング素子
1304 スイッチング素子
1310 pチャネル型トランジスタ
1311 nチャネル型トランジスタ
1312 pチャネル型トランジスタ
1313 nチャネル型トランジスタ
7001 筐体
7002 表示部
7011 筐体
7012 表示部
7013 支持台
7021 筐体
7022 表示部
7031 筐体
7032 筐体
7033 表示部
7034 表示部
7035 マイクロホン
7036 スピーカー
7037 操作キー
7038 スタイラス
7041 筐体
7042 表示部
7043 音声入力部
7044 音声出力部
7045 操作キー
7046 受光部
7051 筐体
7052 表示部
7053 操作キー
Claims (14)
- 互いに、他の出力端子が自らの入力端子に接続されることで、データの保持を行う第1の位相反転素子及び第2の位相反転素子と、容量素子と、チャネル形成領域に酸化物半導体を含み、前記容量素子への前記データの書き込みを制御するトランジスタとを、複数の各記憶素子に有する記憶装置。
- 第1の位相反転素子と、入力端子が前記第1の位相反転素子の出力端子に接続されている第2の位相反転素子と、前記第1の位相反転素子の入力端子への、データを含む信号の入力を制御する第1のスイッチング素子と、前記第1の位相反転素子の入力端子と前記第2の位相反転素子の出力端子との接続を制御する第2のスイッチング素子と、容量素子と、チャネル形成領域に酸化物半導体を含み、前記容量素子への前記データの書き込みを制御するトランジスタとを、複数の各記憶素子に有する記憶装置。
- 第1の位相反転素子と、入力端子が前記第1の位相反転素子の出力端子に接続されている第2の位相反転素子と、前記第1の位相反転素子の入力端子への、データを含む信号の入力を制御する第1のスイッチング素子と、前記第1の位相反転素子の入力端子と前記第2の位相反転素子の出力端子との接続を制御する第2のスイッチング素子と、容量素子と、チャネル形成領域に酸化物半導体を含み、前記第1の位相反転素子の入力端子と前記容量素子との接続を制御するトランジスタとを、複数の各記憶素子に有する記憶装置。
- 第1の位相反転素子と、入力端子が前記第1の位相反転素子の出力端子に接続されている第2の位相反転素子と、前記第1の位相反転素子の入力端子への、データを含む信号の入力を制御する第1のスイッチング素子と、前記第1の位相反転素子の入力端子と前記第2の位相反転素子の出力端子との接続を制御する第2のスイッチング素子と、前記第1の位相反転素子の出力端子の電位の出力を制御する第3のスイッチング素子と、容量素子と、チャネル形成領域に酸化物半導体を含み、前記容量素子への前記データの書き込みを制御するトランジスタと、前記容量素子に書き込まれた前記データを含む電位が、入力端子に与えられる第3の位相反転素子と、前記第3の位相反転素子の出力端子の電位の出力を制御する第4のスイッチング素子とを、複数の各記憶素子に有する記憶装置。
- 第1の位相反転素子と、入力端子が前記第1の位相反転素子の出力端子に接続されている第2の位相反転素子と、前記第1の位相反転素子の入力端子とデータを含む信号が入力されるノードとの接続を制御する第1のスイッチング素子と、前記第1の位相反転素子の入力端子と前記第2の位相反転素子の出力端子との接続を制御する第2のスイッチング素子と、前記第1の位相反転素子の出力端子の電位の出力を制御する第3のスイッチング素子と、容量素子と、チャネル形成領域に酸化物半導体を含み、前記ノードと前記容量素子との接続を制御するトランジスタと、前記容量素子に書き込まれた前記データを含む電位が、入力端子に与えられる第3の位相反転素子と、前記第3の位相反転素子の出力端子の電位の出力を制御する第4のスイッチング素子とを、複数の各記憶素子に有する記憶装置。
- 請求項1乃至請求項5のいずれか1項において、
前記トランジスタのオフ電流密度は、100zA/μm以下である記憶装置。 - 第1の位相反転素子と、入力端子が前記第1の位相反転素子の出力端子に接続されている第2の位相反転素子と、前記第1の位相反転素子の入力端子への、データを含む信号の入力を制御する第1のスイッチング素子と、前記第1の位相反転素子の入力端子と前記第2の位相反転素子の出力端子との接続を制御する第2のスイッチング素子と、第1の容量素子と、チャネル形成領域に酸化物半導体を含み、前記第1の容量素子への前記データの書き込みを制御する第1のトランジスタと、第2の容量素子と、チャネル形成領域に酸化物半導体を含み、前記第2の容量素子への前記データの書き込みを制御する第2のトランジスタと、を、複数の各記憶素子に有する記憶装置。
- 第1の位相反転素子と、入力端子が前記第1の位相反転素子の出力端子に接続されている第2の位相反転素子と、前記第1の位相反転素子の入力端子への、データを含む信号の入力を制御する第1のスイッチング素子と、前記第1の位相反転素子の入力端子と前記第2の位相反転素子の出力端子との接続を制御する第2のスイッチング素子と、第1の容量素子と、チャネル形成領域に酸化物半導体を含み、前記第1の位相反転素子の入力端子と前記第1の容量素子との接続を制御する第1のトランジスタと、第2の容量素子と、チャネル形成領域に酸化物半導体を含み、前記第1の位相反転素子の出力端子と前記第2の容量素子との接続を制御する第2のトランジスタとを、複数の各記憶素子に有する記憶装置。
- 請求項7または請求項8において、
前記第1のトランジスタまたは前記第2のトランジスタのオフ電流密度は、100zA/μm以下である記憶装置。 - 請求項1乃至請求項9のいずれか1項において、
前記位相反転素子は、インバータまたはクロックドインバータである記憶装置。 - 請求項1乃至請求項10のいずれか1項において、
前記酸化物半導体は、In−Ga−Zn−O系の酸化物半導体である記憶装置。 - 請求項1乃至請求項11のいずれか1項において、
前記チャネル形成領域の水素濃度は、5×1019/cm3以下である記憶装置。 - 請求項1乃至請求項12のいずれか1項に記載の記憶装置を用いた、CPU、DSP、またはマイクロコントローラを含むLSIである半導体装置。
- 請求項1乃至請求項12のいずれか1項に記載の記憶装置を用いた、ゲーム機、画像再生装置、またはパーソナルコンピュータを含む電子機器。
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