JP2011139051A - 半導体装置及びその作製方法 - Google Patents
半導体装置及びその作製方法 Download PDFInfo
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- JP2011139051A JP2011139051A JP2010268321A JP2010268321A JP2011139051A JP 2011139051 A JP2011139051 A JP 2011139051A JP 2010268321 A JP2010268321 A JP 2010268321A JP 2010268321 A JP2010268321 A JP 2010268321A JP 2011139051 A JP2011139051 A JP 2011139051A
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- oxide semiconductor
- film
- semiconductor film
- electrode
- heat treatment
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Abstract
【解決手段】酸化物半導体膜中の水分または水素などの不純物を低減するために、酸化物半導体膜を形成した後、酸化物半導体膜が露出した状態で第1の加熱処理を行う。次いで、酸化物半導体膜中の水分、または水素などの不純物をさらに低減するために、イオン注入法またはイオンドーピング法などを用いて、酸化物半導体膜に酸素を添加した後、再び、酸化物半導体膜が露出した状態で第2の加熱処理を行う。
【選択図】図1
Description
チャネルエッチ構造のボトムゲート型のトランジスタを例に挙げ、本発明の一態様に係る半導体装置が有する、トランジスタの構造とその作製方法について説明する。
本実施の形態では、さらに高電圧または大電流の制御が可能な、パワーデバイス向きであるトランジスタの構造及び作製方法について、説明する。なお、実施の形態1と同一部分又は同様な機能を有する部分、及び工程は、実施の形態1と同様に行うことができるため、繰り返しの説明は省略する。
本実施の形態では、チャネル保護構造のボトムゲート型のトランジスタを例に挙げ、半導体装置の構造及び作製方法について説明する。なお、実施の形態1と同一部分又は同様な機能を有する部分、及び工程は、実施の形態1と同様に行うことができるため、繰り返しの説明は省略する。
本実施の形態では、本発明の作製方法を用いて形成される半導体表示装置の一つである、電子ペーパー或いはデジタルペーパーと呼ばれる半導体表示装置の構成について説明する。
アクティブマトリクス型の半導体表示装置のブロック図の一例を図12(A)に示す。表示装置の基板5300上には、画素部5301、第1の走査線駆動回路5302、第2の走査線駆動回路5303、信号線駆動回路5304を有する。画素部5301には、複数の信号線が信号線駆動回路5304から延伸して配置され、複数の走査線が第1の走査線駆動回路5302、及び第2の走査線駆動回路5303から延伸して配置されている。なお走査線と信号線との交差領域には、各々、表示素子を有する画素がマトリクス状に配置されている。また、表示装置の基板5300はFPC(Flexible Printed Circuit)等の接続部を介して、タイミング制御回路5305(コントローラ、制御ICともいう)に接続されている。
本発明の一態様に係る液晶表示装置は、オフ電流が低く、なおかつ信頼性の高いトランジスタを用いているため、視認性が高く、信頼性も高い。本実施の形態では、本発明の一態様に係る液晶表示装置の構成について説明する。
本実施の形態では、本発明の一態様に係るトランジスタを画素に用いた、発光装置の構成について説明する。本実施の形態では、発光素子を駆動させるためのトランジスタがn型の場合における、画素の断面構造について、図18を用いて説明する。なお図18では、第1の電極が陰極、第2の電極が陽極の場合について説明するが、第1の電極が陽極、第2の電極が陰極であっても良い。
11 配線
12 配線
13 配線
14 配線
15 配線
21 入力端子
22 入力端子
23 入力端子
24 入力端子
25 入力端子
26 出力端子
27 出力端子
31 トランジスタ
32 トランジスタ
33 トランジスタ
34 トランジスタ
35 トランジスタ
36 トランジスタ
37 トランジスタ
38 トランジスタ
39 トランジスタ
40 トランジスタ
41 トランジスタ
42 トランジスタ
43 トランジスタ
51 電源線
52 電源線
53 電源線
100 基板
101 ゲート電極
102 ゲート絶縁膜
103 酸化物半導体膜
104 酸化物半導体膜
105 酸化物半導体膜
107 酸化物半導体膜
108 酸化物半導体膜
111 ソース電極
112 ドレイン電極
113 絶縁膜
114 トランジスタ
115 バックゲート電極
116 絶縁膜
130 チャネル保護膜
131 ソース電極
132 ドレイン電極
133 絶縁膜
140 トランジスタ
145 バックゲート電極
146 絶縁膜
150 酸化物半導体膜
151 酸化物半導体膜
152 酸化物半導体膜
153 酸化物半導体膜
200 基板
201 絶縁膜
202 電極
203 酸化物半導体膜
205 酸化物半導体膜
207 酸化物半導体膜
208 酸化物半導体膜
211 電極
212 ゲート絶縁膜
213 ゲート電極
214 絶縁膜
215 配線
216 配線
217 配線
218 部分
220 トランジスタ
221 コンタクトホール
222 コンタクトホール
223 コンタクトホール
230 配線
231 コンタクトホール
700 画素部
701 信号線駆動回路
702 走査線駆動回路
703 画素
704 トランジスタ
705 表示素子
706 保持容量
707 信号線
708 走査線
710 画素電極
711 対向電極
712 マイクロカプセル
713 ドレイン電極
714 樹脂
1401 トランジスタ
1402 ゲート電極
1403 ゲート絶縁膜
1404 酸化物半導体膜
1406a 導電膜
1406b 導電膜
1407 絶縁膜
1408 絶縁膜
1410 画素電極
1411 配向膜
1413 対向電極
1414 配向膜
1415 液晶
1416 シール材
1417 スペーサ
1420 基板
1601 液晶パネル
1602 拡散板
1603 プリズムシート
1604 拡散板
1605 導光板
1606 反射板
1607 光源
1608 回路基板
1609 FPC
1610 FPC
5300 基板
5301 画素部
5302 走査線駆動回路
5303 走査線駆動回路
5304 信号線駆動回路
5305 タイミング制御回路
5601 シフトレジスタ
5602 サンプリング回路
5603 トランジスタ
5604 配線
5605 配線
6031 トランジスタ
6033 発光素子
6034 電極
6035 電界発光層
6036 電極
6037 絶縁膜
6038 隔壁
6041 トランジスタ
6043 発光素子
6044 電極
6045 電界発光層
6046 電極
6047 絶縁膜
6048 隔壁
6051 トランジスタ
6053 発光素子
6054 電極
6055 電界発光層
6056 電極
6057 絶縁膜
6058 隔壁
7001 筐体
7002 表示部
7011 筐体
7012 表示部
7013 支持台
7021 筐体
7022 表示部
7031 筐体
7032 筐体
7033 表示部
7034 表示部
7035 マイクロホン
7036 スピーカー
7037 操作キー
7038 スタイラス
7041 筐体
7042 表示部
7043 音声入力部
7044 音声出力部
7045 操作キー
7046 受光部
7051 筐体
7052 表示部
7053 操作キー
Claims (13)
- 酸化物半導体膜に第1の加熱処理を施し、
前記第1の加熱処理が施された酸化物半導体膜に酸素を添加し、
前記酸素が添加された前記酸化物半導体膜に第2の加熱処理を施す半導体装置の作製方法。 - 酸化物半導体膜をエッチングにより加工することで、島状の酸化物半導体膜を形成し、
前記島状の酸化物半導体膜に第1の加熱処理を施し、
前記第1の加熱処理が施された前記島状の酸化物半導体膜に酸素を添加し、
前記酸素が添加された前記島状の酸化物半導体膜に第2の加熱処理を施す半導体装置の作製方法。 - 絶縁表面上において、ゲート絶縁膜を間に挟んでゲート電極上に酸化物半導体膜を形成し、
前記酸化物半導体膜をエッチングにより加工することで、ゲート絶縁膜を間に挟んでゲート電極と重なる位置に島状の酸化物半導体膜を形成し、
前記島状の酸化物半導体膜に第1の加熱処理を施し、
前記第1の加熱処理が施された前記島状の酸化物半導体膜に酸素を添加し、
前記酸素が添加された前記島状の酸化物半導体膜に第2の加熱処理を施し、
前記第2の加熱処理が施された島状の酸化物半導体膜上に、ソース電極及びドレイン電極を形成する半導体装置の作製方法。 - 絶縁表面上において、ゲート絶縁膜を間に挟んでゲート電極上に酸化物半導体膜を形成し、
前記酸化物半導体膜をエッチングにより加工することで、ゲート絶縁膜を間に挟んでゲート電極と重なる位置に島状の酸化物半導体膜を形成し、
前記島状の酸化物半導体膜に第1の加熱処理を施し、
前記第1の加熱処理が施された前記島状の酸化物半導体膜に酸素を添加し、
前記酸素が添加された前記島状の酸化物半導体膜に第2の加熱処理を施し、
前記第2の加熱処理が施された島状の酸化物半導体膜上に、ソース電極及びドレイン電極を形成し、
前記島状の酸化物半導体膜、前記ソース電極及び前記ドレイン電極上に、前記島状の酸化物半導体膜と接するように、酸素を含む絶縁膜を形成する半導体装置の作製方法。 - 絶縁表面上において、ゲート絶縁膜を間に挟んでゲート電極上に酸化物半導体膜を形成し、
前記酸化物半導体膜に第1の加熱処理を施し、
前記第1の加熱処理が施された前記酸化物半導体膜に酸素を添加し、
前記酸素が添加された前記酸化物半導体膜に第2の加熱処理を施し、
前記第2の加熱処理が施された前記酸化物半導体膜をエッチングにより加工することで、ゲート絶縁膜を間に挟んでゲート電極と重なる位置に島状の酸化物半導体膜を形成し、
前記島状の酸化物半導体膜上に、ソース電極及びドレイン電極を形成する半導体装置の作製方法。 - 絶縁表面上において、ゲート絶縁膜を間に挟んでゲート電極上に酸化物半導体膜を形成し、
前記酸化物半導体膜に第1の加熱処理を施し、
前記第1の加熱処理が施された前記酸化物半導体膜に酸素を添加し、
前記酸素が添加された前記酸化物半導体膜に第2の加熱処理を施し、
前記第2の加熱処理が施された前記酸化物半導体膜をエッチングにより加工することで、ゲート絶縁膜を間に挟んでゲート電極と重なる位置に島状の酸化物半導体膜を形成し、
前記島状の酸化物半導体膜上に、ソース電極及びドレイン電極を形成し、
前記島状の酸化物半導体膜、前記ソース電極及び前記ドレイン電極上に、前記島状の酸化物半導体膜と接するように、酸素を含む絶縁膜を形成する半導体装置の作製方法。 - 絶縁表面上において、ゲート絶縁膜を間に挟んでゲート電極上に酸化物半導体膜を形成し、
前記酸化物半導体膜をエッチングにより加工することで、ゲート絶縁膜を間に挟んでゲート電極と重なる位置に島状の酸化物半導体膜を形成し、
前記島状の酸化物半導体膜に第1の加熱処理を施し、
前記第1の加熱処理が施された前記島状の酸化物半導体膜に酸素を添加し、
前記酸素が添加された前記島状の酸化物半導体膜に第2の加熱処理を施し、
前記第2の加熱処理が施された島状の酸化物半導体膜上に、前記ゲート電極と重なる位置にチャネル保護膜を形成する半導体装置の作製方法。 - 絶縁表面上において、ゲート絶縁膜を間に挟んでゲート電極上に酸化物半導体膜を形成し、
前記酸化物半導体膜に第1の加熱処理を施し、
前記第1の加熱処理が施された前記酸化物半導体膜に酸素を添加し、
前記酸素が添加された前記酸化物半導体膜に第2の加熱処理を施し、
前記第2の加熱処理が施された酸化物半導体膜をエッチングにより加工することで、ゲート絶縁膜を間に挟んでゲート電極と重なる位置に島状の酸化物半導体膜を形成し、
前記島状の酸化物半導体膜上に、前記ゲート電極と重なる位置にチャネル保護膜を形成する半導体装置の作製方法。 - 請求項7または請求項8において、
前記チャネル保護膜は、酸素を含む絶縁膜である半導体装置の作製方法。 - 絶縁表面上に第1の電極を形成し、
前記第1の電極上に酸化物半導体膜を形成し、
前記酸化物半導体膜をエッチングにより加工することで、前記第1の電極と重なる位置に島状の酸化物半導体膜を形成し、
前記島状の酸化物半導体膜に第1の加熱処理を施し、
前記第1の加熱処理が施された前記島状の酸化物半導体膜に酸素を添加し、
前記酸素が添加された前記島状の酸化物半導体膜に第2の加熱処理を施し、
前記第2の加熱処理が施された前記島状の酸化物半導体膜上に、前記第1の電極と離隔する第2の電極を形成し、
前記第1の電極、前記島状の酸化物半導体膜、及び前記第2の電極を覆うようにゲート絶縁膜を形成し、
前記ゲート絶縁膜を間に挟んで、前記島状の酸化物半導体膜の端部と重なるように、ゲート電極を形成する半導体装置の作製方法。 - 絶縁表面上に第1の電極を形成し、
前記第1の電極上に酸化物半導体膜を形成し、
前記酸化物半導体膜に第1の加熱処理を施し、
前記第1の加熱処理が施された前記酸化物半導体膜に酸素を添加し、
前記酸素が添加された前記酸化物半導体膜に第2の加熱処理を施し、
前記第2の加熱処理が施された前記酸化物半導体膜をエッチングにより加工することで、島状の酸化物半導体膜を形成し、
前記島状の酸化物半導体膜上に、前記第1の電極と離隔する第2の電極を形成し、
前記第1の電極、前記島状の酸化物半導体膜、及び前記第2の電極を覆うようにゲート絶縁膜を形成し、
前記ゲート絶縁膜を間に挟んで、前記島状の酸化物半導体膜の端部と重なるように、ゲート電極を形成する半導体装置の作製方法。 - 請求項1乃至請求項11のいずれか1項において、
前記酸素の添加は、イオン注入法またはイオンドーピング法を用いて行う半導体装置の作製方法。 - 請求項1乃至請求項11のいずれか1項において、
前記第1の加熱処理または前記第2の加熱処理は、300℃以上850℃以下の範囲で行う半導体装置の作製方法。
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JP2013070039A (ja) * | 2011-09-07 | 2013-04-18 | Semiconductor Energy Lab Co Ltd | 半導体装置及び半導体装置の作製方法 |
KR20130045173A (ko) * | 2011-10-24 | 2013-05-03 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 반도체 장치의 제작 방법 |
JP2013149681A (ja) * | 2012-01-17 | 2013-08-01 | Asahi Kasei Electronics Co Ltd | ホール素子 |
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JP2014241406A (ja) * | 2013-05-16 | 2014-12-25 | 株式会社半導体エネルギー研究所 | 半導体装置 |
KR20140135651A (ko) * | 2013-05-16 | 2014-11-26 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
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JP2019216268A (ja) * | 2013-05-16 | 2019-12-19 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP2015005672A (ja) * | 2013-06-21 | 2015-01-08 | 出光興産株式会社 | 酸化物トランジスタ |
JP2015181162A (ja) * | 2014-03-06 | 2015-10-15 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
JP2020004981A (ja) * | 2014-04-18 | 2020-01-09 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JPWO2016067161A1 (ja) * | 2014-10-28 | 2017-08-31 | 株式会社半導体エネルギー研究所 | 半導体装置およびその作製方法 |
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