JP2008072051A - 不揮発性半導体記憶装置及びその製造方法 - Google Patents
不揮発性半導体記憶装置及びその製造方法 Download PDFInfo
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
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Abstract
【解決手段】基板と、第1の柱状半導体を有する第1の選択トランジスタと、前記第1の柱状半導体上に形成された第2の柱状半導体と、前記第2の柱状半導体の周りに形成された第1の絶縁膜と、前記第1の絶縁膜の周りに形成された電荷蓄積層と、前記電荷蓄積層の周りに形成された第2の絶縁膜と、前記第2の絶縁膜の周りに形成された平板状の第1乃至第nの電極(nは2以上の自然数)とを有する複数のメモリセルと、第3の柱状半導体を有する第2の選択トランジスタと、を有するメモリストリングスを複数備え、前記メモリストリングスは前記第1乃至第nの電極を2次元的に共有し、前記第1の柱状半導体の接続部のみが前記第2の柱状半導体の径よりも大きい不揮発性半導体記憶装置。
【選択図】図17
Description
本発明の第1の実施形態に係る不揮発性半導体記憶装置1の概略構成図を図1に示す。本発明の第1の実施形態に係る不揮発性半導体記憶装置1は、メモリトランジスタ領域2、ワード線駆動回路3、ソース側選択ゲート線(SGS)駆動回路4、ドレイン側選択ゲート線(SGD)駆動回路5、センスアンプ6、ワード線WL7、ビット線BL8、ソース側選択ゲート線SGS30、ドレイン側選択ゲート線SGD31等を有している。図1に示すように、本発明の第1の実施形態に係る不揮発性半導体記憶装置1においては、メモリトランジスタ領域2を構成するメモリトランジスタは、半導体層を複数積層することによって一括して形成されている。また、図1に示すとおり各層のワード線は、ある領域で2次元的に広がっている。各層のワード線は、それぞれ同一層からなる平面構造を有しており、板状の平面構造となっている。かかる構造により、PEPを含めた加工工程が大幅に短縮されている。
図4は、本発明の第1の実施形態に係る不揮発性半導体記憶装置1において、点線で示したメモリトランジスタMTr321(40)のデータの読み出し動作を行う場合のバイアス状態を示した図である。ここでは、本実施形態におけるメモリトランジスタMTrは、所謂MONOS型縦型トランジスタであり、電荷蓄積層に電子が蓄積されていない状態のメモリトランジスタMTrのしきい値Vth(中性しきい値)が0V付近にあるとして説明する。
図5は、本発明の第1の実施形態に係る不揮発性半導体記憶装置1において、点線で示したメモリトランジスタMTr321(40)のデータの書き込み動作を行う場合のバイアス状態を示した図である。
データの消去は、複数のメモリストリングスからなるブロック単位で行う。図6は、本発明の第1の実施形態に係る不揮発性半導体記憶装置1において、選択したブロックのメモリトランジスタMTrのデータの消去動作を行う場合の選択ブロックのバイアス状態を示した図である。図7は、本発明の第1の実施形態に係る不揮発性半導体記憶装置1において、消去動作時における非選択ブロックのバイアス状態を示した図である。
本発明の第1の実施形態に係る不揮発性半導体記憶装置は、詳細な製造方法は以下に説明するが、概略下部セレクトゲート(SGS)層、メモリセル層、上部セレクトゲート(SGD)層を各層毎に形成し、各層毎にコンタクトホールをフォトエッチング工程で形成し、ホールにアモルファスシリコン
(a−Si)やポリシリコン(Poly−Si)等を堆積してチャネルを形成する工程を経る。従って、加工寸法のバラツキやコンタクトの合せズレにより、各層のチャネルのコンタクトの接触面積が減少する場合が生じる。また、メモリセル層のチャネルが形成されるメモリプラグホールをフォトエッチング工程で形成する場合に、エッチングガスの切り替え、堆積物の除去、膜の材料などの種々の要因によって、ホールを垂直に加工することが困難で、ホールの下部の径が小さくなり順テーパー状の形状となることが生じる。これは、特に容量の増大を図るためにメモリセル層を数多く積層し、加工するホールの深さが深くなるほど顕著となる。これも接触面積の減少の一因となる。
上述したように、本発明の第1の実施形態に係る不揮発性半導体記憶装置は、メモリセルが三次元的に積層される構造を有し、下部セレクトゲート(SGS)層、メモリセル層及び上部セレクトゲート(SGD)層が層毎に形成されて積層され、更にビット線等のメタル配線層が形成される。この際、加工寸法のバラツキや合せズレ等が生じるが、かかる加工寸法のバラツキや合せズレは、上部セレクトゲート(SGD)層とメタル配線層との間でも生じる。しかし上述したように、上部セレクトゲート(SGD)層のチャネル部を構成する柱状のアモルファスシリコン層(又は、ポリシリコン層。)とメタル配線層の例えばタングステンプラグ等の金属プラグとの間では、シリコンと金属であるため本来的に抵抗が小さいため、接触面積の減少により抵抗が上がっても信頼性を損なうほどの影響は生じない。従って、上部セレクトゲート(SGD)層のチャネルが形成されるトランジスタプラグホールについては、ホール上部のみ径を大きく形成する必要はなく、前記トランジスタプラグホールは、1PEPで概略同一径に形成される。
10:メモリストリングス
126:ポリシリコン膜
127:酸化珪素膜(TEOS膜)
128:窒化珪素膜
130a: (SGS)トランジスタプラグホール
132a、132c:熱酸化膜
136:柱状のアモルファスシリコン層(第1の柱状半導体)
150、154、158、162、166:アモルファスシリコン膜
152、156、160、164:酸化珪素膜
168:窒化珪素膜
170:メモリプラグホール
172:ONO膜
180:柱状のアモルファスシリコン層(第2の柱状半導体)
189:熱酸化膜
193、193a、193b、193c、193d:柱状のアモルファスシリコン層(第3の柱状半導体)
197:窒化珪素スペーサ
Claims (5)
- 基板と、
前記基板に対して垂直に形成された第1の柱状半導体と、前記第1の柱状半導体の周りに形成された第1のゲート絶縁膜と、前記第1のゲート絶縁膜の周りに形成された第1のゲート電極とを有する第1の選択トランジスタと、
前記第1の柱状半導体上に形成された第2の柱状半導体と、前記第2の柱状半導体の周りに形成された第1の絶縁膜と、前記第1の絶縁膜の周りに形成された電荷蓄積層と、前記電荷蓄積層の周りに形成された第2の絶縁膜と、前記第2の絶縁膜の周りに形成された平板状の第1乃至第nの電極(nは2以上の自然数)とを有する複数のメモリセルと、
前記第2の柱状半導体上に形成された第3の柱状半導体と、前記第3の柱状半導体の周りに形成された第2のゲート絶縁膜と、前記第2のゲート絶縁膜の周りに形成された第2のゲート電極とを有する第2の選択トランジスタと、
を有するメモリストリングスを複数備え、
複数の前記メモリストリングスは前記第1乃至第nの電極を2次元的に共有し、前記第2の柱状半導体と接続する前記第1の柱状半導体の接続部のみが前記第2の柱状半導体の径よりも大きいことを特徴とする不揮発性半導体記憶装置。 - さらに、前記第3の柱状半導体と接続する前記第2の柱状半導体の接続部のみが前記第3の柱状半導体の径よりも大きいことを特徴とする請求項1記載の不揮発性半導体記憶装置。
- 前記第2の選択トランジスタは、金属プラグを介してビット線と接続され、
前記金属プラグが前記第3の柱状半導体と接続される部分において、前記金属プラグの径が前記第3の柱状半導体の径よりも小さく形成されていることを特徴とする請求項1乃至請求項3記載の不揮発性半導体記憶装置。 - 半導体基板上に導電性不純物の拡散領域を形成し、
前記半導体基板上に導電体膜を形成し、
前記導電体膜上に保護膜を形成し、
前記導電体膜と前記保護膜に第1のホールを形成し、
前記第1のホールの保護膜部分における径を大きく加工し、
前記第1のホールに第1の柱状半導体を形成し、
前記保護膜及び前記第1の柱状半導体上に第1の絶縁膜と導電体膜とを交互に複数形成し、
前記複数の第1の絶縁膜と前記導電体膜に第2のホールを形成し、
前記第2のホールの内側表面に第2の絶縁膜を形成し、
前記第2のホールに第2の柱状半導体を形成することを特徴とする不揮発性半導体記憶装置の製造方法。 - 前記導電体膜を形成した後、前記保護膜を形成する前に、前記導電体膜上に第3の絶縁膜を形成することを特徴とする請求項4記載の不揮発性半導体記憶装置の製造方法。
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US20080067583A1 (en) | 2008-03-20 |
US8278695B2 (en) | 2012-10-02 |
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