JP2007507108A5 - - Google Patents

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Publication number
JP2007507108A5
JP2007507108A5 JP2006528047A JP2006528047A JP2007507108A5 JP 2007507108 A5 JP2007507108 A5 JP 2007507108A5 JP 2006528047 A JP2006528047 A JP 2006528047A JP 2006528047 A JP2006528047 A JP 2006528047A JP 2007507108 A5 JP2007507108 A5 JP 2007507108A5
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Prior art keywords
lead frame
die
pad
wire
semiconductor die
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JP2006528047A
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English (en)
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JP4608494B2 (ja
JP2007507108A (ja
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Priority claimed from US10/670,631 external-priority patent/US7030469B2/en
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Publication of JP2007507108A publication Critical patent/JP2007507108A/ja
Publication of JP2007507108A5 publication Critical patent/JP2007507108A5/ja
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Claims (5)

  1. ダイパッド(13)及びボンドパッド(33)を有するリードフレーム(10)と、
    前記ダイパッドに取り付けられ、前記ボンドパッドに電気的に接続された半導体ダイ(25)と、
    前記半導体ダイ上に配置されたモールド封入材(35)と、
    前記モールド封入材上に配置された導電層(42)と、
    前記リードフレームを前記導電層に電気的に接続するワイヤ(33)と
    を備える半導体パッケージ(2)。
  2. 前記導電層が強磁性材料を含む請求項1に記載の半導体パッケージ。
  3. 半導体パッケージ(2)を形成する方法であって、
    第1ダイパッド(13)を含む第1の部分と、第2ダイパッド(15)を含む第2の部分とを備えたリードフレーム(10)を提供する工程と、
    前記第1ダイパッドに第1半導体ダイ(25)を取り付ける工程と、
    前記第2ダイパッドに第2半導体ダイ(27)を取り付ける工程と、
    前記第1半導体ダイを前記リードフレームに電気的に接続する工程と、
    前記第2半導体ダイを前記リードフレームに電気的に接続する工程と、
    ワイヤボンド(33)を使用して、前記リードフレームの第1の部分を前記リードフレームの第2の部分に電気的に接続する工程と、
    前記第1半導体ダイ及び第2半導体ダイをモールド封入材(35)によって封入する工程と、
    前記ワイヤボンドを切断して、前記リードフレームの第1の部分に第1ワイヤ(33)を、前記リードフレームの第2の部分に第2ワイヤ(33)をそれぞれ形成するために、前記モールド封入材をカットする工程と、
    前記封入材上に導電層(42)を形成して、前記第1ワイヤ及び第2ワイヤを前記導電層に電気的に接続する工程と、
    前記リードフレームの第1の部分を単一化して、半導体パッケージを形成する工程と
    を含む方法。
  4. 半導体パッケージ(2)を形成する方法であって、
    パッド(13)及びダイパッド(33)を含むリードフレーム(10)を提供する工程と、
    前記ダイパッドに半導体ダイ(35)を取り付ける工程と、
    前記半導体ダイを前記パッドに電気的に接続する工程と、
    第1端部及び第2端部を有するワイヤボンドを設ける工程と、
    前記ワイヤボンドの第1端部及び第2端部を前記半導体ダイに電気的に接続する工程と、
    前記半導体ダイ及びワイヤボンド上にモールド封入材を形成する工程と、
    前記ワイヤボンドの一部を露出させる工程と、
    前記モールド封入材及びワイヤボンド上に、前記ワイヤボンドに電気的に接続した導電層(42)を形成する工程と
    を含む方法。
  5. 半導体パッケージ(2)を形成する方法であって、
    ダイパッド(13)を有するリードフレーム(10)を提供する工程と、
    前記ダイパッドに半導体ダイ(25)を取り付ける工程と、
    前記半導体ダイ上にモールド封入材(35)を形成する工程と、
    前記モールド封入材上に導電層(42)を形成する工程と、
    ワイヤ(33)を使用して、前記リードフレームを前記導電層に電気的に接続する工程と
    を含む方法。
JP2006528047A 2003-09-25 2004-09-14 半導体パッケージの形成方法及びその構造 Active JP4608494B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/670,631 US7030469B2 (en) 2003-09-25 2003-09-25 Method of forming a semiconductor package and structure thereof
PCT/US2004/029845 WO2005050699A2 (en) 2003-09-25 2004-09-14 Method of forming a semiconductor package and structure thereof

Publications (3)

Publication Number Publication Date
JP2007507108A JP2007507108A (ja) 2007-03-22
JP2007507108A5 true JP2007507108A5 (ja) 2007-10-11
JP4608494B2 JP4608494B2 (ja) 2011-01-12

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JP2006528047A Active JP4608494B2 (ja) 2003-09-25 2004-09-14 半導体パッケージの形成方法及びその構造

Country Status (7)

Country Link
US (1) US7030469B2 (ja)
EP (1) EP1668699A2 (ja)
JP (1) JP4608494B2 (ja)
KR (1) KR101076972B1 (ja)
CN (1) CN100561732C (ja)
TW (1) TWI365529B (ja)
WO (1) WO2005050699A2 (ja)

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