JP2007507108A - 半導体パッケージの形成方法及びその構造 - Google Patents
半導体パッケージの形成方法及びその構造 Download PDFInfo
- Publication number
- JP2007507108A JP2007507108A JP2006528047A JP2006528047A JP2007507108A JP 2007507108 A JP2007507108 A JP 2007507108A JP 2006528047 A JP2006528047 A JP 2006528047A JP 2006528047 A JP2006528047 A JP 2006528047A JP 2007507108 A JP2007507108 A JP 2007507108A
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- Prior art keywords
- pad
- conductive layer
- lead frame
- die
- wire
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Abstract
Description
利点、他の効果、及び問題の解決方法を、特定の実施形態に関して説明してきた。しかしながら、利点、効果、問題の解決方法、ならびに、任意の利点、効果、又は解決方法を生むいかなる要素、あるいはそれらをより顕著にするいかなる要素も、いずれかの請求項又は全ての請求項の、不可欠な、必要な、又は必須の特徴又は要素として解釈すべきではない。本明細書においては、「含む(comprises) 」、「含んでいる(comprising)」という語又はそれらを変化させたいかなる語も、列挙された要素を含む工程、方法、物品、又は装置がこれらの要素のみを含むのではなく、明確に挙げられていない、又はこのような工程、方法、物品又は装置に固有の他の要素も含むように、非排他的に含まれているものにも及ぶものとする。本明細書で使用する「一つの(a又はan)」という語は、一つ又は複数を指すものとして定義する。本明細書で使用する「複数の」という言葉は、2以上の数を指すものとして定義する。本明細書で使用する「別の」という言葉は、少なくとも2番目以上のものを指すものとして定義する。本明細書で使用する「接続された(coupled) 」という言葉は、接続された状態を指すが、接続は必ずしも直接的なものでなくてもよく、また必ずしも機械的に接続されていなくてもよい。さらに、詳細な説明及び請求項において「前部」、「後部」、「上部」、「底部」、「上に」、「下に」及びこれらに類する言葉がある場合は、これらの言葉は説明のために使用するものであり、必ずその相対的位置になければならないことを示すものではない。このように使用されるこうした語は、本明細書に記載する発明の実施形態が、例えば例示した以外の方向性において、又は本明細書に記載した以外の方法で動作可能であるように、適切な状況下で置き替え可能である。
Claims (10)
- ダイパッド(13)及びボンドパッド(33)を有するリードフレーム(10)と、
前記ダイパッドに取り付けられ、前記ボンドパッドに電気的に接続された半導体ダイ(25)と、
前記半導体ダイ上に配置されたモールド封入材(35)と、
前記モールド封入材上に配置された導電層(42)と、
前記リードフレームを前記導電層に電気的に接続するワイヤ(33)と
を備える半導体パッケージ(2)。 - 前記導電層が強磁性材料を含む請求項1に記載の半導体パッケージ。
- 前記ワイヤが、前記半導体ダイ及びワイヤボンド(29)を介して前記リードフレームに接続される、請求項1に記載の半導体パッケージ。
- 前記ワイヤが、パッドを介して前記リードフレームに接続される、請求項1に記載の半導体パッケージ。
- 前記導電層が電磁シールドである請求項1に記載の半導体パッケージ。
- 半導体パッケージ(2)を形成する方法であって、
第1ダイパッド(13)を含む第1の部分と、第2ダイパッド(15)を含む第2の部分とを備えたリードフレーム(10)を提供する工程と、
前記第1ダイパッドに第1半導体ダイ(25)を取り付ける工程と、
前記第2ダイパッドに第2半導体ダイ(27)を取り付ける工程と、
前記第1半導体ダイを前記リードフレームに電気的に接続する工程と、
前記第2半導体ダイを前記リードフレームに電気的に接続する工程と、
ワイヤボンド(33)を使用して、前記リードフレームの第1の部分を前記リードフレームの第2の部分に電気的に接続する工程と、
前記第1半導体ダイ及び第2半導体ダイをモールド封入材(35)によって封入する工程と、
前記ワイヤボンドを切断して、前記リードフレームの第1の部分に第1ワイヤ(33)を、前記リードフレームの第2の部分に第2ワイヤ(33)をそれぞれ形成するために、前記モールド封入材をカットする工程と、
前記封入材上に導電層(42)を形成して、前記第1ワイヤ及び第2ワイヤを前記導電層に電気的に接続する工程と、
前記リードフレームの第1の部分を単一化して、半導体パッケージを形成する工程と
を含む方法。 - 前記モールド封入材をカットする工程が、前記モールド封入材に側壁を有する溝(40)を形成する工程をさらに含み、前記第1ワイヤの一部と前記第2ワイヤの一部とが前記溝において露出されることと、
前記導電層を形成する工程が、前記溝の側壁に前記導電層を形成する工程をさらに含む、
請求項9に記載の方法。 - 半導体パッケージ(2)を形成する方法であって、
パッド(13)及びダイパッド(33)を含むリードフレーム(10)を提供する工程と、
前記ダイパッドに半導体ダイ(35)を取り付ける工程と、
前記半導体ダイを前記パッドに電気的に接続する工程と、
第1端部及び第2端部を有するワイヤボンドを設ける工程と、
前記ワイヤボンドの第1端部及び第2端部を前記半導体ダイに電気的に接続する工程と、
前記半導体ダイ及びワイヤボンド上にモールド封入材を形成する工程と、
前記ワイヤボンドの一部を露出させる工程と、
前記モールド封入材及びワイヤボンド上に、前記ワイヤボンドに電気的に接続した導電層(42)を形成する工程と
を含む方法。 - 半導体パッケージ(2)を形成する方法であって、
ダイパッド(13)を有するリードフレーム(10)を提供する工程と、
前記ダイパッドに半導体ダイ(25)を取り付ける工程と、
前記半導体ダイ上にモールド封入材(35)を形成する工程と、
前記モールド封入材上に導電層(42)を形成する工程と、
ワイヤ(33)を使用して、前記リードフレームを前記導電層に電気的に接続する工程と
を含む方法。 - ワイヤを使用してリードフレームを導電層に電気的に接続する前記工程が、
第1端部及び第2端部を有するワイヤを設ける工程と、
前記ワイヤの第1端部及び第2端部を前記半導体ダイに電気的に接続する工程と、
前記ワイヤの一部を露出させるために、前記モールド封入材の一部を除去する工程と
をさらに含み、
前記導電層を形成する工程が、
前記導電層を前記ワイヤに電気的に接続する工程
をさらに含む、請求項20に記載の方法。
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US10/670,631 US7030469B2 (en) | 2003-09-25 | 2003-09-25 | Method of forming a semiconductor package and structure thereof |
PCT/US2004/029845 WO2005050699A2 (en) | 2003-09-25 | 2004-09-14 | Method of forming a semiconductor package and structure thereof |
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- 2004-09-14 JP JP2006528047A patent/JP4608494B2/ja not_active Expired - Fee Related
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JP2010010441A (ja) * | 2008-06-27 | 2010-01-14 | Murata Mfg Co Ltd | 回路モジュールの製造方法および回路モジュール |
JP2011529638A (ja) * | 2008-07-31 | 2011-12-08 | スカイワークス ソリューションズ,インコーポレイテッド | 一体化された干渉シールドを備えた半導体パッケージおよびその製造方法 |
US8748230B2 (en) | 2008-07-31 | 2014-06-10 | Skyworks Solutions, Inc. | Semiconductor package with integrated interference shielding and method of manufacture thereof |
US8987889B2 (en) | 2008-07-31 | 2015-03-24 | Skyworks Solutions, Inc. | Semiconductor package with integrated interference shielding and method of manufacture thereof |
JP2017143312A (ja) * | 2013-02-08 | 2017-08-17 | クアルコム,インコーポレイテッド | 磁気抵抗ランダムアクセスメモリ(mram)のためのスモールフォームファクタ磁気シールド |
KR20150050859A (ko) * | 2013-11-01 | 2015-05-11 | 에스케이하이닉스 주식회사 | 반도체 패키지 및 그의 제조방법 |
KR102172786B1 (ko) * | 2013-11-01 | 2020-11-02 | 에스케이하이닉스 주식회사 | 반도체 패키지 및 그의 제조방법 |
US10396039B2 (en) | 2014-12-09 | 2019-08-27 | Mitsubishi Electric Corporation | Semiconductor package |
WO2016092633A1 (ja) * | 2014-12-09 | 2016-06-16 | 三菱電機株式会社 | 半導体パッケージ |
JPWO2016092633A1 (ja) * | 2014-12-09 | 2017-04-27 | 三菱電機株式会社 | 半導体パッケージ |
JP2017220654A (ja) * | 2016-06-11 | 2017-12-14 | 新日本無線株式会社 | 電磁シールドを備えた半導体装置及びその製造方法 |
KR101962017B1 (ko) * | 2016-06-29 | 2019-03-25 | 미쓰비시덴키 가부시키가이샤 | 반도체 장치 및 그 제조 방법 |
US10373898B2 (en) | 2016-06-29 | 2019-08-06 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing the same |
KR20180002531A (ko) * | 2016-06-29 | 2018-01-08 | 미쓰비시덴키 가부시키가이샤 | 반도체 장치 및 그 제조 방법 |
CN107887283A (zh) * | 2016-09-30 | 2018-04-06 | 株式会社迪思科 | 半导体封装的制造方法 |
JP2018056501A (ja) * | 2016-09-30 | 2018-04-05 | 株式会社ディスコ | 半導体パッケージの製造方法 |
CN107887283B (zh) * | 2016-09-30 | 2023-03-31 | 株式会社迪思科 | 半导体封装的制造方法 |
JP2018107408A (ja) * | 2016-12-28 | 2018-07-05 | 株式会社ディスコ | 半導体パッケージの製造方法 |
JP2020193304A (ja) * | 2019-05-30 | 2020-12-03 | 東洋紡株式会社 | インサート成形用樹脂組成物、電子部品の封止体、及び電子部品の封止体の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
WO2005050699A3 (en) | 2005-12-22 |
KR20060098431A (ko) | 2006-09-18 |
EP1668699A2 (en) | 2006-06-14 |
TW200524127A (en) | 2005-07-16 |
CN1856878A (zh) | 2006-11-01 |
TWI365529B (en) | 2012-06-01 |
JP4608494B2 (ja) | 2011-01-12 |
US20050067676A1 (en) | 2005-03-31 |
KR101076972B1 (ko) | 2011-10-26 |
CN100561732C (zh) | 2009-11-18 |
US7030469B2 (en) | 2006-04-18 |
WO2005050699A2 (en) | 2005-06-02 |
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