JP2011529638A - 一体化された干渉シールドを備えた半導体パッケージおよびその製造方法 - Google Patents
一体化された干渉シールドを備えた半導体パッケージおよびその製造方法 Download PDFInfo
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- JP2011529638A JP2011529638A JP2011521084A JP2011521084A JP2011529638A JP 2011529638 A JP2011529638 A JP 2011529638A JP 2011521084 A JP2011521084 A JP 2011521084A JP 2011521084 A JP2011521084 A JP 2011521084A JP 2011529638 A JP2011529638 A JP 2011529638A
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- wire bond
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- semiconductor module
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 150000001875 compounds Chemical class 0.000 claims abstract description 47
- 230000000694 effects Effects 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 56
- 230000008569 process Effects 0.000 claims description 29
- 238000005452 bending Methods 0.000 claims description 19
- 238000000465 moulding Methods 0.000 claims description 17
- 238000001465 metallisation Methods 0.000 claims description 16
- 238000001721 transfer moulding Methods 0.000 claims description 15
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052737 gold Inorganic materials 0.000 claims description 9
- 239000010931 gold Substances 0.000 claims description 9
- 239000004593 Epoxy Substances 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 5
- 239000004332 silver Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 239000002184 metal Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 238000013461 design Methods 0.000 description 6
- 239000004020 conductor Substances 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 238000012858 packaging process Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000005489 elastic deformation Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000010422 painting Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000007592 spray painting technique Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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Abstract
Description
発明の分野
本発明は、半導体装置パッケージに関し、より特定的には半導体装置のための電磁および/または無線周波数干渉シールドに関する。
無線周波数(RF)通信システムでは、一般的に、RF装置を他のRF装置から発生した電磁(無線周波数)干渉(EMI)から隔離することが、適切な装置性能を維持するために必要である。同様に、RF装置は、一般的に、環境から受けるまたは環境に伝達される電磁干渉から隔離する必要がある。
本発明の局面および実施例は、ワイヤボンドプロセス技術を用いて電磁干渉シールドを装置のパッケージに組込んだ半導体装置パッケージおよびこの半導体装置パッケージの製造方法に関する。ある実施例では、ワイヤボンドプロセスを用いて、装置の周りに配置され装置の上下の導電層に結合されるワイヤボンドばねを形成することによって、装置の周りに電磁干渉シールドを形成する。以下でさらに説明するように、ワイヤボンドばねの形状およびワイヤボンドばねによって生まれるばね効果により、安定した製造プロセスによって、成形されたパッケージの上端にある導電層とパッケージの基板内の接地面との間に信頼性の高い電気的接続を形成することができる。これらのワイヤボンドばねを使用することにより、どのようなオーバーモールドされた装置にも適用し得る一体化された電磁干渉シールドに対する柔軟性のある解決策が得られる。
無線周波数(RF)成分を使用する、携帯電話端末、携帯情報端末(PDA)、メディアプレイヤー、およびその他の携帯機器を含む数多くの現代の用途では、完成品の大きさ(長さ、幅および厚み)ならびに重量が重要な設計パラメータであることが多い。たとえば、特に携帯電話端末については、より多くの機能性および特徴を提供するより小型でより軽量の装置が常に求められている。このため、これらの機器で使用される個々の部品の大きさおよび重量も重要となる可能性がある。上記のように、RF装置の電磁干渉シールドを与えるための従来の方策は、接地した金属カンを、シールドする個々のRF装置の上に配置することを含み、これは、大きさ、重量および設計のコストを増すため、多くの用途において望ましくないことがある。
Claims (21)
- 一体化された電磁干渉シールドを有するパッケージングされた半導体モジュールであって、前記パッケージングされた半導体モジュールは、
接地面を有する基板と、
前記基板の表面上に設けられた電子装置と、
前記電子装置の周りに配置され前記接地面に電気的に結合された複数のワイヤボンドばねと、
前記電子装置を覆い前記複数のワイヤボンドばねを少なくとも部分的に覆うモールド化合物と、
前記モールド化合物の上面上に配置され前記複数のワイヤボンドばねのうち少なくともいくつかに電気的に結合された導電層とを含み、
前記複数のワイヤボンドばね、前記導電層、および前記接地面はともに、前記一体化された電磁干渉シールドを含む、パッケージングされた半導体モジュール。 - 前記複数のワイヤボンドばねは金線から形成される、請求項1に記載のパッケージングされた半導体モジュール。
- 前記複数のワイヤボンドばねは銅線から形成される、請求項1に記載のパッケージングされた半導体モジュール。
- 前記導電層は銀が充填されたエポキシを含む、請求項1から3のいずれかに記載のパッケージングされた半導体モジュール。
- 前記電子装置はRF装置である、請求項1から4のいずれかに記載のパッケージングされた半導体モジュール。
- 前記複数のワイヤボンドばねは各々、前記導電層と前記ワイヤボンドばねとの間を接触させることにより前記導電層と前記ワイヤボンドばねとの間に電気的結合を与えるばね効果を提供するように成形されたワイヤの連続ループを含む、請求項1から5のいずれか1つに記載のパッケージングされた半導体モジュール。
- 前記複数のワイヤボンドばねは各々、ワイヤの連続ループを含み、前記ワイヤの連続ループは、
前記基板の表面上に配置されたボールボンドと、
屈曲ゾーンと、
頂部と、
前記屈曲ゾーンと前記頂部との間に延びる凸領域と、
傾斜した後端領域と、
前記頂部と前記傾斜した後端領域との間に延びる実質的に平坦な領域とを含み、
前記屈曲領域は前記凸領域と前記ボールボンドとの間にあり、
前記傾斜した後端領域の端部は前記基板に結合される、請求項1から5のいずれか1つに記載のパッケージングされた半導体モジュール。 - 前記基板の表面上に配置された第1および第2のメタライズされた接続点をさらに含み、
前記ボールボンドは前記第1のメタライズされた接続点に結合され、
前記傾斜した後端領域の端部は前記第2のメタライズされた接続点に結合される、請求項7に記載のパッケージングされた半導体モジュール。 - ワイヤの連続ループで形成されたワイヤボンドばねであって、
ボールボンドと、
屈曲ゾーンと、
頂部と、
前記屈曲ゾーンと前記頂部との間に延びる凸領域と、
傾斜した後端領域と、
前記頂部と前記傾斜した後端領域との間に延びる実質的に平坦な領域とを含み、
前記屈曲ゾーンは前記凸領域と前記ボールボンドとの間にある、ワイヤボンドばね。 - 前記頂部は前記屈曲ゾーンの実質的に垂直方向上方にある、請求項9に記載のワイヤボンドばね。
- 前記ワイヤボンドばねは金線から形成される、請求項9および10のうちいずれか1つに記載のワイヤボンドばね。
- 前記ワイヤボンドばねは銅線から形成される、請求項9および10のうちいずれか1つに記載のワイヤボンドばね。
- 一体化された電磁干渉シールドを有する半導体モジュールパッケージであって、前記半導体モジュールパッケージは、
基板と、
前記基板の第1の面の上に配置された第1および第2のメタライズされた接続点と、
前記第1のメタライズされた接続点と前記第2のメタライズされた接続点との間に延びる連続ワイヤを含むワイヤボンドばねとを含み、
第1のワイヤボンドばねは、
前記第1のメタライズされた接続点に電気的に接続されたボールボンドと、
屈曲ゾーンと、
頂部と、
前記屈曲ゾーンと前記頂部との間に延びる凸領域と、
前記頂部に近接する実質的に平坦な領域と、
前記実質的に平坦な領域と前記第2のメタライズされた接続点との間に延びる傾斜した後端領域とを含む、半導体モジュールパッケージ。 - 前記基板上に配置され前記第1および第2のメタライズされた接続点のうち少なくとも1つに電気的に結合された接地面をさらに含む、請求項14に記載の半導体モジュールパッケージ。
- 電子装置と、
前記ワイヤボンドばねと実質的に同一である複数のさらなるワイヤボンドばねとをさらに含み、
前記複数のワイヤボンドばねは、前記電子装置の周囲の周りにおいて前記基板の上に配置される、請求項15に記載の半導体モジュールパッケージ。 - 前記電子装置を覆い前記複数のワイヤボンドばねを少なくとも部分的に覆うモールド化合物と、
前記モールド化合物の表面上に配置され前記複数のワイヤボンドばねのうち少なくともいくつかに電気的に接続された導電層とをさらに含み、
前記接地面、前記導電層、および前記複数のワイヤボンドばねのうち少なくともいくつかは、ともに、一体化された電磁干渉シールドを形成する、請求項16に記載の半導体モジュールパッケージ。 - 一体化された電磁干渉シールドを有するモジュールの製造方法であって、
電子装置を基板に接続するステップと、
前記基板上にメタライゼーションを与えるステップと、
前記メタライゼーションに接続された複数のワイヤボンドばねを形成するステップと、
トランスファー成形プロセスを実施することにより前記電子装置をモールド化合物内に封じ込めかつ前記複数のワイヤボンドばねを前記モールド化合物で少なくとも部分的に覆うステップと、
導電層を前記モールド化合物の表面上に配置するステップとを含み、前記導電層は前記複数のワイヤボンドばねのうち少なくともいくつかに電気的に接続される、方法。 - 前記導電層を前記モールド化合物の表面上に配置する前に、前記モールド化合物の表面を除去して前記複数のワイヤボンドばねのうち少なくともいくつかの領域を露出させるステップをさらに含む、請求項18に記載の方法。
- 前記メタライゼーションを与えるステップは、接地面と、前記接地面に電気的に接続された少なくとも1つのワイヤボンド接触領域とを与えるステップを含む、請求項18に記載の方法。
- 前記複数のワイヤボンドばねを形成するステップは、
ワイヤボールを前記メタライゼーションの上に堆積させるステップと、
前記ワイヤボールからワイヤを引出して前記ワイヤボールに接続された第1の端部と、第2の端部とを有するワイヤループを形成するステップと、
前記第2の端部を前記メタライゼーションに接続するステップとを含む、請求項18に記載の方法。 - 前記導電層を前記モールド化合物の表面上に配置するステップは、銀が充填されたエポキシの層を前記モールド化合物の表面上に塗装するステップを含む、請求項18に記載の方法。
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- 2008-07-31 KR KR1020117002352A patent/KR101533866B1/ko active IP Right Grant
- 2008-07-31 EP EP08796999.4A patent/EP2308085A4/en not_active Withdrawn
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JP2015056427A (ja) * | 2013-09-10 | 2015-03-23 | 株式会社東芝 | 半導体装置および半導体装置の検査方法 |
TWI503931B (zh) * | 2013-09-10 | 2015-10-11 | Toshiba Kk | Semiconductor device and semiconductor device inspection method |
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Also Published As
Publication number | Publication date |
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JP5276169B2 (ja) | 2013-08-28 |
KR20110039448A (ko) | 2011-04-18 |
EP2308085A1 (en) | 2011-04-13 |
WO2010014103A1 (en) | 2010-02-04 |
EP2752872A1 (en) | 2014-07-09 |
EP2308085A4 (en) | 2013-06-05 |
CN102105981A (zh) | 2011-06-22 |
EP2752872B1 (en) | 2018-06-27 |
CN102105981B (zh) | 2013-11-13 |
HK1159311A1 (en) | 2012-07-27 |
KR101533866B1 (ko) | 2015-07-03 |
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