TWI375287B - Manufacturing process for quad flat non-leaded package - Google Patents

Manufacturing process for quad flat non-leaded package Download PDF

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Publication number
TWI375287B
TWI375287B TW098101393A TW98101393A TWI375287B TW I375287 B TWI375287 B TW I375287B TW 098101393 A TW098101393 A TW 098101393A TW 98101393 A TW98101393 A TW 98101393A TW I375287 B TWI375287 B TW I375287B
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TW
Taiwan
Prior art keywords
layer
patterned
conductive layer
solder mask
item
Prior art date
Application number
TW098101393A
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Chinese (zh)
Other versions
TW201027643A (en
Inventor
Geng Shin Shen
Chun Ying Lin
Original Assignee
Chipmos Technologies Inc
Chipmos Technologies Bermuda
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Application filed by Chipmos Technologies Inc, Chipmos Technologies Bermuda filed Critical Chipmos Technologies Inc
Priority to TW098101393A priority Critical patent/TWI375287B/en
Publication of TW201027643A publication Critical patent/TW201027643A/en
Application granted granted Critical
Publication of TWI375287B publication Critical patent/TWI375287B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a conductive layer having recesses and a patterned solder resist layer on the conductive layer are provided, wherein the patterned solder resist layer covers the recesses of the conductive layer. A part of the conductive layer uncovered by the patterned solder resist layer is removed so as to form a patterned conductive layer. Chips are bonded onto the patterned conductive layer such that the patterned solder resist layer and the chips are at the same side of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. At least one molding compound is formed and the molding compound and the patterned conductive layer are separated.

Description

1375287 ID-200809007 16667-0P7twf.doc/n 六、發明說明： * 【發明所屬之技術領域】 本發明是有關於一種晶片封襞製程，且特別是有關於 一種四方扁平無引腳（Quad Flat Non-leaded，QFN)封较 製程。 【先前技術】 隨著半導體工業的高度發展，電子及半導體裝置廣泛 ^ 地被應用於日常生活中’如娛樂、教育、交通運輸及家電 用品等方面。電子產品朝向設計複雜、尺寸小、重量輕及 人性化方面發展’以帶給使用者更多的方便。在封裝結構 中，導線架是常用的元件之一且應用於多種封裝產品。以 導線架的類型而5，四方扁平封裝（Quad Flat Package， QFP )可刀為I型接腳之四方扁平封裝（qUa(j f|at package with’Τ’lead，QFI)、J型接腳之四方扁平晶片封裝（卿d flat package with，，J” lead ’ QFJ )及四方扁平無引腳（咖以 • FlatN〇n_leaded’ QFN)封裝。四方爲平無引腳封裳之導線 架的引腳不超出封裝結構的邊緣，故其具有較小的體積。 此外’四方扁平無引腳封裝具有較短的訊號傳遞路徑及較 快之訊號傳遞速度’因此_直是低靠（bw pin e〇unt) 構裝型悲的主流之一。 一般而a，在四方扁平無引腳封裝的製造過程中，會 將多個晶片配置於導線架上，其中導線架包括多個相互連 接的引腳組’且各晶片被一引腳組所環繞。各晶片透過打 4 ID-200809007 16667-0P7twf.doc/n 晶^及、連接於—引腳組。接著，形成用以包覆導線架、 二二*^至少—封襄膠體。最後，透過單體化製程形 ^ f騎糾腳賴，財賴化製程包括衝壓製 私(啊一)或鋸切製程(sawingp—^ 【發明内容】 出具有本二：種方：:=裝製程’⑽ =ΪΓΓ圖案化導電層。在圖案化導電層上配 層，其中晶片及焊二二將;::導 焊Ϊ1 案化導電層、圖案化焊罩層、晶片 ^ 者，分剎封裝膠體及圖案化導電層。 在本發明之一實施例中， 曰 層及圖案鱗罩層的方法包括提;;^供具有凹槽的導電 焊罩層。圖案化焊罩層以形成-圖宰化 卜罩^其中圖案化焊罩層暴露出部分導電； 製程，上述^方騎糾腳封農 在本發明之一實施例中，上述之四方為平=丨腳封裝 ID-200809007 16667-0P7twf.doc/n 爲其中多個第—^及多個第二開W形成於圖案化 知罩層，其中第iD及第二開口暴露出部分圖案化 層。 、’ 在本發明之一實施例中，上述之焊線透過 性連接於圖案化導電層。 .$ ^ 在本發明之一實施例中，上述之晶片配置於 暴露出的圖案化導電層。 ' 一汗 製程2 實施例中’上述之四方扁平無引腳封裝 =私更包括形成位於晶片及圖案化導電層之間的一黏著 增0 層。在本發明之-實施例中’上述之黏著層為—Β階黏著 成於ΒΐίΓ=實施射，上述之Β _著層預先被形1375287 ID-200809007 16667-0P7twf.doc/n VI. Description of the Invention: * Technical Field of the Invention The present invention relates to a wafer sealing process, and more particularly to a quad flat no-pin (Quad Flat Non) -leaded, QFN) seals the process. [Prior Art] With the development of the semiconductor industry, electronic and semiconductor devices are widely used in daily life such as entertainment, education, transportation, and home appliances. The development of electronic products towards complex design, small size, light weight and humanity has brought more convenience to users. In the package structure, the lead frame is one of the commonly used components and is used in a variety of packaged products. In the type of lead frame, the Quad Flat Package (QFP) can be a quad flat package of the I-type pin (qUa(jf|at package with'Τ'lead, QFI), J-type pin Quartz flat package (J" lead 'QFJ) and quad flat no-lead (Payin• FlatN〇n_leaded' QFN) package. Quartet is the lead of the flat leadless lead frame It does not exceed the edge of the package structure, so it has a small volume. In addition, the 'quadruple flat leadless package has a shorter signal transmission path and faster signal transmission speed'. Therefore, it is low (bw pin e〇unt One of the mainstream of the sorrow type. Generally, in the manufacturing process of the quad flat no-lead package, a plurality of wafers are arranged on the lead frame, wherein the lead frame includes a plurality of interconnected pin sets' And each of the wafers is surrounded by a set of pins. Each of the wafers is connected to the -pin group by means of 4 ID-200809007 16667-0P7twf.doc/n, and then formed to cover the lead frame, the second and second* ^At least - seal the colloid. Finally, through the singulation process ^ f riding a slap in the foot, the financial reliance process includes stamping private (ah) or sawing process (sawingp-^ [invention content] out has two: kind::=installation process '(10) = ΪΓΓ patterned conductive Layer. The layer is patterned on the patterned conductive layer, wherein the wafer and the solder are used;:: the soldering layer 1 is patterned, the patterned solder mask layer, the wafer is soldered, and the patterned solder layer is patterned. In one embodiment of the present invention, a method for ruthenium layer and pattern scale layer includes: providing a conductive solder mask layer having a groove; patterning the solder mask layer to form a pattern soldering mask; wherein the pattern soldering The cover layer exposes a portion of the conductive portion; the process, the above-mentioned square-side riding and correcting foot sealing agriculture, in one embodiment of the present invention, the above-mentioned four squares are flat=foot-foot package ID-200809007 16667-0P7twf.doc/n And a plurality of second openings W are formed in the patterned cap layer, wherein the iD and the second openings expose a portion of the patterned layer. In one embodiment of the invention, the wire bond is transparently connected to Patterning the conductive layer. In one embodiment of the invention, the wafer is disposed on the exposed Patterning the conductive layer. 'One Sweat Process 2' In the embodiment, the above-described quad flat no-lead package = privately includes forming an adhesion-increasing layer between the wafer and the patterned conductive layer. In the present invention - an embodiment In the above-mentioned adhesive layer, the Β Γ 黏 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施

製程在施例中，上述之四方扁平⑻丨腳封I 層被形成圖案化焊罩層之前，黏著 所填i本ui貫關中，上述之__案化焊罩層 在本發明之1施例中，上述之 弟-表面及-第二表面，且凹槽位於第面有相對的- 成圖= 月ί:;施例中，上述之移除部分導電層以形 成，案化β層的方法包括從第二 以暴露出部分_化焊罩層。 導電層， 1375287 ID-200809007 16667-0P7twf.doc/nIn the embodiment, the above-mentioned tetragonal flat (8) crucible sealing layer I is formed by patterning the solder mask layer, and the above-mentioned method is used in the first embodiment of the present invention. Wherein, the above-mentioned brother-surface and - second surface, and the groove is located on the first side of the opposite - mapping = month ί:; in the embodiment, the above method of removing a part of the conductive layer to form a method of forming a beta layer Included from the second to expose a portion of the chemist layer. Conductive layer, 1375287 ID-200809007 16667-0P7twf.doc/n

階層在本發明之一實施例中，上述之圖案化焊罩層為一B 氧樹實施例+，上述之_化焊罩層為一環 在本發明之一實施例中，上述之四 製程，其中多個第一開口被形成於_』二 一開口暴露出部分圖案化導電層。 a ^ ^ 罩層ΐ本發明之—實施例中^述之晶片配置於圖案化谭 階層在本發明之—實施例中，上述之圖案化埠罩層為-Β 在本發明之一實施例中，上诚之τ f程更包括形成位於晶片及圖案化焊罩層之間^腳^ 層。在本發明之—實施例中，上述之黏著層為-㈣黏著 在本發明之一實施例t，上 製程上進行-掠化處理或封裝 基於上述，本發明的四方扁平盔 :出的:方爲平無引腳封裝具有用以結 層，以使得圖案化導電層可具有較小的厚产構強度叫罩 為讓本發明之上述特徵和優點^ 舉貧施例，並配合所附圖式作詳細說明如^以，下文特 7 1375287 DD-200809007 16667-0P7twf.doc/n 【實施方式】 圖1A至圖1H為本發明_實施例之四方爲平益引腳 封裝的製程剖視流程圖❶請參考圖1A，提供具有一第'一表 面112及一第二表面114的導電層110。接著，部分地移 除位於預定區域之導電層110，以在導電層110的第一表 面II2上形成多個凹;ft R。在本實施例中，是透過半姓刻 (half-etching)製程或衝壓（stamping)製程形成位於 一表面112的凹槽R。 、 請參考圖1B，在導電層11〇的第一表面112上形 具有多個第一開口 122及多個第二開口 124的—圖案^俨 罩層120，以使得形成於導電層11〇的第一表面丨^'之= 槽R被圖案化焊罩層120所填滿。形成於部分第—表面Η) 上的圖案化焊罩層120定義出多個第一焊墊118—較 佳實施例中’更可在導電層11〇上進行棕化（br〇^ oxidation)處理或黑化（black〇xidati〇n)處理以增加導 電層110之表面粗度，進而提升導電層11〇與圖案^焊 層120之間的結合力。 / 在一可選擇的實施例中，相較於圖之在導電層no 的第一表面112上形成具有多個第一開口 122及多個S第二 開口 124的一圖案化焊罩層12〇，亦可在導電層“ο的第 一表面112上形成具有多個第一開口 122且不具有多個第 二開口 124的一圖案化焊罩層（未緣示）。 在本貫施例中，圖案化焊罩層120可為—B階膜 (Β-stagedflhn)(亦為焊罩膜），且第一開口 122^圖 8 1375287 ID-200809007 16667-0P7twf.doc/n 案化焊罩層120被貼附於導電層no之前或之後被形成。 在一可選擇的實施例中，可將一液態悍罩塗層塗佈在導電 層110的第一表面112上，並將其固化及圖案化以形成圖 案化:fcf·罩層120，且液態焊罩塗層可為一 b階液態焊罩塗 層。在一可選擇的實施例中，更可透過在導電層110的第 一表面112預成型（pre_m〇iding) 一環氧樹脂成型化合物 (epoxy molding compound) ’並對其進行脫模後固化（卩⑽ mold curing)製程以形成圖案化焊罩層12〇。In one embodiment of the present invention, the patterned solder mask layer is a B oxygen tree embodiment +, and the above-mentioned chemical solder mask layer is a ring. In one embodiment of the present invention, the above four processes, wherein A plurality of first openings are formed in the "one" opening to expose a portion of the patterned conductive layer. a ^ ^ ΐ ΐ ΐ ΐ 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片The process of the cheng τ f includes forming a layer between the wafer and the patterned solder mask layer. In the embodiment of the present invention, the above-mentioned adhesive layer is - (4) adhered to an embodiment of the present invention t, the upper process is carried out - grazing treatment or encapsulation based on the above, the quad flat helmet of the present invention: out: square is flat The leadless package has a layer for the layering so that the patterned conductive layer can have a small thickness of the resultant strength to make the above features and advantages of the present invention a poor example, and the details are combined with the drawings. The description is as follows, the following is a special flow chart of the process of the present invention. FIG. 1A to FIG. 1H are the flow chart of the process of the square of the invention. Referring to FIG. 1A, a conductive layer 110 having a 'first surface 112' and a second surface 114 is provided. Next, the conductive layer 110 located in the predetermined region is partially removed to form a plurality of recesses on the first surface II2 of the conductive layer 110; ft R. In the present embodiment, the groove R on a surface 112 is formed by a half-etching process or a stamping process. Referring to FIG. 1B, a plurality of first openings 122 and a plurality of second openings 124 are formed on the first surface 112 of the conductive layer 11A so as to be formed on the conductive layer 11 The first surface =^' = slot R is filled with the patterned solder mask layer 120. The patterned solder mask layer 120 formed on a portion of the surface-surface 定义 defines a plurality of first pads 118 - in the preferred embodiment - can be browned on the conductive layer 11 Or blackening (black) treatment to increase the surface roughness of the conductive layer 110, thereby improving the bonding force between the conductive layer 11 and the pattern solder layer 120. In an alternative embodiment, a patterned solder mask layer 12 having a plurality of first openings 122 and a plurality of second openings 124 is formed on the first surface 112 of the conductive layer no as compared to the figure. A patterned solder mask layer (not shown) having a plurality of first openings 122 and no plurality of second openings 124 may also be formed on the first surface 112 of the conductive layer ο. In the present embodiment The patterned solder mask layer 120 can be a -B-staged film (also a solder mask film), and the first opening 122 ^ Figure 8 1375287 ID-200809007 16667-0P7twf.doc / n case welding mask layer 120 is formed before or after being attached to the conductive layer no. In an alternative embodiment, a liquid enamel coating can be applied to the first surface 112 of the conductive layer 110 and cured and patterned. The patterning: fcf. cap layer 120, and the liquid solder mask coating can be a b-stage liquid solder mask coating. In an alternative embodiment, the first surface 112 of the conductive layer 110 is more permeable. Pre-formed (epoxy molding compound) and cured after demolding (卩(10) m The process is to form a patterned solder mask layer 12〇.

，外，在一較佳實施例中，可透過電鍍（plating)製 程在第一焊墊118上形成一電鍍導電層（未繪示）。電鑛 ，電層可為鎳金疊層或其它適用的金屬層。值得注意的 疋，可在圖案化焊罩層12〇形成於導電層n〇之前或之 形成電錢導電層。 —請參考圖1C’透過蝕刻對導電層11〇的第二表面ιΐ4 以形成—圖案化導電層liG，，其中圖案化導電層In addition, in a preferred embodiment, a plating conductive layer (not shown) is formed on the first pad 118 by a plating process. The electric ore layer may be a nickel gold laminate or other suitable metal layer. It is worth noting that the patterned conductive mask layer 12 is formed before or during the formation of the conductive layer n〇. - Referring to FIG. 1C', the second surface ι 4 of the conductive layer 11 is etched to form a patterned conductive layer liG, wherein the conductive layer is patterned

=將=導電層no移除的方法例如是=面 etching)製程。 110, 著二5 :將多個晶“3〇黏著於圖案化導電) 相對主動表面m的-H413^有—主動表面132 多個第H m A 4及配置於絲表面132 0 化導電芦nn, 。D晶片130透過位於晶片130及圖！ 曰之間的—黏著層H0而黏著於圖案化導電^ 1375287 ID-200809007 16667-0P7twf.doc/n 110’。在一可選擇的實施例中，晶片13〇可不透過黏著層 140而黏著於圖案化焊罩層120上，其中圖案化焊罩層12〇 為形成於引腳ll〇b及晶片座110a上的一 B階焊單層（此 時無第一開口 124)，且圖案化焊罩層120在配置晶片130 之如未被完全固化。 在本實施例中，可透過打線（wire bonding)製程形成 知線150，以使付各焊線150.電性連接於一第一焊塾118 及一第一焊塾* 之間。焊線15〇例却是金線。 在本實施中，黏著層140例如是一 b階黏著層 (B-staged adhesive layer )。B 階黏著層 14〇 可為 ABLESTIJC 的 8008、8008HT、6200、6201、6202C ^ HITACHI Chemical CO·，Ltd.提供的 SA-200-6、 SA-200-10。在本發明之一實施例中，3階黏著層i4〇是被 形成於一晶圓的背面。在切割晶圓之後可得到具有位於背 面134之黏著層14〇的多個晶片13〇。因此，B階黏著層 H0適於大量生產。此外’可透過旋塗、印刷或其它適用 的製程以形成B階黏著層刚。黏著層14G係預先被形成 於晶片130的背面134。特別的是，可先提供具有陣列地 排列之夕個晶片130的-晶圓。接著，在晶片13〇的背面 134形成一二階黏著層，並透過加熱（heating)或紫外線 照射（mediation)將其部分固化，以形❹階黏著層 14^。此外’亦可在晶片13〇被貼附於圖案化導電層⑽， 之刚’在目案化導電層110,上形成B階黏著層14〇。 在本實施财，3階黏著層140是在晶片13G被貼附 10 1375287 ID-200809007 16667-0P7twf.doc/n 於圖案化導電層110’之後完全固化，或在之後透過後固化 (post curing)處理而完全固化’或在被封裝膠體160包 覆後完全固化。 請參考圖1E，形成包覆圖案化導電層no，、圖案化 焊罩層120、晶片130及焊線150的至少一封裝膠體160。 封裝膠體160的材質例如是環氧樹脂（ep〇xyresin)。 請參考圖1F，相較於圖1E之形成包覆圖案化導電層 no’、圖案化焊罩層12〇、晶片13()及焊線15〇的一封裝 膠體160 ’亦可形成包覆圖案化導電層11〇,、目案化焊罩 層12〇、晶片130及焊線150的多個封裝膠體16〇,。 、，印參考圖ig及圖1Ή，透過單體化製程形成多個四方 扁平無引腳封裝10〇 (繪示於圖1G)或多個四方扁平益引 ，封裝1〇〇，（綠示於1Η)，其中單體化製程包括衝壓 P:h)製程或鑛切製程。如圖1(}所繪示，本發明的四 圖宰化ίΪ:封裝1〇0主要包括一圖案化導電層110’、-體160。干圖二=7晶片13〇、多條焊線150及一封裝膠 案化導電層110’具有一第一表面112，其中圖 多個引腳^ 晶片座11〇a及環繞晶片座腕的 的第-矣且圖案化焊罩層120從圖案化導電層110, 焊罩層19η且t 置弟一表12，其中圖案化 宰化導雷思路出部分第一表®112°晶片130配置於圖 圖案化導二So，：中圖案化焊罩層m及晶片130位於 曰1〇的同一側。焊線15〇電性連接於晶片130 11 ID-200809007 16667-0P7twf.doc/n 及圖案化焊罩層120暴露出的圖案化 體⑽包覆圖案化導電層㈣，同^ 曰1〇封裝膠 ⑽及烊線15G。 』G、圖案化焊罩層⑽、晶片 ，所述，相較於傳統之四方扁平無 本發明之时料無_城抛製 .=’其具有用以強化結構強度的焊罩層二= ^小的整體厚度及較低的製造成本，以：能 (throughput)獲得提升。 使產月 本發揭露如上，然其並非用以限定 2：何所屬技術領域中具有通常知識者，在不脫離 和範_ ’當可作些許之更動與潤ί故本 X之保羞犯圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1Α至圖1W劣I人 封裝的製程剖視流程^本务明一實施例之四方扁平無引腳 【主要元件符號說明】 100、100 ’四方扁平無引腳封裝 110 :導電層 ：圖案化導電層 110a ·晶片座 ll〇b :引腳 12 1375287 ID-200809007 16667-0P7twf.doc/n 112 :第一表面 114 :第二表面 118 :第一焊墊 120 :圖案化焊罩層 122 :第一開口 124 :第二開口 130 :晶片 132 :主動表面 134 :背面 136 :第二焊墊 140 :黏著層 150 :焊線 160、160’ ：封裝膠體 R :凹槽= The method of removing the conductive layer no is, for example, a = surface etching process. 110, holding two 5: bonding a plurality of crystals "3〇 to the patterned conductive" -H413 with respect to the active surface m - active surface 132, a plurality of H m A 4 and disposed on the surface of the wire 132 The D-wafer 130 is adhered to the patterned conductive ^ 1375287 ID-200809007 16667-0P7twf.doc/n 110' through the adhesive layer H0 between the wafer 130 and the image 曰. In an alternative embodiment, The wafer 13 can be adhered to the patterned solder mask layer 120 without the adhesive layer 140. The patterned solder mask layer 12 is a B-stage solder monolayer formed on the leads 11b and the wafer holder 110a. There is no first opening 124), and the patterned solder mask layer 120 is not fully cured in the configuration wafer 130. In this embodiment, the wire 150 can be formed through a wire bonding process to make the bonding wires 150. Electrically connected between a first pad 118 and a first pad*. The wire 15 is a gold wire. In the present embodiment, the adhesive layer 140 is, for example, a b-stage adhesive layer (B- Staged adhesive layer ). B-stage adhesive layer 14〇 can be ABLESTIJC's 8008, 8008HT, 6200, 6201, 6202C ^ HITACHI Chemical CO· SA-200-6, SA-200-10 provided by the Ltd. In one embodiment of the present invention, the third-order adhesive layer i4 is formed on the back side of a wafer. The plurality of wafers 13 are located on the adhesive layer 14 of the back surface 134. Therefore, the B-stage adhesive layer H0 is suitable for mass production. In addition, it can be formed by spin coating, printing or other suitable processes to form a B-stage adhesive layer. Adhesive layer The 14G system is formed in advance on the back surface 134 of the wafer 130. In particular, a wafer having an array of wafers 130 arranged in an array may be provided first. Then, a second-order adhesive layer is formed on the back surface 134 of the wafer 13A, and It is partially cured by heating or ultraviolet irradiation to form a layer of adhesive layer 14^. In addition, it can also be attached to the patterned conductive layer (10) on the wafer 13〇. The conductive layer 110 is formed with a B-stage adhesive layer 14A. In the present embodiment, the third-order adhesive layer 140 is attached to the patterned conductive layer 110' after the wafer 13G is attached with 10 1375287 ID-200809007 16667-0P7twf.doc/n. Completely cured, or completely post-treated by post curing Of 'or 160 after being completely cured encapsulant cladding. Refer to 1E, the patterned conductive layer forming coating no ,, patterned solder mask layer 120, the wafer 130 and at least one of bonding wires encapsulated colloidal 150 160. The material of the encapsulant 160 is, for example, epoxy resin (ep〇xyresin). Referring to FIG. 1F, a package pattern can also be formed by forming the encapsulation conductive layer no', the patterned solder mask layer 12, the wafer 13 (), and the bonding wire 160' of the bonding wire 15'. The conductive layer 11A, the meshed solder mask layer 12, the wafer 130, and the plurality of encapsulants 16 of the bonding wires 150 are formed. Referring to FIG. 1 and FIG. 1 , a plurality of quad flat no-lead packages 10 〇 (shown in FIG. 1G ) or a plurality of square flat leads are formed through a singulation process, and the package is 1 〇〇, (green is shown in FIG. 1Η), wherein the singulation process includes stamping P:h) process or mineral cutting process. As shown in FIG. 1 (}, the four figures of the present invention: the package 1 〇 0 mainly includes a patterned conductive layer 110 ′, the body 160. The dry picture 2 = 7 wafer 13 〇, a plurality of bonding wires 150 And a packaged patterned conductive layer 110' having a first surface 112, wherein the plurality of pins ^ wafer holder 11A and the first and second patterned patterned solder mask layer 120 surrounding the wafer holder are patterned from conductive The layer 110, the solder mask layer 19n and t are placed in a table 12, wherein the patterned slaughtering guides the portion of the first table® 112° wafer 130 is disposed in the patterned patterned second So,: the patterned solder mask layer m And the wafer 130 is located on the same side of the 曰1〇. The bonding wire 15 is electrically connected to the wafer 130 11 ID-200809007 16667-0P7twf.doc/n and the patterned body (120) is patterned by the patterned solder mask layer 120. Conductive layer (4), same as ^ 曰 1 〇 encapsulation glue (10) and 烊 line 15G. 』 G, patterned solder mask layer (10), wafer, said, compared to the traditional square flat without the present invention, no _ city throwing .='It has a weld cap layer to strengthen the structural strength = 2 small overall thickness and low manufacturing cost, to: increase the throughput. The present disclosure is as above, but it is not intended to be limited to 2: what is the general knowledge in the technical field, and does not deviate from the norm _ 'when it can be changed and run a little. The scope of the patent application is subject to the definition of the patent application. [Simplified schematic diagram] Figure 1Α to Figure 1W Process diagram of the inferior I package process ^The first embodiment of the quad flat no-lead [main component symbol description] 100 , 100 'quad flat no-lead package 110 : conductive layer: patterned conductive layer 110a · wafer holder ll 〇 b : pin 12 1375287 ID-200809007 16667-0P7twf.doc / n 112 : first surface 114 : second surface 118: first pad 120: patterned solder mask layer 122: first opening 124: second opening 130: wafer 132: active surface 134: back surface 136: second solder pad 140: adhesive layer 150: bonding wires 160, 160 ' : Package colloid R : groove

Claims (1)

U丨J厶Q ! U丨J厶Q ! ID-200809007 16667-0P7twf.d〇c/n 穿制i如盆申H專利範圍第1項所述之四方扁平無引腳封 置Γ!個第一開口及多個第二開口被形成於該圖 =導;;該些第，及該些第二開口暴露出部 穿製i如盆申^專利範圍第4項所述之四方扁平無引腳封 t二電過該些第-開口電性連接於該圖 事制J：如專利範圍第4項所述之四方扁平無引腳封 電ί晶片配置於該些第二開口暴露出的該圖 ^^鄕圍第丨項所狀四方扁平無引腳封 :二:著:包括形成位於該些晶片及該圖案化導電層之間 带制S 概财7項㈣之四^扁平無引腳封 裝衣紅，其中該黏著層為一B階黏著層。 裝4:!=:範圍第8項所述之四方扁平無引腳封 黏者層預先被形成於該晶片的一背面。 裝製r·並利範圍第8項所述之四方扁平無引腳封 該BP㈣著#=^片被貼附於該圖案化焊罩層之前， 尸白勒者層被形成於該圖案化焊罩層上。 袭製公，圍第1項所述之四方扁平無引腳封 八Μ二凹槽被該圖案化焊罩層所填滿。 •如申請專利範圍第丨 展製程’其t該導電層具有相對的—第：=丨= 15 ^-200809007 16667-0P7twf.doc/i ’且該些凹槽位於該第一表面 面 13.如中請專利範圍第12項所述之四方扁 除部分該導電層以形成該圖 八法包括4^第二表面侧部分該導電層 +曰 刀該圖案化焊罩層。 暴路出部 裝製i4'如其扁平無一 从如ΐ靖專利rL，為氧成型化合物。 裝製程，計多個第!項所述之四方扁平無引腳封 中該此第—π I㊉扣麵成於該圖案化焊罩層，其 二弟m口暴路出部分該圖案化導電層。 封裝i7程如Π=Γ16項所述之四方扁平無引腳 /、中5玄二曰曰片配置於該圖案化焊罩層上。 封裝势程如圍第17項所述之四方^平無引腳 H其中該圖案化焊罩層為-B階層。 ^⑵^所述之四方扁平無引腳封 的-黏著層。 於該些⑼及該_化谭罩層之間 封裳f程如圍第19項所述之四方扁平無引腳 了裒…其中該黏著層為一 β_著層。 裝專利範園第1項所述之四方扁平益引腳封 ’更包括在該導電層上進行—稼化處理或:黑化處 16U丨J厶Q ! U丨J厶Q ! ID-200809007 16667-0P7twf.d〇c/n The uniform square-shaped leadless package described in item 1 of the patent application scope An opening and a plurality of second openings are formed in the figure; the first and the second openings are exposed, and the quad flat no-pin as described in the fourth aspect of the patent application The second opening is electrically connected to the drawing system: the quad flat no-lead sealing device described in item 4 of the patent scope is disposed on the second opening. ^^ 四 丨 丨 丨 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四The clothing is red, wherein the adhesive layer is a B-stage adhesive layer. Mount 4:!=: The quad flat no-lead sealer layer described in item 8 of the range is previously formed on a back side of the wafer. The quad flat no-lead seal described in item 8 of the r<>> range is applied to the patterned solder mask layer before the BP(4)##^^ sheet is attached to the patterned solder mask layer, and the corpse layer is formed on the patterned solder On the cover. The quad flat no-lead seal described in item 1 is filled with the patterned solder mask layer. • If the patent application scope is the third development process, the conductive layer has a relative value of -=:======================================================================================= The four-party flat part of the patent scope is divided into a portion of the conductive layer to form the second embodiment, and the conductive layer + the trowel of the patterned solder mask layer. The violent road out of the assembly i4' as it is flat, from the patent, such as the appease patent rL, is an oxygen molding compound. The mounting process, in the quad flat no-lead seal described in the above item, wherein the first π I ten-face is formed in the patterned solder mask layer, and the second brother has a portion of the patterned conductive layer . The four-sided flat no-pin/, medium-bright two-pronged piece described in the package i7, such as Π=Γ16, is disposed on the patterned solder mask layer. The package potential is as described in item 17 of the square, no lead H, wherein the patterned solder mask layer is -B level. ^(2)^ The square flat unshielded-adhesive layer described. Between the (9) and the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The quad flat-shaped pin seals described in Item 1 of the Patent Fan Park are further included on the conductive layer for processing or blackening.
TW098101393A 2009-01-15 2009-01-15 Manufacturing process for quad flat non-leaded package TWI375287B (en)

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TWI556359B (en) * 2015-03-31 2016-11-01 南茂科技股份有限公司 Quad flat non-leaded package structure and leadframe thereof
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