WO2013037188A1 - Pre-encapsulated islandless lead frame structures and manufacturing method - Google Patents

Pre-encapsulated islandless lead frame structures and manufacturing method Download PDF

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Publication number
WO2013037188A1
WO2013037188A1 PCT/CN2012/001162 CN2012001162W WO2013037188A1 WO 2013037188 A1 WO2013037188 A1 WO 2013037188A1 CN 2012001162 W CN2012001162 W CN 2012001162W WO 2013037188 A1 WO2013037188 A1 WO 2013037188A1
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WO
WIPO (PCT)
Prior art keywords
leads
metal substrate
top surface
back surface
photoresist film
Prior art date
Application number
PCT/CN2012/001162
Other languages
French (fr)
Inventor
Xinchao Wang
Zhizhong Liang
Original Assignee
Jiangsu Changjiang Electronics Technology Co. Ltd
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Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co. Ltd filed Critical Jiangsu Changjiang Electronics Technology Co. Ltd
Publication of WO2013037188A1 publication Critical patent/WO2013037188A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

Definitions

  • the present invention generally relates to the field of semiconductor assembly or packaging and, more particularly, to lead frame structures and related manufacturing processes.
  • a conventional Quad Flat No-Lead (QFN) lead frame it is generally required that the size of the chip to be mounted is less than the size of the island or die pad to avoid mounting glue (electrically conductive or non-conductive) contaminating the leads of the lead frame.
  • the size of the area surrounded the leads may still be limited to fit large-size chip without mounting glue contamination.
  • Fig. 1 shows a conventional islandless QFN lead frame having leads 21 and molding compound 22.
  • Fig. 2 shows chip 23 is mounted on the lead frame using mounting glue 24 and sealed by molding compound 22. As shown in Fig.
  • the chip 23 because the size of the chip 23 is larger than the size of the area surrounded by leads 21 , the chip 23 also touches the inner leads of the leads 22 and mounting glue 24 also touches or contaminates the inner leads of the leads 22. Therefore, to avoid such contamination, the size of the chip to be mounted on the islandless lead frame is limited, and the chip scale may be low.
  • One aspect of the present disclosure includes a method for manufacturing an islandless lead frame structure in a semiconductor packaging process.
  • the method includes providing a metal substrate having a top surface and a back surface, forming a first photoresist film on the top surface of the metal substrate, and forming a top surface etching pattern in the first photoresist film using photolithography.
  • the method also includes forming a second photoresist film on the back surface of the metal substrate, forming a back surface etching pattern in the second photoresist film using photolithography, and performing an etching process on the top surface and the back surface of the metal substrate using the top surface etching pattern and the back surface etching pattern as the respective masks to form a plurality of leads.
  • Outer leads of the plurality of leads on the back surface extend towards an area surrounded by the outer leads such that a length of the outer leads is larger than a length of inner leads of the plurality of leads on the top surface.
  • the method includes removing the first photoresist film and the second photoresist film, and encapsulating the etched metal substrate using a molding compound exposing top surfaces and back surfaces of the plurality leads.
  • Another aspect of the present disclosure includes an islandless lead frame structure for semiconductor packaging.
  • the islandless lead frame includes a plurality of leads formed based on a metal substrate by an etching process, and a molding compound used to encapsulate the etched metal substrate with the plurality of leads.
  • the etching process is performed by: providing the metal substrate; forming a first photoresist film on a top surface of the metal substrate; forming a top surface etching pattern in the first photoresist film using photolithography; forming a second photoresist film on a back surface of the metal substrate; forming a back surface etching pattern in the second photoresist film using photolithography; performing an etching process on the top surface and the back surface of the metal substrate using the top surface etching pattern and the back surface etching pattern as the respective masks to form a plurality of leads, where outer leads of the plurality of leads on the back surface extend towards an area surrounded by the outer leads such that a length of the outer leads is larger than a length of inner leads of the plurality of leads on the top surface; and removing the first photoresist film and the second photoresist film.
  • Figure 1 shows a conventional islandless QFN lead frame
  • Figure 2 shows a large-size chip mounted on the conventional islandless QFN lead frame with mounting glue contamination
  • Figure 3 illustrates an exemplary pre-encapsulated islandless lead frame structure consistent with the disclosed embodiments
  • Figure 4 illustrates a large-size chip mounted on the pre-encapsulated islandless lead frame structure
  • Figure 5 shows an exemplary packaging process based on the pre-encapsulated islandless lead frame structure consistent with the disclosed embodiments.
  • Fig. 3 illustrates an exemplary pre-encapsulated islandless lead frame structure 100 consistent with the disclosed embodiments.
  • islandless lead frame 100 includes a plurality of leads 1 and molding compound 2 filled in etched areas and the areas between the leads of the plurality of leads 1.
  • Islandless lead frame 100 does not contain any island or die pad. Other components may also be included and certain components may be omitted.
  • islandless lead frame 100 may also include a first metal layer (not shown) on the top surfaces of the plurality of leads 1 and a second metal layer (not shown) on the back surfaces of the plurality of leads 1.
  • the plurality of leads 1 may be made from a metal substrate (unnumbered).
  • the molding compound 2 is filled up to the top surface and the back surface of the metal substrate such that both the top surface and the back surface of the metal substrate are flat planes.
  • Islandless lead frame structure 100 may be formed as a part of a packaging process.
  • Fig. 5 illustrates an exemplary packaging process 200 consistent with the disclosed embodiments.
  • a metal substrate is provided (202).
  • the metal substrate may have a top surface and a back surface, and may also have a desired thickness.
  • the metal substrate may be made of any appropriate metal materials, such as copper, aluminum, iron, copper alloy, stainless steel, or nickel-iron alloy. The particular metal used for metal substrate may be determined based on the functionalities and characteristics of the chips to be packaged.
  • adhesive films may be attached to the top surface and the back surface of the metal substrate (204). More particularly, a first photoresist film may be attached to the top surface of the metal substrate, and a second photoresist film may be attached to the back surface of the metal substrate.
  • the first photoresist film and the second photoresist film may be attached using certain film equipment to protect the substrate from a later etching process. Further, the first photoresist film and second photoresist film can be used in a photolithographic process, and any of the first photoresist film and second photoresist film may be a dry photoresist film or a wet photoresist film. Other types of film may also be used.
  • etching patterns may be formed based on the first photoresist film and second photoresist film (206). More specifically, a top surface etching pattern may be formed using the first photoresist film and a back surface etching pattern may be formed using the second photoresist film via photolithography. That is, the etching patterns may be formed using a photolithographic process. A top surface etching mask is used to expose the first photoresist film, which is followed by development, and certain parts of the first photoresist film are removed to form the top surface etching pattern to uncover the areas on the metal substrate that need to be etched.
  • a back surface etching mask is used to expose the second photoresist film, which is' followed by development, and certain parts of the second photoresist film are removed to form the back surface etching pattern to uncover the areas on the metal substrate that need to be etched.
  • the top surface etching pattern corresponds to inner leads of the plurality of leads 1, and the back surface etching pattern corresponds to outer leads of the plurality of leads 1.
  • the top surface etching pattern is designed in a way that the size of the area surrounded by the inner leads of the plurality of leads 1 is substantially large to fit a large chip. That is, the distance between two opposite inner leads is within a same range of the size of the large chip such that a large chip can be mounted on the lead frame without touching the inner leads of the plurality of leads 1.
  • the back surface etching pattern is designed in a way that the outer leads of the plurality of leads 1 extends towards to the center of the area surrounded by the plurality of leads 1 such that the length of the outer leads is larger than the length of the inner leads of the plurality of leads 1.
  • an etching process may be performed on the top surface and back surface of the metal substrate (208). That is, the etching process is performed on the exposed areas on the top surface and back surface of the metal substrate, which are exposed by removing parts of the first and second photoresist films.
  • the top surface of metal substrate is etched using the top surface etching pattern as a mask, and the back surface of metal substrate is etched using the back surface etching pattern as a mask.
  • the etching process may be a half etching and may be performed on both the top surface and the back surface simultaneously.
  • the plurality of leads 1 and certain etched areas are formed on the metal substrate.
  • the plurality of leads 1 have smaller length on top surface of the metal substrate and larger length on back surface of the metal substrate.
  • Other types of etching such as a full etching, may also be used.
  • the remaining adhesive films on the surfaces of metal substrate are removed (210).
  • the films may be removed by mechanical means or chemical means.
  • the etched metal substrate is encapsulated in a molding process or a pre- encapsulating process (212). That is, molding compound 2 is filled into the etched metal substrate using a mold.
  • pre-encapsulation refers to the encapsulation or molding process that is performed after the etching process and before the subsequent plating process.
  • the pre-encapsulated islandless lead frame has a flat top surface comprising the exposed top surfaces of the plurality of leads 1 and the molding compound 2, and a flat back surface comprising the exposed back surfaces of the plurality of leads 1 and the molding compound 2.
  • a plating process may be performed on the pre-encapsulated lead frame to form the first metal layer and the second metal layer.
  • the plating process may include any appropriate type of electrical or chemical plating process, such as a multi-layer electrical plating process.
  • the plating material may include gold, nickel-gold, nickel-palladium-gold, or silver. Other materials may also be used.
  • the first metal layer may be formed on the top surfaces of the plurality of leads 1 to provide inner leads for the plurality of leads 1.
  • the second metal layer may be formed on back surfaces of the plurality of leads 1 to provide outer leads for leads 1.
  • the first metal layer and the second metal layer may be formed on the top surface and the back surface of the metal substrate, respectively, before the etching process.
  • the pre-encapsulated lead frame 100 may then be used in other subsequent processes in the packaging process 200 (214).
  • a die 3 may be attached on the pre-encapsulated lead frame 100 using conductive or non-conductive adhesive material 4 in a die attaching process.
  • the size of die 3 may be larger than the size of the area surrounded by the outer leads of the plurality of leads 1, the adhesive material 4 does not contaminate the inner leads of the plurality of leads 1. That is, even when a substantial area of the die 3 is outside the area surrounded by the outer leads, the die 3 does not touch or is above any of the inner leads of the plurality of leads 1.
  • top surface of die 3 and the top surface of the inner leads of the plurality of leads 1 are connected with metal wires in a wire bonding process.
  • the inner leads, the die 3, and the metal wires are then encapsulated using encapsulation material 2.
  • encapsulation material 2 For example, molding equipment may be used to seal or encapsulate the packaging structure by the molding compound 2.
  • Post-molding curing may also be performed such that the molding compound 2 or other plastic encapsulation materials may also be cured.
  • the disclosed lead frame structures and manufacturing methods may be applied in a variety of semiconductor packaging applications for different carriers with different substrates and filling materials.
  • the disclosed structures and methods may be used to package plastic leaded chip carrier (PLCC), plastic quad flat pack (PQFP), ball grid array (BGA), system in package (SiP) or 3D ICs, and multi-chip module, etc.
  • an islandless lead frame structure can be created using etching and pre-encapsulation.
  • Such lead frame structures and methods can be suitable for mounting large-size chips.
  • the outer leads extends to the area surrounded by the outer leads of the plurality of leads such that the length of the outer leads is bigger than the length of the inner leads. That is, the plurality of leads have smaller length on top surface of the metal substrate and larger length on back surface of the metal substrate.
  • Such small-top-size and large-bottom-size lead structure can fit larger chip without causing mounting glue contamination and the chip scale can also be increased.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A method is provided for manufacturing an islandless lead frame structure (100) in a semiconductor packaging process. The method includes providing a metal substrate having a top surface and a back surface, forming a first photoresist film on the top surface of the metal substrate, and forming a top surface etching pattern in the first photoresist film using photolithography. The method also includes forming a plurality of leads (1). Outer leads of the plurality of leads (1) on the back surface extend toward an area surrounded by the outer leads such that a length of the outer leads is larger than a length of inner leads of the plurality of leads (1) on the top surface. Further, the method includes removing the first photoresist film and the second photoresist film, and encapsulating the etched metal substrate using a molding compound (2) exposing top surfaces and back surfaces of the plurality leads (1).

Description

PRE-ENCAPSULATED ISLANDLESS LEAD FRAME STRUCTURES AND
MANUFACTURING METHOD
CROSS-REFERENCES TO RELATED APPLICATIONS
[0001] This application claims the priority of Chinese patent application
no.201110268348.5. filed on 13/09/2011. the entire contents of which are incorporated herein by reference.
FIELD OF THE INVENTION
[0002] The present invention generally relates to the field of semiconductor assembly or packaging and, more particularly, to lead frame structures and related manufacturing processes.
BACKGROUND
[0003] In a conventional Quad Flat No-Lead (QFN) lead frame, it is generally required that the size of the chip to be mounted is less than the size of the island or die pad to avoid mounting glue (electrically conductive or non-conductive) contaminating the leads of the lead frame. For those conventional islandless QFN lead frames, the size of the area surrounded the leads may still be limited to fit large-size chip without mounting glue contamination. For example, Fig. 1 shows a conventional islandless QFN lead frame having leads 21 and molding compound 22. Fig. 2 shows chip 23 is mounted on the lead frame using mounting glue 24 and sealed by molding compound 22. As shown in Fig. 2, because the size of the chip 23 is larger than the size of the area surrounded by leads 21 , the chip 23 also touches the inner leads of the leads 22 and mounting glue 24 also touches or contaminates the inner leads of the leads 22. Therefore, to avoid such contamination, the size of the chip to be mounted on the islandless lead frame is limited, and the chip scale may be low.
[0004] The disclosed methods and systems are directed to solve one or more problems set forth above and other problems. BRIEF SUMMARY OF THE DISCLOSURE
[0005] One aspect of the present disclosure includes a method for manufacturing an islandless lead frame structure in a semiconductor packaging process. The method includes providing a metal substrate having a top surface and a back surface, forming a first photoresist film on the top surface of the metal substrate, and forming a top surface etching pattern in the first photoresist film using photolithography. The method also includes forming a second photoresist film on the back surface of the metal substrate, forming a back surface etching pattern in the second photoresist film using photolithography, and performing an etching process on the top surface and the back surface of the metal substrate using the top surface etching pattern and the back surface etching pattern as the respective masks to form a plurality of leads. Outer leads of the plurality of leads on the back surface extend towards an area surrounded by the outer leads such that a length of the outer leads is larger than a length of inner leads of the plurality of leads on the top surface. Further, the method includes removing the first photoresist film and the second photoresist film, and encapsulating the etched metal substrate using a molding compound exposing top surfaces and back surfaces of the plurality leads. [0006] Another aspect of the present disclosure includes an islandless lead frame structure for semiconductor packaging. The islandless lead frame includes a plurality of leads formed based on a metal substrate by an etching process, and a molding compound used to encapsulate the etched metal substrate with the plurality of leads. The etching process is performed by: providing the metal substrate; forming a first photoresist film on a top surface of the metal substrate; forming a top surface etching pattern in the first photoresist film using photolithography; forming a second photoresist film on a back surface of the metal substrate; forming a back surface etching pattern in the second photoresist film using photolithography; performing an etching process on the top surface and the back surface of the metal substrate using the top surface etching pattern and the back surface etching pattern as the respective masks to form a plurality of leads, where outer leads of the plurality of leads on the back surface extend towards an area surrounded by the outer leads such that a length of the outer leads is larger than a length of inner leads of the plurality of leads on the top surface; and removing the first photoresist film and the second photoresist film.
[0007] Other aspects of the present disclosure can be understood by those skilled in the art in light of the description, the claims, and the drawings of the present disclosure.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figure 1 shows a conventional islandless QFN lead frame;
[0009] Figure 2 shows a large-size chip mounted on the conventional islandless QFN lead frame with mounting glue contamination;
[0010] Figure 3 illustrates an exemplary pre-encapsulated islandless lead frame structure consistent with the disclosed embodiments; [0011] Figure 4 illustrates a large-size chip mounted on the pre-encapsulated islandless lead frame structure; and [0012] Figure 5 shows an exemplary packaging process based on the pre-encapsulated islandless lead frame structure consistent with the disclosed embodiments.
DETAILED DESCRIPTION
[0013] Reference will now be made in detail to exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
[0014] Fig. 3 illustrates an exemplary pre-encapsulated islandless lead frame structure 100 consistent with the disclosed embodiments. As shown in Fig. 3, islandless lead frame 100 includes a plurality of leads 1 and molding compound 2 filled in etched areas and the areas between the leads of the plurality of leads 1. Islandless lead frame 100 does not contain any island or die pad. Other components may also be included and certain components may be omitted. For example, islandless lead frame 100 may also include a first metal layer (not shown) on the top surfaces of the plurality of leads 1 and a second metal layer (not shown) on the back surfaces of the plurality of leads 1. [0015] The plurality of leads 1 may be made from a metal substrate (unnumbered). The molding compound 2 is filled up to the top surface and the back surface of the metal substrate such that both the top surface and the back surface of the metal substrate are flat planes.
[0016] Islandless lead frame structure 100 may be formed as a part of a packaging process. Fig. 5 illustrates an exemplary packaging process 200 consistent with the disclosed embodiments. As shown in Fig. 5, at the beginning of the packaging process 200, a metal substrate is provided (202). [0017] The metal substrate may have a top surface and a back surface, and may also have a desired thickness. The metal substrate may be made of any appropriate metal materials, such as copper, aluminum, iron, copper alloy, stainless steel, or nickel-iron alloy. The particular metal used for metal substrate may be determined based on the functionalities and characteristics of the chips to be packaged.
[0018] After the metal substrate is provided (202), adhesive films may be attached to the top surface and the back surface of the metal substrate (204). More particularly, a first photoresist film may be attached to the top surface of the metal substrate, and a second photoresist film may be attached to the back surface of the metal substrate. The first photoresist film and the second photoresist film may be attached using certain film equipment to protect the substrate from a later etching process. Further, the first photoresist film and second photoresist film can be used in a photolithographic process, and any of the first photoresist film and second photoresist film may be a dry photoresist film or a wet photoresist film. Other types of film may also be used. [0019] Further, etching patterns may be formed based on the first photoresist film and second photoresist film (206). More specifically, a top surface etching pattern may be formed using the first photoresist film and a back surface etching pattern may be formed using the second photoresist film via photolithography. That is, the etching patterns may be formed using a photolithographic process. A top surface etching mask is used to expose the first photoresist film, which is followed by development, and certain parts of the first photoresist film are removed to form the top surface etching pattern to uncover the areas on the metal substrate that need to be etched. Similarly, a back surface etching mask is used to expose the second photoresist film, which is' followed by development, and certain parts of the second photoresist film are removed to form the back surface etching pattern to uncover the areas on the metal substrate that need to be etched.
[0020] The top surface etching pattern corresponds to inner leads of the plurality of leads 1, and the back surface etching pattern corresponds to outer leads of the plurality of leads 1. The top surface etching pattern is designed in a way that the size of the area surrounded by the inner leads of the plurality of leads 1 is substantially large to fit a large chip. That is, the distance between two opposite inner leads is within a same range of the size of the large chip such that a large chip can be mounted on the lead frame without touching the inner leads of the plurality of leads 1.
[0021 ] On the other hand, the back surface etching pattern is designed in a way that the outer leads of the plurality of leads 1 extends towards to the center of the area surrounded by the plurality of leads 1 such that the length of the outer leads is larger than the length of the inner leads of the plurality of leads 1.
[0022] Further, an etching process may be performed on the top surface and back surface of the metal substrate (208). That is, the etching process is performed on the exposed areas on the top surface and back surface of the metal substrate, which are exposed by removing parts of the first and second photoresist films. The top surface of metal substrate is etched using the top surface etching pattern as a mask, and the back surface of metal substrate is etched using the back surface etching pattern as a mask.
[0023] The etching process may be a half etching and may be performed on both the top surface and the back surface simultaneously. After the etching process, the plurality of leads 1 and certain etched areas are formed on the metal substrate. The plurality of leads 1 have smaller length on top surface of the metal substrate and larger length on back surface of the metal substrate. Thus, with same size as conventional lead frames, such small-top-size and large- bottom-size lead structure can fit larger chip without causing any extra problems, such as mounting glue contamination. Other types of etching, such as a full etching, may also be used.
[0024] After the etching process, the remaining adhesive films on the surfaces of metal substrate are removed (210). The films may be removed by mechanical means or chemical means. Further, the etched metal substrate is encapsulated in a molding process or a pre- encapsulating process (212). That is, molding compound 2 is filled into the etched metal substrate using a mold. The term "pre-encapsulation" refers to the encapsulation or molding process that is performed after the etching process and before the subsequent plating process. [0025] After the molding compound is injected in the metal substrate, i.e., the islandless lead frame is pre-encapsulated, the pre-encapsulated islandless lead frame has a flat top surface comprising the exposed top surfaces of the plurality of leads 1 and the molding compound 2, and a flat back surface comprising the exposed back surfaces of the plurality of leads 1 and the molding compound 2. [0026] Optionally, if the lead frame 100 includes the first metal layer on the top surface of the metal substrate and the second metal layer on the back surface of the metal substrate, a plating process may be performed on the pre-encapsulated lead frame to form the first metal layer and the second metal layer. The plating process may include any appropriate type of electrical or chemical plating process, such as a multi-layer electrical plating process. The plating material may include gold, nickel-gold, nickel-palladium-gold, or silver. Other materials may also be used.
[0027] The first metal layer may be formed on the top surfaces of the plurality of leads 1 to provide inner leads for the plurality of leads 1. The second metal layer may be formed on back surfaces of the plurality of leads 1 to provide outer leads for leads 1. Alternatively, the first metal layer and the second metal layer may be formed on the top surface and the back surface of the metal substrate, respectively, before the etching process.
[0028] The pre-encapsulated lead frame 100 may then be used in other subsequent processes in the packaging process 200 (214). For example, as shown in Fig. 4, a die 3 may be attached on the pre-encapsulated lead frame 100 using conductive or non-conductive adhesive material 4 in a die attaching process. Although the size of die 3 may be larger than the size of the area surrounded by the outer leads of the plurality of leads 1, the adhesive material 4 does not contaminate the inner leads of the plurality of leads 1. That is, even when a substantial area of the die 3 is outside the area surrounded by the outer leads, the die 3 does not touch or is above any of the inner leads of the plurality of leads 1.
[0029] Further the top surface of die 3 and the top surface of the inner leads of the plurality of leads 1 are connected with metal wires in a wire bonding process. The inner leads, the die 3, and the metal wires are then encapsulated using encapsulation material 2. For example, molding equipment may be used to seal or encapsulate the packaging structure by the molding compound 2. Post-molding curing may also be performed such that the molding compound 2 or other plastic encapsulation materials may also be cured.
INDUSTRIAL APPLICABILITY AND ADVANTAGEOUS EFFECTS
[0030] Without limiting the scope of any claim and/or the specification, examples of industrial applicability and certain advantageous effects of the disclosed embodiments are listed for illustrative purposes. Various alternations, modifications, or equivalents to the technical solutions of the disclosed embodiments can be obvious to those skilled in the art. [0031] The disclosed lead frame structures and manufacturing methods may be applied in a variety of semiconductor packaging applications for different carriers with different substrates and filling materials. For example, the disclosed structures and methods may be used to package plastic leaded chip carrier (PLCC), plastic quad flat pack (PQFP), ball grid array (BGA), system in package (SiP) or 3D ICs, and multi-chip module, etc.
[0032] By using the disclosed methods and structures, an islandless lead frame structure can be created using etching and pre-encapsulation. Such lead frame structures and methods can be suitable for mounting large-size chips. The outer leads extends to the area surrounded by the outer leads of the plurality of leads such that the length of the outer leads is bigger than the length of the inner leads. That is, the plurality of leads have smaller length on top surface of the metal substrate and larger length on back surface of the metal substrate. Such small-top-size and large-bottom-size lead structure can fit larger chip without causing mounting glue contamination and the chip scale can also be increased.
Reference Signs List
Leads 21
Molding compound 22
Die 23
Adhesive material 24
Lead frame structure 100
Leads 1
Molding compound 2
Die 3
Adhesive material 4
Packaging process 200
Providing a metal substrate 202
Attaching adhesive films 204
Forming etching patterns 206
Performing an etching process 208
Removing adhesive films 210
Pre-encapsulating the lead frame 212
Performing other packaging processes 214

Claims

What is claimed is:
1. A method for manufacturing an islandless lead frame structure in a semiconductor
packaging process, comprising: providing a metal substrate having a top surface and a back surface; forming a first photoresist film on the top surface of the metal substrate;
forming a top surface etching pattern in the first photoresist film using photolithography; forming a second photoresist film on the back surface of the metal substrate;
forming a back surface etching pattern in the second photoresist film using
photolithography; performing an etching process on the top surface and the back surface of the metal substrate using the top surface etching pattern and the back surface etching pattern as the respective masks to form a plurality of leads, wherein outer leads of the plurality of leads on the back surface extend towards an area surrounded by the outer leads such that a length of the outer leads is larger than a length of inner leads of the plurality of leads on the top surface; removing the first photoresist film and the second photoresist film; and encapsulating the etched metal substrate using a molding compound exposing top surfaces and back surfaces of the plurality leads.
2. The method according to claim 1 , wherein: the etching process is a half etching process.
3. The method according to claim 2, wherein: the etching process is performed on the top surface and the back surface of the metal substrate simultaneously using the top surface etching pattern and the back surface etching pattern as the respective masks.
4. The method according to claim 1, further including: performing a plating process on the metal substrate to form a first metal layer on the top surface of the metal substrate and a second metal layer on the back surface of the metal substrate, wherein the first metal layer contains the inner leads of the plurality of leads, and the second metal layer contains the outer leads of the plurality of leads.
5. The method according to claim 1 , further including: attaching a die on the pre-encapsulated lead frame using an adhesive material in a die attaching process, wherein a substantial area of the die is outside the area surrounded by the outer leads without touching the inner leads of the plurality of leads; connecting a top surface of the die and top surfaces of the inner leads of the plurality of leads with metal wires in a wire bonding process; and encapsulating the inner leads, the die, and the metal wires using a molding compound.
6. An islandless lead frame structure for semiconductor packaging, comprising: a plurality of leads formed based on a metal substrate by an etching process; and a molding compound used to encapsulate the etched metal substrate with the plurality of leads, wherein the etching process is performed by: providing the metal substrate; forming a first photoresist film on a top surface of the metal substrate; forming a top surface etching pattern in the first photoresist film using photolithography; forming a second photoresist film on a back surface of the metal substrate; forming a back surface etching pattern in the second photoresist film using photolithography; performing an etching process on the top surface and the back surface of the metal substrate using the top surface etching pattern and the back surface etching pattern as the respective masks to form a plurality of leads, outer leads of the plurality of leads on the back surface extending towards an area surrounded by the outer leads such that a length of the outer leads is larger than a length of inner leads of the plurality of leads on the top surface; and removing the first photoresist film and the second photoresist film.
7. The islandless lead frame structure according to claim 6, wherein: the etching process is a half etching process.
8. The islandless lead frame structure according to claim 7, wherein: the etching process is performed on the top surface and the back surface of the metal substrate simultaneously using the top surface etching pattern and the back surface etching pattern as the respective masks.
9. The islandless lead frame structure according to claim 6, further including: a first metal layer formed on the top surface of the metal substrate and a second metal layer formed on the back surface of the metal substrate by a plating process performed on the metal substrate, wherein the first metal layer contains an inner surface of the inner leads of the plurality of leads, and the second metal layer contains an outer surface of the outer leads of the plurality of leads.
10. The islandless lead frame structure according to claim 6, further including: a die attached on the islandless lead frame structure using an adhesive material by a die attaching process, wherein a substantial area of the die is outside the area surrounded by the outer leads without touching the inner leads of the plurality of leads;
metal wires connecting a top surface of the die and top surfaces of the inner leads of the plurality of leads by a wire bonding process; and a molding compound encapsulating the inner leads, the die, and the metal wires.
PCT/CN2012/001162 2011-09-13 2012-08-28 Pre-encapsulated islandless lead frame structures and manufacturing method WO2013037188A1 (en)

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