TWI556359B - Quad flat non-leaded package structure and leadframe thereof - Google Patents

Quad flat non-leaded package structure and leadframe thereof Download PDF

Info

Publication number
TWI556359B
TWI556359B TW104110498A TW104110498A TWI556359B TW I556359 B TWI556359 B TW I556359B TW 104110498 A TW104110498 A TW 104110498A TW 104110498 A TW104110498 A TW 104110498A TW I556359 B TWI556359 B TW I556359B
Authority
TW
Taiwan
Prior art keywords
leadframe
package structure
quad flat
flat non
leaded package
Prior art date
Application number
TW104110498A
Other versions
TW201635447A (en
Inventor
Tzu Sheng Wu
Original Assignee
Chipmos Technologies Inc
Chipmos Technologies Bermuda
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipmos Technologies Inc, Chipmos Technologies Bermuda filed Critical Chipmos Technologies Inc
Priority to TW104110498A priority Critical patent/TWI556359B/en
Publication of TW201635447A publication Critical patent/TW201635447A/en
Application granted granted Critical
Publication of TWI556359B publication Critical patent/TWI556359B/en

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
TW104110498A 2015-03-31 2015-03-31 Quad flat non-leaded package structure and leadframe thereof TWI556359B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW104110498A TWI556359B (en) 2015-03-31 2015-03-31 Quad flat non-leaded package structure and leadframe thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW104110498A TWI556359B (en) 2015-03-31 2015-03-31 Quad flat non-leaded package structure and leadframe thereof
CN201510336607.1A CN106206479A (en) 2015-03-31 2015-06-17 Quad flat non-leaded package structure and leadframe thereof

Publications (2)

Publication Number Publication Date
TW201635447A TW201635447A (en) 2016-10-01
TWI556359B true TWI556359B (en) 2016-11-01

Family

ID=57452994

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104110498A TWI556359B (en) 2015-03-31 2015-03-31 Quad flat non-leaded package structure and leadframe thereof

Country Status (2)

Country Link
CN (1) CN106206479A (en)
TW (1) TWI556359B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200627608A (en) * 2005-01-26 2006-08-01 Advanced Semiconductor Eng Quad flat no-lead chip package structure
TW201010035A (en) * 2008-08-29 2010-03-01 Chipmos Technologies Inc Quad flat non-leaded package
TW201027637A (en) * 2009-01-15 2010-07-16 Chipmos Technologies Inc Manufacturing process for quad flat non-leaded package
TW201027642A (en) * 2009-01-15 2010-07-16 Chipmos Technologies Inc Manufacturing process for quad flat non-leaded package
TW201027643A (en) * 2009-01-15 2010-07-16 Chipmos Technologies Inc Manufacturing process for quad flat non-leaded package

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1287452C (en) * 2002-11-14 2006-11-29 矽品精密工业股份有限公司 Windowing ball grid array semiconductor packaging element with wire-holder as carrier and making method thereof
DE10255844B3 (en) * 2002-11-29 2004-07-15 Infineon Technologies Ag Integrated circuit manufacturing method of chip scale package, involves attaching solder balls in area that is uncovered by resist element, of patterned rewriting element, in patterned form
CN1677649A (en) * 2004-03-30 2005-10-05 相互股份有限公司 Semiconductor element with crystal-particle-protection function
CN100470783C (en) * 2006-08-15 2009-03-18 力成科技股份有限公司 Encapsulation structure of lead rack base ball grid array and its wafer carrier
US8569894B2 (en) * 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8786062B2 (en) * 2009-10-14 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package and process for fabricating same
US8884415B2 (en) * 2013-02-28 2014-11-11 Nxp B.V. IC package with stainless steel leadframe

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200627608A (en) * 2005-01-26 2006-08-01 Advanced Semiconductor Eng Quad flat no-lead chip package structure
TW201010035A (en) * 2008-08-29 2010-03-01 Chipmos Technologies Inc Quad flat non-leaded package
TW201027637A (en) * 2009-01-15 2010-07-16 Chipmos Technologies Inc Manufacturing process for quad flat non-leaded package
TW201027642A (en) * 2009-01-15 2010-07-16 Chipmos Technologies Inc Manufacturing process for quad flat non-leaded package
TW201027643A (en) * 2009-01-15 2010-07-16 Chipmos Technologies Inc Manufacturing process for quad flat non-leaded package

Also Published As

Publication number Publication date
CN106206479A (en) 2016-12-07
TW201635447A (en) 2016-10-01

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