TWI393194B - Manufacturing process for quad flat non-leaded package - Google Patents

Abstract

A manufacturing process for a Quad Flat Non-leaded (QFN) package is provided. First, a conductive layer having a plurality of recesses and a patterned solder resist layer on the conductive layer are provided, wherein the patterned solder resist layer covers the recesses of the conductive layer. A plurality of chips are bonded onto the patterned solder resist layer such that the patterned solder resist layer is between the chips and the conductive layer. The chips are electrically connected to the conductive layer by a plurality of bonding wires. At least one molding compound is formed to encapsulate the conductive layer, the patterned solder resist layer, the chips and the bonding wires. A part of the conductive layer uncovered by the patterned solder resist layer is removed so as to form a patterned conductive layer. Then, the molding compound and the patterned conductive layer are separated.

Description

Quad flat no-lead package process

The present invention relates to a wafer packaging process, and more particularly to a quad flat Non-leaded (QFN) packaging process.

With the rapid development of the semiconductor industry, electronic and semiconductor devices are widely used in daily life, such as entertainment, education, transportation, and home appliances. Electronic products are developed in terms of complex design, small size, light weight and humanity, so as to bring more convenience to users. In package structures, leadframes are one of the commonly used components and are used in a variety of packaged products. In terms of the type of lead frame, the Quad Flat Package (QFP) can be divided into quad flat package with "I" lead (QFI) and J-type flat chip. Quad flat package with "J" lead, QFJ) and Quad Flat Non-leaded (QFN) package. The lead frame of the quad flat no-lead package does not exceed the edge of the package structure, so it has a small volume. In addition, the quad flat no-lead package has a short signal transmission path and a fast signal transmission speed, so it has always been one of the mainstream of the low pin count configuration.

Generally, in the manufacturing process of a quad flat no-lead package, a plurality of wafers are disposed on a lead frame, wherein the lead frame includes a plurality of interconnected pin groups, and each wafer is surrounded by a pin group. . Each wafer is electrically connected to a pin group through a wire bonding process. Next, at least one encapsulant for covering the lead frame, the wafer, and the bonding wire is formed. Finally, a plurality of quad flat no-lead packages are formed through a singulation process, wherein the singulation process includes a punch process or a sawing process.

The present invention provides a quad flat no-lead packaging process that can produce a quad flat no-lead package having a small thickness.

The invention proposes a quad flat no-lead packaging process. First, a conductive layer having a plurality of recesses and a patterned solder mask layer on the conductive layer are provided, wherein the patterned solder mask covers the recess of the conductive layer. A plurality of wafers are disposed on the patterned solder mask layer such that the patterned solder mask layer is between the wafer and the conductive layer. The wafer is electrically connected to the conductive layer through a plurality of bonding wires. At least one encapsulant is formed to encapsulate the conductive layer, the patterned solder mask layer, the wafer, and the bonding wire. A portion of the conductive layer is removed to form a patterned conductive layer. Next, the encapsulant and the patterned conductive layer are separated.

In an embodiment of the invention, the above described quad flat no-lead packaging process, wherein a plurality of first openings are formed in the patterned solder mask layer, and the first opening exposes a portion of the conductive layer.

In one embodiment of the invention, the quad flat no-lead package process further includes forming an adhesive layer between the wafer and the patterned solder mask layer.

In one embodiment of the invention, the quad flat no-lead packaging process described above, wherein a B-stage adhesive layer is formed on the patterned solder mask layer before the wafer is attached to the patterned solder mask layer.

In an embodiment of the invention, the patterned solder mask layer is a B-layer.

In an embodiment of the invention, the material of the B-layer is a photosensitive material.

The invention proposes a quad flat no-lead packaging process. First, a conductive layer having a plurality of recesses and a patterned solder mask layer on the conductive layer are provided, wherein the patterned solder mask layer covers the recesses of the conductive layer. A plurality of wafers are disposed on the conductive layer such that the patterned solder mask layer and the wafer are on the same side of the conductive layer. The wafer is electrically connected to the conductive layer through a plurality of bonding wires. At least one encapsulant is formed to encapsulate the conductive layer, the patterned solder mask layer, the wafer, and the bonding wire. A portion of the conductive layer is removed to form a patterned conductive layer. Next, the encapsulant and the patterned conductive layer are separated.

In one embodiment of the invention, the above method of providing a conductive layer having a recess and a patterned solder mask layer includes providing a conductive layer having a recess. A solder mask layer is formed on the conductive layer. The solder mask layer is patterned to form a patterned solder mask layer, wherein the patterned solder mask layer exposes a portion of the conductive layer.

In one embodiment of the invention, the quad flat no-lead package process described above, wherein a plurality of wafer pads and a plurality of leads are formed on the patterned conductive layer.

In an embodiment of the present invention, the quad flat no-lead package process, wherein a plurality of first openings and a plurality of second openings are formed in the patterned solder mask layer, and the first opening and the second opening are exposed Part of the conductive layer.

In an embodiment of the invention, the bonding wire passes through the first opening to be electrically connected to the patterned conductive layer.

In an embodiment of the invention, the wafer is disposed on the conductive layer exposed by the second opening.

In one embodiment of the invention, the quad flat no-lead package process further includes forming an adhesive layer between the wafer and the conductive layer.

In an embodiment of the invention, the adhesive layer is a B-stage adhesive layer.

In an embodiment of the invention, the B-stage adhesive layer is formed in advance on a back side of the wafer.

In one embodiment of the invention, the quad flat no-lead packaging process described above, wherein a B-stage adhesive layer is formed on the conductive layer before the wafer is attached to the conductive layer.

In one embodiment of the invention, the recess is filled with a patterned solder mask layer.

In an embodiment of the invention, the conductive layer has a first surface and a second surface, and the recess is located on the first surface.

In one embodiment of the invention, the above method of removing a portion of the conductive layer to form a patterned conductive layer includes etching a portion of the conductive layer from the second surface to expose a partially patterned solder mask layer.

In an embodiment of the invention, the quad flat no-lead packaging process further includes performing a browning process or a blackening process on the conductive layer.

Based on the above, the quad flat no-lead packaging process of the present invention produces a quad flat no-lead package having a solder mask layer for enhancing the structural strength such that the patterned conductive layer can have a small thickness.

The above described features and advantages of the present invention will be more apparent from the following description.

1A-1I are process cross-sectional views showing a process of a quad flat no-lead package according to an embodiment of the invention. Referring to FIG. 1A, a conductive layer 110 having a first surface 112 and a second surface 114 is provided. Next, the conductive layer 110 located in the predetermined region is partially removed to form a plurality of grooves R on the first surface 112 of the conductive layer 110. In the present embodiment, the groove R is formed by a half-etching process or a stamping process.

Referring to FIG. 1B, a solder mask layer 120 is formed to completely cover the first surface 112 of the conductive layer 110 such that the recess R formed on the first surface 112 of the conductive layer 110 is filled with the solder monolayer 120. In a preferred embodiment, a brown oxidation process or a black oxidation process may be performed on the conductive layer 110 to increase the surface roughness of the conductive layer 110, thereby improving the conductive layer 110 and the solder mask. The bonding force between the layers 120.

Next, referring to FIG. 1C, the solder mask layer 120 is patterned to form a patterned solder mask layer 120' having a plurality of first openings 122, wherein the first openings 122 expose portions of the first surface 112. In other words, the patterned solder mask layer 120' formed on a portion of the first surface 112 defines a plurality of first pads 118.

In this embodiment, the patterned solder mask layer 120 ′ may be a B-staged film (also a solder mask film), and the first opening 122 is attached to the patterned solder mask layer 120 ′. The conductive layer 110 is formed before or after. In an alternative embodiment, a liquid solder mask coating can be applied to the first surface 112 of the conductive layer 110 and cured and patterned to form a patterned solder mask layer 120' and liquid soldered. The cover coat can be a B-stage liquid weld cap coating. In the present embodiment, the patterned solder mask layer 120' is, for example, a photosensitive B-staged film.

In addition, in a preferred embodiment, a plating conductive layer (not shown) may be formed on the first pad 118 through a plating process. The electroplated conductive layer can be a nickel gold laminate or other suitable metal layer. It is noted that the plated conductive layer can be formed before or after the patterned solder mask layer 120' is formed on the conductive layer 110.

Referring to FIG. 1D, a plurality of wafers 130 are adhered to the patterned solder mask layer 120', and then a plurality of bonding wires 150 are formed to electrically connect the wafer 130 and the conductive layer 110. Each of the wafers 130 has an active surface 132 and a relative surface. A back surface 134 of the active surface 132 and a plurality of second pads 136 disposed on the active surface 132. Each of the wafers 130 is adhered to the patterned solder mask layer 120' via an adhesive layer 140 between the wafer 130 and the conductive layer 110 such that the patterned solder mask layer 120' is positioned between the conductive layer 110 and each of the wafers 130. In an alternative embodiment, the wafer 130 may be adhered to the patterned solder mask layer 120' without the adhesive layer 140, wherein the patterned solder mask layer 120' is a B-layer formed on the conductive layer 110, and the pattern The chemical mask layer 120' is not fully cured prior to placement of the wafer 130.

In this embodiment, the bonding wires 150 are formed through a wire bonding process such that the bonding wires 150 are electrically connected between a first bonding pad 118 and a second bonding pad 136. The bonding wire 150 is, for example, a gold wire.

In the present embodiment, the adhesive layer 140 is, for example, a B-staged adhesive layer. The B-stage adhesive layer 140 may be 800-800, 8008 HT, 6200, 6201, 6202C of ABLESTIK or SA-200-6, SA-200-10 supplied by HITACHI Chemical CO., Ltd. In one embodiment of the invention, the B-stage adhesive layer 140 is formed on the back side of a wafer. A plurality of wafers 130 having an adhesive layer 140 on the back side 134 can be obtained after dicing the wafer. Therefore, the B-stage adhesive layer 140 is suitable for mass production. Additionally, the B-stage adhesive layer 140 can be formed by spin coating, printing, or other suitable process. The adhesive layer 140 is formed in advance on the back surface 134 of the wafer 130. In particular, a wafer having a plurality of wafers 130 arranged in an array may be provided first. Next, a second-order adhesive layer is formed on the back surface 134 of the wafer 130, and partially cured by heat or ultraviolet irradiation to form a B-stage adhesive layer 140. Alternatively, a B-stage adhesive layer 140 may be formed on the patterned solder mask layer 120' before the wafer 130 is attached to the patterned solder mask layer 120'.

In the present embodiment, the B-stage adhesive layer 140 is completely cured after the wafer 130 is attached to the patterned solder mask layer 120', or is then fully cured by post curing treatment, or in the encapsulated colloid. 160 is completely cured after coating.

Referring to FIG. 1E, at least one encapsulant 160 encapsulating the conductive layer 110, the patterned solder mask layer 120', the wafer 130, and the bonding wires 150 is formed. The material of the encapsulant 160 is, for example, an epoxy resin.

Referring to FIG. 1F, the coated conductive layer 110 and the patterned solder can be formed as compared with the encapsulant 160 that forms the conductive layer 110, the patterned solder mask layer 120', the wafer 130, and the bonding wire 150. A plurality of encapsulants 160' of the cap layer 120', the wafer 130, and the bonding wires 150.

Referring to FIG. 1G and FIG. 1H, the second surface 114 of the conductive layer 110 of FIG. 1G or FIG. 1H is removed by etching to form a pattern of exposed portions of the patterned solder mask layer 120 ′. The conductive layer 110', wherein the patterned conductive layer 110' has a plurality of wafer holders 110a and a plurality of pins 110b. Next, a plurality of quad flat no-lead packages 100 (shown in FIG. 1G) or a plurality of quad flat no-lead packages 100' (shown in FIG. 1H) are formed through a singulation process, wherein the singulation process includes cutting Process or punch process.

It is noted that a portion of the conductive layer 110 may be removed from the second surface 114 in any of the processing steps after the solder mask layer 120 is formed on the conductive layer 110. A method of removing a portion of the conductive layer 110 from the second surface 114 is, for example, a back-side etching process.

As shown in FIG. 1G , the quad flat no-lead package 100 of the present invention mainly includes a patterned conductive layer 110 ′, a patterned solder mask layer 120 ′, a wafer 130 , a plurality of bonding wires 150 , and an encapsulant 160 . . The patterned conductive layer 110' has a first surface 112, wherein the patterned conductive layer 110' includes a wafer holder 110a and a plurality of pins 110b surrounding the wafer holder 110a, and the patterned solder mask layer 120' is patterned from the conductive layer The first surface 112 of 110' extends to a region between the wafer holder 110a and the pin 110b. The patterned solder mask layer 120' is disposed on the first surface 112, wherein the patterned solder mask layer 120' exposes a portion of the first surface 112. The wafer 130 is disposed on the patterned solder mask layer 120', wherein the patterned solder mask layer 120' is between the patterned conductive layer 110' and the wafer 130. The bonding wire 150 is electrically connected to the patterned conductive layer 110' exposed by the wafer 130 and the patterned solder mask layer 120'. The encapsulant 160 encloses the patterned conductive layer 110', the patterned solder mask layer 120', the wafer 130, and the bonding wires 150.

Referring to FIG. 1I, in an alternative embodiment, a plurality of second openings 124 may be formed in the patterned solder mask layer 120' such that the wafers 130 are disposed on a second opening 124 and adhered to the patterned pattern. The first surface 112 of the solder mask layer 120' is exposed. In this embodiment, the adhesive layer 140 is, for example, a B-stage adhesive layer, a conductive layer or a non-conductive layer.

In summary, the quad flat no-lead package manufactured by the quad flat no-lead package process of the present invention has a solder mask layer for strengthening the structural strength, compared to the conventional quad flat no-lead package process. So that the patterned conductive layer can have a small thickness. In addition, the quad flat no-lead package has a smaller overall thickness and lower manufacturing cost to increase throughput.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 100’. . . Quad flat no-lead package

110. . . Conductive layer

110’. . . Patterned conductive layer

110a. . . Wafer holder

110b. . . Pin

112. . . First surface

114. . . Second surface

118. . . First pad

120. . . Welding mask

120’. . . Patterned solder mask

122. . . First opening

124. . . Second opening

130. . . Wafer

132. . . Active surface

134. . . back

136. . . Second pad

140. . . Adhesive layer

150. . . Welding wire

160, 160’. . . Encapsulant

R. . . Groove

1A-1I are process cross-sectional views showing a process of a quad flat no-lead package according to an embodiment of the invention.

100. . . Quad flat no-lead package

110’. . . Patterned conductive layer

110a. . . Wafer holder

110b. . . Pin

112. . . First surface

118. . . First pad

120’. . . Patterned solder mask

122. . . First opening

130. . . Wafer

132. . . Active surface

134. . . back

136. . . Second pad

140. . . Adhesive layer

150. . . Welding wire

160. . . Encapsulant

Claims (25)

A quad flat no-lead packaging process includes: providing a conductive layer having a plurality of recesses and a patterned solder mask layer on the conductive layer, wherein the patterned solder mask layer covers the recesses of the conductive layer a conductive layer having a first surface and a second surface, and the recesses are located on the first surface; a plurality of wafers are disposed on the patterned solder mask layer to enable the patterned solder mask layer Located between the wafers and the conductive layer; electrically connecting the wafers to the conductive layer through a plurality of bonding wires; forming at least one encapsulant to encapsulate the conductive layer, the patterned solder mask layer, and the wafers And the bonding wires; removing a portion of the conductive layer to form a patterned conductive layer, wherein removing a portion of the conductive layer to form the patterned conductive layer comprises etching a portion of the conductive layer from the second surface to expose And extracting the patterned solder mask layer; and dividing the encapsulant and the patterned conductive layer. The quad flat no-lead packaging process of claim 1, wherein the method of providing the conductive layer and the patterned solder mask layer having the recesses comprises: providing the conductive layer having the recesses Forming a solder mask layer on the conductive layer; and patterning the solder mask layer to form the patterned solder mask layer, wherein the patterned solder mask layer exposes a portion of the conductive layer. A quad flat no-lead seal as described in claim 1 A mounting process in which a plurality of wafer holders and a plurality of leads are formed on the patterned conductive layer. The quad flat no-lead packaging process of claim 1, wherein a plurality of first openings are formed in the patterned solder mask layer, and the first openings expose a portion of the conductive layer. The quad flat no-lead packaging process of claim 4, wherein the bonding wires pass through the first openings to be electrically connected to the patterned conductive layer. The quad flat no-lead packaging process of claim 1, further comprising forming an adhesive layer between the wafers and the patterned solder mask layer. The quad flat no-lead packaging process of claim 6, wherein the adhesive layer is a B-stage adhesive layer. The quad flat no-lead packaging process of claim 7, wherein the B-stage adhesive layer is previously formed on a back side of the wafer. The quad flat no-lead packaging process of claim 7, wherein the B-stage adhesive layer is formed on the patterned solder mask layer before the wafers are attached to the patterned solder mask layer. . The quad flat no-lead packaging process of claim 1, wherein the recesses are filled by the patterned solder mask layer. The quad flat no-lead packaging process of claim 1, wherein the patterned solder mask layer is a B-layer. For example, the quad flat no-lead packaging process described in claim 11 wherein the material of the B layer is a photosensitive material. The quad flat no-lead packaging process as described in claim 1 further includes performing a browning process or a blackening process on the conductive layer. A quad flat no-lead packaging process includes: providing a conductive layer having a plurality of recesses and a patterned solder mask layer on the conductive layer, wherein the patterned solder mask layer covers the recesses of the conductive layer a conductive layer having a first surface and a second surface, and the recesses are located on the first surface; a plurality of wafers are disposed on the conductive layer to enable the patterned solder mask layer and the The wafers are located on the same side of the conductive layer; the wafers are electrically connected to the conductive layer through a plurality of bonding wires; at least one encapsulant is formed to encapsulate the conductive layer, the patterned solder mask layer, the wafers, and the a plurality of bonding wires; removing a portion of the conductive layer to form a patterned conductive layer, wherein removing a portion of the conductive layer to form the patterned conductive layer comprises etching a portion of the conductive layer from the second surface to expose a portion The patterned solder mask layer; and the encapsulation colloid and the patterned conductive layer are separated. The quad flat no-lead packaging process of claim 14, wherein the method of providing the conductive layer and the patterned solder mask layer having the recesses comprises: providing the conductive layer having the recesses Forming a solder mask layer on the conductive layer; and patterning the solder mask layer to form the patterned solder mask layer, wherein the pattern The chemical mask layer exposes a portion of the conductive layer. The quad flat no-lead packaging process of claim 14, wherein a plurality of wafer holders and a plurality of pins are formed on the patterned conductive layer. The quad flat no-lead package process of claim 14, wherein a plurality of first openings and a plurality of second openings are formed in the patterned solder mask layer, and the first openings and the plurality of The two openings expose a portion of the conductive layer. The quad flat no-lead packaging process of claim 17, wherein the bonding wires pass through the first openings to be electrically connected to the patterned conductive layer. The quad flat no-lead package process of claim 17, wherein the wafers are disposed on the conductive layer exposed by the second openings. The quad flat no-lead packaging process of claim 14, further comprising forming an adhesive layer between the wafers and the conductive layer. The quad flat no-lead packaging process of claim 20, wherein the adhesive layer is a B-stage adhesive layer. The quad flat no-lead packaging process of claim 21, wherein the B-stage adhesive layer is previously formed on a back side of the wafer. The quad flat no-lead packaging process of claim 21, wherein the B is before the wafers are attached to the conductive layer. A step adhesive layer is formed on the conductive layer. The quad flat no-lead packaging process of claim 14, wherein the recesses are filled by the patterned solder mask layer. The quad flat no-lead packaging process as described in claim 14 further includes performing a browning process or a blackening process on the conductive layer.