TWI761116B - Semiconductor package structure and leadframe - Google Patents

Semiconductor package structure and leadframe Download PDF

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TWI761116B
TWI761116B TW110108067A TW110108067A TWI761116B TW I761116 B TWI761116 B TW I761116B TW 110108067 A TW110108067 A TW 110108067A TW 110108067 A TW110108067 A TW 110108067A TW I761116 B TWI761116 B TW I761116B
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pins
package structure
lead frame
semiconductor package
material layer
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TW110108067A
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Chinese (zh)
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TW202236560A (en
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石智仁
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南茂科技股份有限公司
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Priority to CN202110712329.0A priority patent/CN115036283A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

A semiconductor package structure includes a leadframe, a chip, a molding compound and a conductive material layer. The leadframe includes a die pad and a plurality of leads surrounding the die pad. Each of the leads has a top surface and a bottom surface opposite to each other, and a peripheral surface obliquely connecting to the top surface and the bottom surface. The chip is disposed on the die pad of the leadframe and electrically connected with the lead. The molding compound covers the leadframe and the chip. There is an accommodating space between the molding compound and the peripheral surface of each of the leads. The conductive material layer at least encapsulates each of the leads and the accommodating space.

Description

半導體封裝結構及導線架Semiconductor package structure and lead frame

本發明是有關於一種半導體結構，且特別是有關於一種半導體封裝結構及導線架。The present invention relates to a semiconductor structure, and more particularly, to a semiconductor package structure and a lead frame.

一般來說，現有的四方扁平無引腳（Quad flat no-lead, QFN）封裝結構中，引腳的底面及側面皆為一平面並且受到封裝膠體的包覆而局部外露引腳的底面，透過封裝膠體底部外露的引腳來與外部電路板接觸做為電性連接的途徑。因此，當引腳的底面與外部電路接合時，由於電性連接的引腳位於封裝膠體底部，難以透過外觀檢查來確認其與電路板的連接狀況，容易因銲料與基板之間的接合面積不夠或連接狀況不佳而影響電性。再者，於封裝膠體單體化分割時，刀具切割導線架時會產生金屬毛邊，而導線架也容易因刀具切割後所產生的金屬毛邊而產生短路，進而影響四方扁平無引腳封裝結構的可靠度。Generally speaking, in the existing quad flat no-lead (QFN) package structure, the bottom surface and the side surface of the lead are both flat and covered by the encapsulating compound, and the bottom surface of the lead is partially exposed. The exposed pins at the bottom of the encapsulant are in contact with the external circuit board as a way of electrical connection. Therefore, when the bottom surface of the lead is connected to the external circuit, since the electrically connected lead is located at the bottom of the encapsulant, it is difficult to confirm the connection status between the lead and the circuit board through visual inspection, and the bonding area between the solder and the substrate is likely to be insufficient. or poor connection, which affects the electrical performance. Furthermore, when the packaging colloid is singulated and divided, metal burrs will be generated when the tool cuts the lead frame, and the lead frame is easily short-circuited due to the metal burrs generated by the tool cutting, which will affect the performance of the quad flat leadless package structure. reliability.

本發明提供一種半導體封裝結構，其具有較佳的結構可靠度，可方便且快速地完成後續與外部電路接合後的外觀檢查。The present invention provides a semiconductor package structure, which has better structural reliability and can conveniently and quickly complete the appearance inspection after being joined with an external circuit.

本發明另提供一種導線架，其引腳具有較大的接合面積，可增加電性連接的可靠度。The present invention further provides a lead frame whose pins have a larger bonding area, which can increase the reliability of electrical connection.

本發明提供一種半導體封裝結構，其包括一導線架、一晶片、一封裝膠體以及一導電材料層。導線架包括一承載座以及環繞承載座的多個引腳。每一引腳具有彼此相對的一頂面與一底面以及傾斜地連接頂面與底面的一周圍表面。晶片配置於導線架的承載座上並與導線架的引腳電性連接。封裝膠體覆蓋導線架與晶片。封裝膠體與每一引腳的周圍表面之間具有一容置空間。導電材料層至少部分包覆每一引腳以及容置空間。The invention provides a semiconductor packaging structure, which includes a lead frame, a chip, a packaging colloid and a conductive material layer. The lead frame includes a carrier and a plurality of pins surrounding the carrier. Each pin has a top surface and a bottom surface opposite to each other and a peripheral surface obliquely connecting the top surface and the bottom surface. The chip is arranged on the bearing seat of the lead frame and is electrically connected with the pins of the lead frame. The encapsulant covers the lead frame and the chip. There is an accommodating space between the encapsulating compound and the surrounding surface of each lead. The conductive material layer at least partially covers each pin and the accommodating space.

在本發明的一實施例中，上述的周圍表面包括一平滑曲面、一粗糙曲面或一傾斜面。In an embodiment of the present invention, the above-mentioned surrounding surface includes a smooth curved surface, a rough curved surface or an inclined surface.

在本發明的一實施例中，上述的半導體封裝結構更包括一電路板。電路板包括至少一接墊以及位於至少一接墊上的一銲料。導線架配置於電路板上。每一引腳透過導電材料層以及銲料而電性連接至至少一接墊。In an embodiment of the present invention, the above-mentioned semiconductor package structure further includes a circuit board. The circuit board includes at least one pad and a solder on the at least one pad. The lead frame is arranged on the circuit board. Each pin is electrically connected to at least one pad through the conductive material layer and solder.

在本發明的一實施例中，上述的半導體封裝結構還包括一導電覆層，配置於每一引腳的頂面上。In an embodiment of the present invention, the above-mentioned semiconductor package structure further includes a conductive coating layer disposed on the top surface of each lead.

在本發明的一實施例中，上述的半導體封裝結構更包括多條導線，電性連接於晶片與位於引腳上的導電覆層上。In an embodiment of the present invention, the above-mentioned semiconductor package structure further includes a plurality of wires, which are electrically connected to the chip and the conductive coating on the pins.

在本發明的一實施例中，上述的封裝膠體的一第一下表面與導電材料層的一第二下表面之間具有一高度差。In an embodiment of the present invention, there is a height difference between a first lower surface of the encapsulant and a second lower surface of the conductive material layer.

在本發明的一實施例中，上述的每一引腳的底面與封裝膠體的一第一下表面之間具有一高度差。In an embodiment of the present invention, there is a height difference between the bottom surface of each lead and a first lower surface of the encapsulant.

本發明還提供一種導線架，其包括一承載座以及環繞承載座的多個引腳。每一引腳具有彼此相對的一頂面與一底面以及傾斜地連接頂面與底面的一周圍表面。周圍表面包括一平滑曲面、一粗糙曲面或一傾斜面。The present invention also provides a lead frame, which includes a bearing seat and a plurality of pins surrounding the bearing seat. Each pin has a top surface and a bottom surface opposite to each other and a peripheral surface obliquely connecting the top surface and the bottom surface. The surrounding surface includes a smooth curved surface, a rough curved surface or an inclined surface.

在本發明的一實施例中，上述的每一引腳的周圍表面與底面的一外表面包覆有一導電材料層。In an embodiment of the present invention, an outer surface of the peripheral surface and the bottom surface of each of the above-mentioned pins is covered with a conductive material layer.

在本發明的一實施例中，上述的每一引腳的頂面設置有一導電覆層。In an embodiment of the present invention, a conductive coating is disposed on the top surface of each of the above-mentioned pins.

基於上述，在本發明的導線架的設計中，引腳具有傾斜地連接頂面與底面的周圍表面，其中周圍表面包括平滑曲面、粗糙曲面或傾斜面。在後續所形成的半導體封裝結構中，引腳的形狀可提高與導電材料層的接合面積。此外，由於引腳的形狀是由外側向內側漸縮而形成一傾斜面或弧面，因此在外觀檢查上，可輕易檢查出引腳的底面是否有與外部電路接合在一起。簡言之，本發明的半導體封裝結構具有較佳的結構可靠度，可方便且快速地完成後續與外部電路接合後的外觀檢查。Based on the above, in the design of the lead frame of the present invention, the pins have a peripheral surface that obliquely connects the top surface and the bottom surface, wherein the peripheral surface includes a smooth curved surface, a rough curved surface or an inclined surface. In the subsequently formed semiconductor package structure, the shape of the lead can increase the bonding area with the conductive material layer. In addition, since the shape of the pin is tapered from the outside to the inside to form an inclined surface or an arc surface, it is easy to check whether the bottom surface of the pin is connected with the external circuit in the visual inspection. In short, the semiconductor package structure of the present invention has better structural reliability, and can easily and quickly complete the subsequent appearance inspection after bonding with the external circuit.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

以下將參考圖式來全面地描述本發明的例示性實施例，但本發明還可按照多種不同形式來實施，且不應解釋為限於本文所述的實施例。在圖式中，為了清楚起見，各區域、部位及層的大小與厚度可不按實際比例繪製。為了方便理解，下述說明中相同的元件將以相同之符號標示來說明，圖式繪製上為方便繪製及說明，主要是繪製成圓弧面。Exemplary embodiments of the present invention will be fully described below with reference to the accompanying drawings, but the present invention may also be embodied in many different forms and should not be construed as limited to the embodiments described herein. In the drawings, for the sake of clarity, the size and thickness of various regions, parts and layers may not be drawn to scale. For the convenience of understanding, the same elements in the following description will be described with the same symbols, and the drawings are mainly drawn as arc surfaces for the convenience of drawing and description.

圖1是本發明的一實施例的一種半導體封裝結構的剖面示意圖。請參照圖1，本實施例的半導體封裝結構10a包括一導線架100、一晶片200、一封裝膠體300、一導電材料層400以及多條導線700。導線架100包括一承載座110以及環繞承載座110的多個引腳（示意地繪示兩個引腳120）。此處，承載座110與引腳120的材質例如是相同，例如金屬或金屬合金，如銅或銅合金，但不以此為限。如圖1所示，導線架100的承載座110具有一底表面110b與相對底表面110b的一頂表面110a。晶片200配置於導線架100的承載座110上，且位於頂表面110a上，並與導線架100的多個引腳120電性連接。於本實施例中，電性連接的方式例如是以導線700為例，於其它可行的實施例中，亦可採用錫球、凸塊做為電性連接的途徑。此處，晶片200可藉由一黏著層（未繪示）而固定於承載座110的頂表面110a上，但不限於此。FIG. 1 is a schematic cross-sectional view of a semiconductor package structure according to an embodiment of the present invention. Referring to FIG. 1 , the semiconductor package structure 10 a of this embodiment includes a lead frame 100 , a chip 200 , an encapsulant 300 , a conductive material layer 400 and a plurality of wires 700 . The lead frame 100 includes a carrier 110 and a plurality of pins (two pins 120 are schematically shown) surrounding the carrier 110 . Here, the material of the bearing seat 110 and the pin 120 is, for example, the same, such as metal or metal alloy, such as copper or copper alloy, but not limited thereto. As shown in FIG. 1 , the carrier 110 of the lead frame 100 has a bottom surface 110b and a top surface 110a opposite to the bottom surface 110b. The chip 200 is disposed on the carrier 110 of the lead frame 100 and on the top surface 110 a , and is electrically connected to the plurality of pins 120 of the lead frame 100 . In this embodiment, the electrical connection method is, for example, the wire 700 . In other possible embodiments, solder balls and bumps can also be used as the electrical connection method. Here, the chip 200 may be fixed on the top surface 110a of the carrier 110 by an adhesive layer (not shown), but is not limited thereto.

再者，導線架100的每一引腳120具有彼此相對的一頂面120a與一底面120b以及一周圍表面120c。周圍表面120c傾斜地連接頂面120a與底面120b。特別是，每一引腳120的周圍表面120c由頂面120a兩外側向底面120b漸縮，最終形成例如是一平滑曲面、一粗糙曲面或一傾斜面。此處，周圍表面120c以平滑曲面進行繪示，但不以此為限。在製程上，可透過蝕刻程序來形成引腳120的底面120b及周圍表面120c，因此可避免刀具切割而產生金屬毛邊的問題，同時亦可增加引腳120的表面積及形成粗糙面。Furthermore, each lead 120 of the lead frame 100 has a top surface 120a, a bottom surface 120b and a peripheral surface 120c opposite to each other. The peripheral surface 120c obliquely connects the top surface 120a and the bottom surface 120b. In particular, the peripheral surface 120c of each pin 120 tapers from the two outer sides of the top surface 120a to the bottom surface 120b, and finally forms a smooth curved surface, a rough curved surface or an inclined surface. Here, the surrounding surface 120c is shown as a smooth curved surface, but not limited thereto. In the manufacturing process, the bottom surface 120b and the surrounding surface 120c of the lead 120 can be formed through an etching process, thereby avoiding the problem of metal burrs caused by tool cutting, and at the same time increasing the surface area of the lead 120 and forming a rough surface.

請再參考圖1，封裝膠體300覆蓋導線架100與晶片200，其中封裝膠體300與每一引腳120的周圍表面120c之間具有一容置空間S。也就是說，封裝膠體300沒有直接接觸引腳120的周圍表面120c。更進一步來說，封裝膠體300具有一第一下表面300b，而承載座110的底表面110b切齊於封裝膠體300的第一下表面300b。意即，封裝膠體300的第一下表面300b與承載座110的底表面110b實質上共平面，因此本實施例的半導體封裝結構10a可視為一種四方扁平無引腳（Quad flat no-lead, QFN）封裝結構。此處，封裝膠體300的材質例如是環氧樹脂或其他適合的封裝材料，但不限於此。Please refer to FIG. 1 again, the encapsulant 300 covers the lead frame 100 and the chip 200 , wherein an accommodating space S is formed between the encapsulant 300 and the peripheral surface 120 c of each lead 120 . That is, the encapsulant 300 does not directly contact the peripheral surface 120c of the lead 120 . More specifically, the encapsulant 300 has a first lower surface 300 b , and the bottom surface 110 b of the carrier 110 is aligned with the first lower surface 300 b of the encapsulant 300 . That is, the first lower surface 300b of the encapsulant 300 and the bottom surface 110b of the carrier 110 are substantially coplanar, so the semiconductor package structure 10a of this embodiment can be regarded as a quad flat no-lead (QFN) ) package structure. Here, the material of the encapsulant 300 is, for example, epoxy resin or other suitable encapsulation materials, but is not limited thereto.

再者，請再參考圖1，本實施例的導電材料層400至少包覆每一引腳120周緣以及部分的容置空間S。意即，導線架100的每一引腳120的周圍表面120c與底面120b包覆有導電材料層400，且導電材料層400部分填滿容置空間S，使得導電材料層400與傳統結構相較之下，不僅引腳周緣具有導電材料層400，且透過容置空間S聚集形成較多容量之導電材料層400，有助於後續迴焊接合。此處，導電材料層400的材質例如是金屬或金屬合金，如錫或錫合金，但不限於此。在製程上，可選擇地，可先行在引腳120的底部進行蝕刻，而形成粗糙面（如粗糙曲面），再以沾覆或印刷的方式而塗覆導電材料層400於引腳120的底面120b及周圍表面120c上。之後，在進行封裝程序，以封裝膠體300來包覆導線架100與晶片200，而形成底部預先形成沾覆導電材料層400的半導體封裝結構10a，導電材料層400是以沾覆方式為例，因此，引腳120於進行沾覆製程後，導電材料層400將部分包覆於引腳120周圍，並配合貼膜(Tape)貼覆於導線架100底部進行模封，由於導電材料層400佔據了一定的體積，而使得封裝膠體300對應導電材料層400體積而形成了一容置空間S，圖式繪製上為方便繪製及說明，主要是繪製成傾斜面，但不以此為限，實際上，該容置空間S是順應導電材料層400沾覆形狀而定，可為弧形或其它不規則形狀均可。於其它實施例中，導電材料層400亦可採用電鍍製程電鍍於引腳120表面，並不侷限於採用沾覆或印刷製程，因此容置空間S的形狀會隨著所採用之製程不同而有所改變，且附著於引腳120表面的外觀形狀亦會隨著採用之製程方式而有所不同。Furthermore, please refer to FIG. 1 again, the conductive material layer 400 of this embodiment at least covers the periphery of each lead 120 and a part of the accommodating space S. That is, the peripheral surface 120c and the bottom surface 120b of each lead 120 of the lead frame 100 are covered with the conductive material layer 400, and the conductive material layer 400 partially fills the accommodating space S, so that the conductive material layer 400 is compared with the conventional structure. Below, not only the conductive material layer 400 is provided on the periphery of the lead, but also the conductive material layer 400 with more capacity is formed through the accommodating space S, which is helpful for subsequent reflow bonding. Here, the material of the conductive material layer 400 is, for example, metal or metal alloy, such as tin or tin alloy, but not limited thereto. In the process, optionally, the bottom of the lead 120 may be etched to form a rough surface (eg, a rough surface), and then the conductive material layer 400 may be coated on the bottom of the lead 120 by dipping or printing. 120b and the surrounding surface 120c. After that, in the encapsulation process, the lead frame 100 and the chip 200 are covered with the encapsulant 300 to form the semiconductor package structure 10a with the conductive material layer 400 pre-formed at the bottom. Therefore, after the lead 120 is subjected to the dipping process, the conductive material layer 400 partially wraps around the lead 120, and is attached to the bottom of the lead frame 100 with the tape for molding. Since the conductive material layer 400 occupies A certain volume, so that the encapsulation colloid 300 corresponds to the volume of the conductive material layer 400 to form a accommodating space S, the drawing is mainly drawn as an inclined surface for the convenience of drawing and description, but not limited to this, in fact , the accommodating space S is determined according to the shape of the conductive material layer 400 , and may be an arc shape or other irregular shapes. In other embodiments, the conductive material layer 400 can also be electroplated on the surface of the lead 120 by an electroplating process, and is not limited to a dipping or printing process. Therefore, the shape of the accommodating space S will vary with the process used. The appearance and shape attached to the surface of the lead 120 will also be different according to the process method used.

此外，如圖1所示，本實施例的引腳120及包覆引腳120的導電材料層400皆沒有切齊於封裝膠體300的第一下表面300b。詳細來說，封裝膠體300的第一下表面300b與導電材料層400的一第二下表面400b之間具有一高度差H1。每一引腳120的底面120b與封裝膠體300的第一下表面之300b間具有一高度差H2。此處，高度差H1大於高度差H2。In addition, as shown in FIG. 1 , the lead 120 and the conductive material layer 400 covering the lead 120 in this embodiment are not aligned with the first lower surface 300 b of the encapsulant 300 . In detail, there is a height difference H1 between the first lower surface 300b of the encapsulant 300 and a second lower surface 400b of the conductive material layer 400 . There is a height difference H2 between the bottom surface 120b of each lead 120 and the first lower surface 300b of the encapsulant 300 . Here, the height difference H1 is larger than the height difference H2.

可選擇地，本實施例的半導體封裝結構10a可包括一導電覆層600，其中導電覆層600配置於每一引腳120的頂面120a上。此處，導電覆層600例如是一表面處理層，其材質例如是鎳、鈀、金及其組合，以保護引腳120的頂面120a，以及可供導線700電性連接於晶片200與位於每一引腳120上的導電覆層600上。Optionally, the semiconductor package structure 10 a of this embodiment may include a conductive cladding layer 600 , wherein the conductive cladding layer 600 is disposed on the top surface 120 a of each lead 120 . Here, the conductive coating 600 is, for example, a surface treatment layer, and its material is, for example, nickel, palladium, gold, or a combination thereof, so as to protect the top surface 120a of the lead 120 and allow the wires 700 to be electrically connected to the chip 200 and located on the chip 200 . On the conductive coating 600 on each lead 120 .

在本實施例的導線架100的設計中，引腳120具有傾斜地連接頂面120a與底面120b的周圍表面120c，其中周圍表面120c例如是平滑曲面、粗糙曲面或傾斜面。在後續所形成的半導體封裝結構10a中，導電材料層400除了可包覆引腳120的底面120b之外，還可以包覆引腳120的周圍表面120c，甚至可填滿位於封裝膠體300與周圍表面120c之間的容置空間S。如此一來，透過引腳120周緣的形狀為漸縮的設計，可提高與導電材料層400的接合面積。此外，由於引腳120的形狀為上自下漸縮設計，且封裝膠體300外側緣與引腳120上緣切齊，露出了引腳120周圍表面120c，因此在外觀檢查上，可輕易檢查出引腳120是否有與外部電路接合在一起。簡言之，本實施例的半導體封裝結構10a具有較佳的結構可靠度，可方便且快速地完成後續與外部電路接合後的外觀檢查。In the design of the lead frame 100 of the present embodiment, the pins 120 have a peripheral surface 120c obliquely connecting the top surface 120a and the bottom surface 120b, wherein the peripheral surface 120c is, for example, a smooth curved surface, a rough curved surface or an inclined surface. In the subsequently formed semiconductor package structure 10a, the conductive material layer 400 can not only cover the bottom surface 120b of the lead 120, but also cover the surrounding surface 120c of the lead 120, and can even fill the encapsulation compound 300 and the surrounding surface 120c. The accommodating space S between the surfaces 120c. In this way, the bonding area with the conductive material layer 400 can be increased through the tapered design of the peripheral edge of the lead 120 . In addition, since the shape of the lead 120 is tapered from top to bottom, and the outer edge of the encapsulating compound 300 is cut flush with the upper edge of the lead 120, the surrounding surface 120c of the lead 120 is exposed. Whether the pin 120 is connected with the external circuit. In short, the semiconductor package structure 10a of the present embodiment has better structural reliability, and can easily and quickly complete the subsequent appearance inspection after bonding with the external circuit.

在此必須說明的是，下述實施例沿用前述實施例的元件標號與部分內容，其中採用相同的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參照前述實施例，下述實施例不再重複贅述。It must be noted here that the following embodiments use the element numbers and part of the contents of the previous embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and repeated descriptions in the following embodiments will not be repeated.

圖2是本發明的另一實施例的一種半導體封裝結構的剖面示意圖。請同時參照圖1與圖2，本實施例的半導體封裝結構10b與圖1的半導體封裝結構10a相似，兩者的差異在於：本實施例的半導體封裝結構10b還包括一電路板500，例如是銅箔基板、BT基板、軟性基板(Polyimide film)、印刷電路板(PCB)等等。此處，電路板500的種類例如是單面板（Single sided board）、雙面板（Double sided board）或多層板（Multi layer board），但不限於此。電路板500包括至少一接墊（示意地繪示兩個接墊510）以及位於接墊510上的一銲料520。導線架100配置於電路板500上，其中每一引腳120透過導電材料層400及銲料520而電性連接至接墊510上。此處，接墊510的材質例如金屬或金屬合金，如銅或銅合金，但不以此為限。導電材料層400以及銲料520的材質例如是相同，例如是金屬或金屬合金，如錫或錫合金，但不以此為限。由於導電材料層400以及銲料520的材質可為相同，因此在導線架100與電路板500接合後，導電材料層400以及銲料520會融合為一銲料層，較佳地，導電材料層400以及銲料520所使用的材料可為相同材料，但不以此為限。此時，導電材料層400及銲料520將填滿整個容置空間S及引腳120周圍。2 is a schematic cross-sectional view of a semiconductor package structure according to another embodiment of the present invention. 1 and FIG. 2, the semiconductor package structure 10b of this embodiment is similar to the semiconductor package structure 10a of FIG. 1, the difference between the two is that the semiconductor package structure 10b of this embodiment further includes a circuit board 500, such as Copper foil substrate, BT substrate, flexible substrate (Polyimide film), printed circuit board (PCB), etc. Here, the type of the circuit board 500 is, for example, a single sided board, a double sided board, or a multi layer board, but is not limited thereto. The circuit board 500 includes at least one pad (two pads 510 are schematically shown) and a solder 520 on the pad 510 . The lead frame 100 is disposed on the circuit board 500 , wherein each pin 120 is electrically connected to the pad 510 through the conductive material layer 400 and the solder 520 . Here, the material of the pad 510 is, for example, metal or metal alloy, such as copper or copper alloy, but not limited thereto. The materials of the conductive material layer 400 and the solder 520 are, for example, the same, such as metals or metal alloys, such as tin or tin alloys, but not limited thereto. Since the materials of the conductive material layer 400 and the solder 520 can be the same, after the lead frame 100 and the circuit board 500 are joined together, the conductive material layer 400 and the solder 520 are fused into a solder layer. Preferably, the conductive material layer 400 and the solder The materials used in 520 can be the same materials, but not limited thereto. At this time, the conductive material layer 400 and the solder 520 will fill the entire accommodating space S and around the lead 120 .

由於本實施例的導線架100於引腳120的底面120b及周圍表面120c已有預先沾覆導電材料層400，因此可直接透過導電材料層400與電路板500電性連接。意即，引腳120透過導電材料層400及銲料520與電路板500的接墊510電性連接，因而使得導線架100固定且電性連接至電路板500上。由於引腳120的形狀為自上而下漸縮的設計，因此在外觀檢查上可輕易檢查出導電材料層400是否有電路板500上的銲料520接合在一起。另外，由於引腳120的外形是以蝕刻方式來形成，因此可避免刀具切割時所產生的金屬毛邊而造成短路的問題，進而可提高本實施例的半導體封裝結構10b的結構可靠度。再者，本實施例的半導體封裝結構10b與現有的四方扁平無引腳（Quad flat no-lead, QFN）封裝結構相較之下，本實施例的每一個引腳120都具有傾斜表面，可增加接合面積，有助於後續迴焊上板接合。Since the lead frame 100 of this embodiment has been pre-coated with the conductive material layer 400 on the bottom surface 120 b and the surrounding surface 120 c of the lead 120 , the conductive material layer 400 can be directly electrically connected to the circuit board 500 . That is, the pins 120 are electrically connected to the pads 510 of the circuit board 500 through the conductive material layer 400 and the solder 520 , so that the lead frame 100 is fixed and electrically connected to the circuit board 500 . Since the shape of the pins 120 is designed to be tapered from top to bottom, it can be easily checked whether the conductive material layer 400 is joined together by the solder 520 on the circuit board 500 in the visual inspection. In addition, since the shape of the lead 120 is formed by etching, the problem of short circuit caused by metal burrs generated when the tool is cut can be avoided, thereby improving the structural reliability of the semiconductor package structure 10b of the present embodiment. Furthermore, compared with the conventional quad flat no-lead (QFN) package structure of the semiconductor package structure 10b of the present embodiment, each lead 120 of the present embodiment has an inclined surface, which can Increase the bonding area to facilitate subsequent reflow on board bonding.

綜上所述，在本發明的導線架的設計中，引腳具有傾斜地連接頂面與底面的周圍表面，其中周圍表面包括平滑曲面、粗糙曲面或傾斜面。在後續所形成的半導體封裝結構中，引腳的形狀可提高與導電材料層的接合面積。此外，由於引腳的形狀為漸縮設計並不是傳統的矩形設計，因此在外觀檢查上，可輕易檢查出引腳是否有與外部電路接合在一起。簡言之，本發明的半導體封裝結構具有較佳的結構可靠度，可方便且快速地完成後續與外部電路接合後的外觀檢查。To sum up, in the design of the lead frame of the present invention, the pins have a peripheral surface that obliquely connects the top surface and the bottom surface, wherein the peripheral surface includes a smooth curved surface, a rough curved surface or an inclined surface. In the subsequently formed semiconductor package structure, the shape of the lead can increase the bonding area with the conductive material layer. In addition, since the shape of the pins is a tapered design instead of a traditional rectangular design, it is easy to check whether the pins are joined with an external circuit in the visual inspection. In short, the semiconductor package structure of the present invention has better structural reliability, and can easily and quickly complete the subsequent appearance inspection after bonding with the external circuit.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the appended patent application.

10a、10b:半導體封裝結構 100:導線架 110:承載座 110a:頂表面 110b:底表面 120:引腳 120a:頂面 120b:底面 120c:周圍表面 200:晶片 300:封裝膠體 300b:第一下表面 400:導電材料層 400b:第二下表面 500:電路板 510:接墊 520:銲料 600:導電覆層 700:導線 H1、H2:高度差 S:容置空間 10a, 10b: Semiconductor packaging structure 100: Lead frame 110: Bearing seat 110a: Top surface 110b: Bottom surface 120: pin 120a: top surface 120b: Bottom surface 120c: Surrounding surface 200: Wafer 300: encapsulating colloid 300b: First lower surface 400: Conductive material layer 400b: Second lower surface 500: circuit board 510: Pad 520: Solder 600: Conductive cladding 700: Wire H1, H2: height difference S: accommodating space

圖1是本發明的一實施例的一種半導體封裝結構的剖面示意圖。 圖2是本發明的另一實施例的一種半導體封裝結構的剖面示意圖。 FIG. 1 is a schematic cross-sectional view of a semiconductor package structure according to an embodiment of the present invention. 2 is a schematic cross-sectional view of a semiconductor package structure according to another embodiment of the present invention.

10a:半導體封裝結構 10a: Semiconductor package structure

100:導線架 100: Lead frame

110:承載座 110: Bearing seat

110a:頂表面 110a: Top surface

110b:底表面 110b: Bottom surface

120:引腳 120: pin

120a:頂面 120a: top surface

120b:底面 120b: Bottom surface

120c:周圍表面 120c: Surrounding surface

200:晶片 200: Wafer

300:封裝膠體 300: encapsulating colloid

300b:第一下表面 300b: First lower surface

400:導電材料層 400: Conductive material layer

400b:第二下表面 400b: Second lower surface

600:導電覆層 600: Conductive cladding

700:導線 700: Wire

H1、H2:高度差 H1, H2: height difference

S:容置空間 S: accommodating space

Claims (9)

一種半導體封裝結構，包括：一導線架，包括一承載座以及環繞該承載座的多個引腳，其中各該引腳具有彼此相對的一頂面與一底面以及傾斜地連接該頂面與該底面的一周圍表面，其中該周圍表面包括一平滑曲面、一粗糙曲面或一傾斜面，自該頂面兩外側向該底面漸縮；一晶片，配置於該導線架的該承載座上，並與該導線架的該些引腳電性連接；一封裝膠體，覆蓋該導線架與該晶片，其中該封裝膠體與各該引腳的該周圍表面之間具有一容置空間；以及一導電材料層，至少部分包覆各該引腳以及該容置空間。 A semiconductor package structure, comprising: a lead frame, including a bearing seat and a plurality of pins surrounding the bearing seat, wherein each of the pins has a top surface and a bottom surface opposite to each other and obliquely connects the top surface and the bottom surface a peripheral surface, wherein the peripheral surface includes a smooth curved surface, a rough curved surface or an inclined surface, which tapers from the two outer sides of the top surface to the bottom surface; a chip is disposed on the bearing seat of the lead frame, and is connected with The pins of the lead frame are electrically connected; an encapsulation compound covers the lead frame and the chip, wherein an accommodating space is formed between the encapsulation compound and the surrounding surface of each of the pins; and a conductive material layer , at least partially covering each of the pins and the accommodating space. 如請求項1所述的半導體封裝結構，更包括：一電路板，包括至少一接墊以及位於該至少一接墊上的一銲料，該導線架配置於該電路板上，其中各該引腳透過該導電材料層以及該銲料而電性連接至該至少一接墊。 The semiconductor package structure of claim 1, further comprising: a circuit board including at least one pad and a solder on the at least one pad, the lead frame is disposed on the circuit board, wherein each of the pins passes through The conductive material layer and the solder are electrically connected to the at least one pad. 如請求項1所述的半導體封裝結構，更包括：一導電覆層，配置於各該引腳的該頂面上。 The semiconductor package structure of claim 1, further comprising: a conductive coating layer disposed on the top surface of each of the pins. 如請求項3所述的半導體封裝結構，更包括：多條導線，電性連接於該晶片與位於各該引腳上的該導電覆層上。 The semiconductor package structure of claim 3, further comprising: a plurality of wires electrically connected to the chip and the conductive coating on each of the pins. 如請求項1所述的半導體封裝結構，其中該封裝膠體的一第一下表面與該導電材料層的一第二下表面之間具有一高度差。 The semiconductor package structure of claim 1, wherein a height difference is formed between a first lower surface of the encapsulating compound and a second lower surface of the conductive material layer. 如請求項1所述的半導體封裝結構，其中各該引腳的該底面與該封裝膠體的一第一下表面之間具有一高度差。 The semiconductor package structure of claim 1, wherein there is a height difference between the bottom surface of each of the pins and a first bottom surface of the packaging compound. 一種導線架，包括：一承載座；以及多個引腳，環繞該承載座，其中各該引腳具有彼此相對的一頂面與一底面以及傾斜地連接該頂面與該底面的一周圍表面，其中該周圍表面包括一平滑曲面、一粗糙曲面或一傾斜面，自該頂面兩外側向該底面漸縮。 A lead frame, comprising: a bearing seat; and a plurality of pins surrounding the bearing seat, wherein each of the pins has a top surface and a bottom surface opposite to each other and a surrounding surface obliquely connecting the top surface and the bottom surface, Wherein the surrounding surface includes a smooth curved surface, a rough curved surface or an inclined surface, which tapers from the outer sides of the top surface to the bottom surface. 如請求項7所述的導線架，其中各該引腳的該周圍表面與該底面的一外表面包覆有一導電材料層。 The lead frame of claim 7, wherein an outer surface of the peripheral surface and the bottom surface of each of the pins is covered with a conductive material layer. 如請求項7所述的導線架，其中各該引腳的該頂面設置有一導電覆層。 The lead frame of claim 7, wherein the top surface of each of the pins is provided with a conductive coating.
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5821608A (en) * 1995-09-08 1998-10-13 Tessera, Inc. Laterally situated stress/strain relieving lead for a semiconductor chip package
US20050093177A1 (en) * 2003-10-29 2005-05-05 Advanced Semiconductor Engineering, Inc. Semiconductor package, method for manufacturing the same and lead frame for use in the same
TW200707517A (en) * 2005-08-02 2007-02-16 Chipmos Technologies Inc Chip package having asymmetric molding
TW200814276A (en) * 2006-05-16 2008-03-16 Broadcom Corp No-lead IC packages having integrated heat spreader for electromagnetic interference (EMI) shielding and thermal enhancement
TW200818420A (en) * 2006-10-14 2008-04-16 Nat Applied Res Lab Nat Ct For High Performance Computing High brightness and heat dissipation light guidance structure of LED
TW200950045A (en) * 2008-05-30 2009-12-01 Powertech Technology Inc Lead frame package structure and manufacturing method thereof
WO2017188795A1 (en) * 2016-04-29 2017-11-02 엘지이노텍 주식회사 Phosphor composition, light-emitting device package including same, and lighting device
TW202042315A (en) * 2019-05-08 2020-11-16 力成科技股份有限公司 A package structure and a fabrication method thereof

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5821608A (en) * 1995-09-08 1998-10-13 Tessera, Inc. Laterally situated stress/strain relieving lead for a semiconductor chip package
US20050093177A1 (en) * 2003-10-29 2005-05-05 Advanced Semiconductor Engineering, Inc. Semiconductor package, method for manufacturing the same and lead frame for use in the same
TW200707517A (en) * 2005-08-02 2007-02-16 Chipmos Technologies Inc Chip package having asymmetric molding
TW200814276A (en) * 2006-05-16 2008-03-16 Broadcom Corp No-lead IC packages having integrated heat spreader for electromagnetic interference (EMI) shielding and thermal enhancement
TW200818420A (en) * 2006-10-14 2008-04-16 Nat Applied Res Lab Nat Ct For High Performance Computing High brightness and heat dissipation light guidance structure of LED
TW200950045A (en) * 2008-05-30 2009-12-01 Powertech Technology Inc Lead frame package structure and manufacturing method thereof
WO2017188795A1 (en) * 2016-04-29 2017-11-02 엘지이노텍 주식회사 Phosphor composition, light-emitting device package including same, and lighting device
TW202042315A (en) * 2019-05-08 2020-11-16 力成科技股份有限公司 A package structure and a fabrication method thereof

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