DE10110157B4 - Halbleitervorrichtung mit verringertem Stromverbrauch im Standby-Zustand - Google Patents

Halbleitervorrichtung mit verringertem Stromverbrauch im Standby-Zustand Download PDF

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Publication number
DE10110157B4
DE10110157B4 DE10110157A DE10110157A DE10110157B4 DE 10110157 B4 DE10110157 B4 DE 10110157B4 DE 10110157 A DE10110157 A DE 10110157A DE 10110157 A DE10110157 A DE 10110157A DE 10110157 B4 DE10110157 B4 DE 10110157B4
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Germany
Prior art keywords
signal
circuit
power supply
address
refresh
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE10110157A
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German (de)
English (en)
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DE10110157A1 (de
Inventor
Tsukasa Ooishi
Takaharu Tsuji
Masatoshi Ishikawa
Hideto Hidaka
Hiroshi Kato
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Publication date
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Publication of DE10110157A1 publication Critical patent/DE10110157A1/de
Application granted granted Critical
Publication of DE10110157B4 publication Critical patent/DE10110157B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40622—Partial refresh of memory arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4067—Refresh in standby or low power modes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Logic Circuits (AREA)
DE10110157A 2000-05-24 2001-03-02 Halbleitervorrichtung mit verringertem Stromverbrauch im Standby-Zustand Expired - Fee Related DE10110157B4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000-152651 2000-05-24
JP2000152651A JP2001338489A (ja) 2000-05-24 2000-05-24 半導体装置

Publications (2)

Publication Number Publication Date
DE10110157A1 DE10110157A1 (de) 2001-11-29
DE10110157B4 true DE10110157B4 (de) 2005-04-14

Family

ID=18658046

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10110157A Expired - Fee Related DE10110157B4 (de) 2000-05-24 2001-03-02 Halbleitervorrichtung mit verringertem Stromverbrauch im Standby-Zustand

Country Status (4)

Country Link
US (3) US6414894B2 (enExample)
JP (1) JP2001338489A (enExample)
KR (1) KR100408615B1 (enExample)
DE (1) DE10110157B4 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006043456A1 (de) * 2006-09-15 2008-03-27 Qimonda Ag Verfahren zum Auffrischen des Inhalts einer Speicherzelle einer Speicheranordnung sowie entsprechende Speicheranordnung

Families Citing this family (103)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000070621A1 (fr) * 1999-05-14 2000-11-23 Hitachi, Ltd. Dispositif a circuit integre a semi-conducteurs
JP3534681B2 (ja) * 2000-06-01 2004-06-07 松下電器産業株式会社 半導体記憶装置
US7733069B2 (en) 2000-09-29 2010-06-08 Canon Kabushiki Kaisha Power converting apparatus and power generating apparatus
US6449203B1 (en) * 2001-03-08 2002-09-10 Micron Technology, Inc. Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs
KR100421904B1 (ko) * 2001-03-21 2004-03-10 주식회사 하이닉스반도체 반도체 소자의 리프래쉬 회로
US6590822B2 (en) * 2001-05-07 2003-07-08 Samsung Electronics Co., Ltd. System and method for performing partial array self-refresh operation in a semiconductor memory device
JP2002373489A (ja) * 2001-06-15 2002-12-26 Mitsubishi Electric Corp 半導体記憶装置
JP2003068076A (ja) * 2001-08-27 2003-03-07 Elpida Memory Inc 半導体記憶装置の電力制御方法及び半導体記憶装置
US6771553B2 (en) 2001-10-18 2004-08-03 Micron Technology, Inc. Low power auto-refresh circuit and method for dynamic random access memories
US6751159B2 (en) * 2001-10-26 2004-06-15 Micron Technology, Inc. Memory device operable in either a high-power, full-page size mode or a low-power, reduced-page size mode
US6807122B2 (en) * 2001-11-14 2004-10-19 Hitachi, Ltd. Semiconductor memory device requiring refresh
US6838331B2 (en) * 2002-04-09 2005-01-04 Micron Technology, Inc. Method and system for dynamically operating memory in a power-saving error correction mode
US6751143B2 (en) * 2002-04-11 2004-06-15 Micron Technology, Inc. Method and system for low power refresh of dynamic random access memories
KR100452319B1 (ko) * 2002-05-10 2004-10-12 삼성전자주식회사 반도체 메모리 장치의 내부전원전압 발생회로 및내부전원전압 제어방법
US6731548B2 (en) * 2002-06-07 2004-05-04 Micron Technology, Inc. Reduced power registered memory module and method
JP4041358B2 (ja) * 2002-07-04 2008-01-30 富士通株式会社 半導体メモリ
US7149824B2 (en) 2002-07-10 2006-12-12 Micron Technology, Inc. Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction
KR100881815B1 (ko) * 2002-07-12 2009-02-03 주식회사 하이닉스반도체 반도체 메모리 장치
KR100506057B1 (ko) * 2002-07-15 2005-08-03 주식회사 하이닉스반도체 부분 어레이 셀프 리프레시를 수행하는 반도체 메모리 장치
US7002867B2 (en) * 2002-09-25 2006-02-21 Infineon Technologies Aktiengesellschaft Refresh control circuit for ICs with a memory array
JP4747155B2 (ja) * 2002-10-29 2011-08-17 ルネサスエレクトロニクス株式会社 メモリ制御システム
KR100557590B1 (ko) * 2002-12-26 2006-03-03 주식회사 하이닉스반도체 반도체 메모리 장치의 오토 리프레시 제어회로
US7039818B2 (en) * 2003-01-22 2006-05-02 Texas Instruments Incorporated Low leakage SRAM scheme
JP4184104B2 (ja) 2003-01-30 2008-11-19 株式会社ルネサステクノロジ 半導体装置
JP2004259343A (ja) 2003-02-25 2004-09-16 Renesas Technology Corp 半導体記憶装置
KR100524950B1 (ko) * 2003-02-28 2005-11-01 삼성전자주식회사 전류 소모를 줄이는 인터페이싱 회로
US6765433B1 (en) * 2003-03-20 2004-07-20 Atmel Corporation Low power implementation for input signals of integrated circuits
KR100591759B1 (ko) * 2003-12-03 2006-06-22 삼성전자주식회사 반도체 메모리의 전원 공급장치
KR100596434B1 (ko) * 2003-12-29 2006-07-05 주식회사 하이닉스반도체 레이아웃 면적을 줄일 수 있는 반도체 메모리 장치
US7342841B2 (en) * 2004-12-21 2008-03-11 Intel Corporation Method, apparatus, and system for active refresh management
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US7580312B2 (en) 2006-07-31 2009-08-25 Metaram, Inc. Power saving system and method for use with a plurality of memory circuits
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US7590796B2 (en) 2006-07-31 2009-09-15 Metaram, Inc. System and method for power management in memory systems
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US7386656B2 (en) 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US7609567B2 (en) 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
US7392338B2 (en) 2006-07-31 2008-06-24 Metaram, Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
WO2007002324A2 (en) * 2005-06-24 2007-01-04 Metaram, Inc. An integrated memory core and memory interface circuit
US7472220B2 (en) 2006-07-31 2008-12-30 Metaram, Inc. Interface circuit system and method for performing power management operations utilizing power management signals
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
KR100725362B1 (ko) 2005-07-11 2007-06-07 삼성전자주식회사 동적 메모리 장치 및 이를 포함하는 통신 단말기
JP2007066463A (ja) * 2005-09-01 2007-03-15 Renesas Technology Corp 半導体装置
GB2444663B (en) 2005-09-02 2011-12-07 Metaram Inc Methods and apparatus of stacking drams
US7385858B2 (en) * 2005-11-30 2008-06-10 Mosaid Technologies Incorporated Semiconductor integrated circuit having low power consumption with self-refresh
US7362640B2 (en) * 2005-12-29 2008-04-22 Mosaid Technologies Incorporated Apparatus and method for self-refreshing dynamic random access memory cells
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
KR100776737B1 (ko) * 2006-02-10 2007-11-19 주식회사 하이닉스반도체 반도체 메모리의 액티브 싸이클 제어장치 및 방법
KR100810060B1 (ko) 2006-04-14 2008-03-05 주식회사 하이닉스반도체 반도체 메모리 소자 및 그의 구동방법
KR100776747B1 (ko) * 2006-05-09 2007-11-19 주식회사 하이닉스반도체 반도체 메모리 장치의 로우 어드레스 제어 회로 및 방법
JP4272227B2 (ja) * 2006-06-16 2009-06-03 三洋電機株式会社 メモリおよび制御装置
KR100780624B1 (ko) * 2006-06-29 2007-11-29 주식회사 하이닉스반도체 반도체 메모리 장치 및 그 구동방법
US20080028135A1 (en) * 2006-07-31 2008-01-31 Metaram, Inc. Multiple-component memory interface system and method
US7724589B2 (en) 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
US20080025136A1 (en) * 2006-07-31 2008-01-31 Metaram, Inc. System and method for storing at least a portion of information received in association with a first operation for use in performing a second operation
JP4832232B2 (ja) * 2006-09-20 2011-12-07 パナソニック株式会社 半導体集積回路装置及び電子装置
US7733731B2 (en) 2007-03-05 2010-06-08 Micron Technology, Inc. Control of inputs to a memory device
JP2009009680A (ja) * 2007-05-25 2009-01-15 Nec Electronics Corp 半導体装置
US7692978B2 (en) 2007-05-25 2010-04-06 Nec Electronics Corporation Semiconductor device that uses a plurality of source voltages
US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
KR100880316B1 (ko) * 2007-07-25 2009-01-28 주식회사 하이닉스반도체 메모리 소자 및 그 독출 방법
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
JP5168471B2 (ja) * 2008-02-05 2013-03-21 ルネサスエレクトロニクス株式会社 半導体装置
WO2010039896A2 (en) * 2008-10-01 2010-04-08 Altera Corporation Volatile memory elements with soft error upset immunity
KR100974225B1 (ko) * 2008-12-23 2010-08-06 주식회사 하이닉스반도체 임피던스 조정 주기 설정회로 및 반도체 집적회로
JP5599977B2 (ja) * 2009-01-22 2014-10-01 ピーエスフォー ルクスコ エスエイアールエル 半導体記憶装置
DE202010017690U1 (de) 2009-06-09 2012-05-29 Google, Inc. Programmierung von Dimm-Abschlusswiderstandswerten
WO2012115839A1 (en) 2011-02-23 2012-08-30 Rambus Inc. Protocol for memory power-mode control
KR101926604B1 (ko) 2012-02-27 2018-12-07 삼성전자 주식회사 스탠바이 모드 바디 바이어스 제어 방법 및 이를 이용한 반도체 장치
KR101980162B1 (ko) * 2012-06-28 2019-08-28 에스케이하이닉스 주식회사 메모리
JP5867464B2 (ja) * 2013-08-06 2016-02-24 コニカミノルタ株式会社 情報処理装置及びリフレッシュ制御プログラム並びにリフレッシュ制御方法
KR20170045795A (ko) * 2015-10-20 2017-04-28 삼성전자주식회사 메모리 장치 및 이를 포함하는 메모리 시스템
WO2017099811A1 (en) 2015-12-11 2017-06-15 Hewlett-Packard Development Company, L.P. Collapsible container and sensor
US10332582B2 (en) 2017-08-02 2019-06-25 Qualcomm Incorporated Partial refresh technique to save memory refresh power
JP2019053444A (ja) * 2017-09-13 2019-04-04 東芝メモリ株式会社 半導体集積回路及び半導体装置
US11838020B1 (en) 2017-12-26 2023-12-05 SK Hynix Inc. Semiconductor memory device including write driver with power gating structures and operating method thereof
US11100962B2 (en) 2017-12-26 2021-08-24 SK Hynix Inc. Semiconductor device with a power-down mode and a power gating circuit and semiconductor system including the same
US10943626B1 (en) 2017-12-26 2021-03-09 SK Hynix Inc. Semiconductor memory device with power gating circuit for data input-output control block and data input/output block and semiconductor system including the same
KR20200033690A (ko) * 2018-09-20 2020-03-30 에스케이하이닉스 주식회사 파워다운모드를 제공하는 반도체장치 및 이를 사용하여 파워다운모드를 제어하는 방법
US11295803B2 (en) * 2019-08-30 2022-04-05 Qualcomm Incorporated Memory with dynamic voltage scaling
KR102791225B1 (ko) 2020-05-07 2025-04-07 에스케이하이닉스 주식회사 클럭 생성을 제어하는 전자장치
US11495276B2 (en) 2020-05-07 2022-11-08 SK Hynix Inc. Electronic devices for controlling clock generation
KR102749604B1 (ko) * 2020-09-24 2025-01-02 에스케이하이닉스 주식회사 파워게이팅동작을 수행하는 장치
KR20240117196A (ko) 2023-01-25 2024-08-01 삼성전자주식회사 클럭 드라이버, 이의 동작 방법, 클럭 드라이버를 포함하는 메모리 장치, 및 메모리 시스템

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5615162A (en) * 1995-01-04 1997-03-25 Texas Instruments Incorporated Selective power to memory
EP0820065A2 (en) * 1996-07-15 1998-01-21 Motorola, Inc. Dynamic memory device with refresh circuit and refresh method

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59162690A (ja) * 1983-03-04 1984-09-13 Nec Corp 擬似スタテイツクメモリ
JPS6055593A (ja) * 1983-09-06 1985-03-30 Nec Corp 擬似スタティックメモリ
JPS61105795A (ja) * 1984-10-29 1986-05-23 Nec Corp メモリ回路
JP2534757B2 (ja) * 1988-07-06 1996-09-18 株式会社東芝 リフレッシュ回路
US5113373A (en) * 1990-08-06 1992-05-12 Advanced Micro Devices, Inc. Power control circuit
AU8908691A (en) 1990-10-12 1992-05-20 Intel Corporation Slow memory refresh in a computer with a limited supply of power
JP3034362B2 (ja) * 1990-11-22 2000-04-17 株式会社日立製作所 周辺制御装置およびｓｃｓｉバス制御装置
US5262998A (en) * 1991-08-14 1993-11-16 Micron Technology, Inc. Dynamic random access memory with operational sleep mode
US5365487A (en) 1992-03-24 1994-11-15 Texas Instruments Incorporated DRAM power management with self-refresh
JP3152758B2 (ja) * 1992-09-21 2001-04-03 富士通株式会社 ダイナミック型半導体記憶装置
JPH06168588A (ja) * 1992-11-30 1994-06-14 Hitachi Ltd 半導体記憶装置
JPH0773146A (ja) * 1993-06-28 1995-03-17 Casio Comput Co Ltd 電子機器
US5345424A (en) * 1993-06-30 1994-09-06 Intel Corporation Power-up reset override architecture and circuit for flash memory
JP2838967B2 (ja) * 1993-12-17 1998-12-16 日本電気株式会社 同期型半導体装置用パワーカット回路
JP3607407B2 (ja) * 1995-04-26 2005-01-05 株式会社日立製作所 半導体記憶装置
KR0164395B1 (ko) * 1995-09-11 1999-02-18 김광호 반도체 메모리 장치와 그 리이드 및 라이트 방법
JPH09147553A (ja) * 1995-11-22 1997-06-06 Fujitsu Ltd 半導体記憶装置
JP3319960B2 (ja) * 1996-10-17 2002-09-03 富士通株式会社 半導体装置
US5835401A (en) * 1996-12-05 1998-11-10 Cypress Semiconductor Corporation Dram with hidden refresh
JPH1186537A (ja) * 1997-09-03 1999-03-30 Nec Corp Ｄｒａｍ装置
KR100269313B1 (ko) * 1997-11-07 2000-12-01 윤종용 대기시전류소모가적은반도체메모리장치
JPH11306752A (ja) 1998-04-27 1999-11-05 Nec Corp Ｄｒａｍ混載電子回路装置
JP2000173263A (ja) * 1998-12-04 2000-06-23 Mitsubishi Electric Corp 半導体記憶装置
JP3420120B2 (ja) * 1999-06-29 2003-06-23 日本電気株式会社 同期型半導体メモリシステム

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5615162A (en) * 1995-01-04 1997-03-25 Texas Instruments Incorporated Selective power to memory
EP0820065A2 (en) * 1996-07-15 1998-01-21 Motorola, Inc. Dynamic memory device with refresh circuit and refresh method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006043456A1 (de) * 2006-09-15 2008-03-27 Qimonda Ag Verfahren zum Auffrischen des Inhalts einer Speicherzelle einer Speicheranordnung sowie entsprechende Speicheranordnung
DE102006043456B4 (de) * 2006-09-15 2010-04-08 Qimonda Ag Verfahren zum Auffrischen des Inhalts einer Speicherzelle einer Speicheranordnung sowie entsprechende Speicheranordnung

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JP2001338489A (ja) 2001-12-07
US20010045579A1 (en) 2001-11-29
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US6414894B2 (en) 2002-07-02
DE10110157A1 (de) 2001-11-29

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