JP2001338489A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JP2001338489A
JP2001338489A JP2000152651A JP2000152651A JP2001338489A JP 2001338489 A JP2001338489 A JP 2001338489A JP 2000152651 A JP2000152651 A JP 2000152651A JP 2000152651 A JP2000152651 A JP 2000152651A JP 2001338489 A JP2001338489 A JP 2001338489A
Authority
JP
Japan
Prior art keywords
circuit
power supply
address
signal
refresh
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000152651A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001338489A5 (enExample
Inventor
Tsukasa Oishi
司 大石
Takaharu Tsuji
高晴 辻
Masatoshi Ishikawa
正敏 石川
Hideto Hidaka
秀人 日高
Hiroshi Kato
宏 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2000152651A priority Critical patent/JP2001338489A/ja
Priority to US09/778,062 priority patent/US6414894B2/en
Priority to DE10110157A priority patent/DE10110157B4/de
Priority to KR10-2001-0019955A priority patent/KR100408615B1/ko
Publication of JP2001338489A publication Critical patent/JP2001338489A/ja
Priority to US10/167,437 priority patent/US6597617B2/en
Priority to US10/607,259 priority patent/US6868029B2/en
Publication of JP2001338489A5 publication Critical patent/JP2001338489A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40622—Partial refresh of memory arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4067—Refresh in standby or low power modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Logic Circuits (AREA)
JP2000152651A 2000-05-24 2000-05-24 半導体装置 Pending JP2001338489A (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2000152651A JP2001338489A (ja) 2000-05-24 2000-05-24 半導体装置
US09/778,062 US6414894B2 (en) 2000-05-24 2001-02-07 Semiconductor device with reduced current consumption in standby state
DE10110157A DE10110157B4 (de) 2000-05-24 2001-03-02 Halbleitervorrichtung mit verringertem Stromverbrauch im Standby-Zustand
KR10-2001-0019955A KR100408615B1 (ko) 2000-05-24 2001-04-13 스탠바이시에 소비 전류를 삭감 가능한 반도체 장치
US10/167,437 US6597617B2 (en) 2000-05-24 2002-06-13 Semiconductor device with reduced current consumption in standby state
US10/607,259 US6868029B2 (en) 2000-05-24 2003-06-27 Semiconductor device with reduced current consumption in standby state

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000152651A JP2001338489A (ja) 2000-05-24 2000-05-24 半導体装置

Publications (2)

Publication Number Publication Date
JP2001338489A true JP2001338489A (ja) 2001-12-07
JP2001338489A5 JP2001338489A5 (enExample) 2007-06-07

Family

ID=18658046

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000152651A Pending JP2001338489A (ja) 2000-05-24 2000-05-24 半導体装置

Country Status (4)

Country Link
US (3) US6414894B2 (enExample)
JP (1) JP2001338489A (enExample)
KR (1) KR100408615B1 (enExample)
DE (1) DE10110157B4 (enExample)

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KR20030009125A (ko) * 2001-06-15 2003-01-29 미쓰비시덴키 가부시키가이샤 반도체 기억 장치
US6819618B2 (en) 2003-02-25 2004-11-16 Renesas Technology Corp. Semiconductor memory device capable of executing refresh operation according to refresh space
JP2006500711A (ja) * 2002-09-25 2006-01-05 インフィネオン　テヒノロギーズ　アーゲー メモリ・アレイを有するｉｃ用更新制御回路
US6992946B2 (en) 2003-01-30 2006-01-31 Renesas Technology Corp. Semiconductor device with reduced current consumption in standby state
JP2007066463A (ja) * 2005-09-01 2007-03-15 Renesas Technology Corp 半導体装置
JP2008071371A (ja) * 2002-10-29 2008-03-27 Renesas Technology Corp メモリ制御システム
JP2008078892A (ja) * 2006-09-20 2008-04-03 Matsushita Electric Ind Co Ltd 半導体集積回路装置及び電子装置
US7460428B2 (en) 2005-07-11 2008-12-02 Samsung Electronics Co., Ltd. Dynamic random access memory and communications terminal including the same
JP2009009680A (ja) * 2007-05-25 2009-01-15 Nec Electronics Corp 半導体装置
US7692978B2 (en) 2007-05-25 2010-04-06 Nec Electronics Corporation Semiconductor device that uses a plurality of source voltages

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KR101980162B1 (ko) * 2012-06-28 2019-08-28 에스케이하이닉스 주식회사 메모리
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KR20200033690A (ko) * 2018-09-20 2020-03-30 에스케이하이닉스 주식회사 파워다운모드를 제공하는 반도체장치 및 이를 사용하여 파워다운모드를 제어하는 방법
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KR102791225B1 (ko) 2020-05-07 2025-04-07 에스케이하이닉스 주식회사 클럭 생성을 제어하는 전자장치
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KR102749604B1 (ko) * 2020-09-24 2025-01-02 에스케이하이닉스 주식회사 파워게이팅동작을 수행하는 장치
KR20240117196A (ko) 2023-01-25 2024-08-01 삼성전자주식회사 클럭 드라이버, 이의 동작 방법, 클럭 드라이버를 포함하는 메모리 장치, 및 메모리 시스템

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US20010045579A1 (en) 2001-11-29
DE10110157B4 (de) 2005-04-14
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US20040027902A1 (en) 2004-02-12
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