CN1452244A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN1452244A
CN1452244A CN03130796A CN03130796A CN1452244A CN 1452244 A CN1452244 A CN 1452244A CN 03130796 A CN03130796 A CN 03130796A CN 03130796 A CN03130796 A CN 03130796A CN 1452244 A CN1452244 A CN 1452244A
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China
Prior art keywords
film
insulating barrier
wiring layer
wiring
semiconductor device
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CN03130796A
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English (en)
Inventor
田中顺
大谷美晴
尾形洁
铃木康道
堀田胜彦
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Hitachi Ltd
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Hitachi Ltd
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Publication of CN1452244A publication Critical patent/CN1452244A/zh
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Abstract

提供一种半导体器件，可防止元件整体的机械强度下降，减少沿布线传播的信号的延迟。构成各布线层(100)的第一绝缘层和第三绝缘层包含碳化氮化硅膜、碳化硅和/或氧化硅，下层布线层的第二绝缘层包含氧化硅，上层布线层的第二绝缘层包含添加氟的氧化硅和/或添加碳的氧化硅。使下层布线层的第二绝缘层的介电常数比上层布线层的第二绝缘层的介电常数小。

Description

半导体器件
技术领域
本发明涉及通过将具有低介电常数特性的绝缘膜用作层间绝缘膜来降低信号布线延迟，从而提高元件性能的半导体器件。
背景技术
随着半导体元件的高集成化和芯片尺寸的缩小，布线正逐渐微细化、窄间距化和多层化。随之，有信号通过布线传输时的延迟时间，即布线延迟增加的倾向，在使用其中采用半导体元件的电子设备时成为大问题。
一般来说，通过布线传输的信号的速度取决于布线电阻(R)和布线间的电容(C)之积(RC)，因而为了减少布线延迟，需要降低布线电阻，或减小布线间电容，即进行层间绝缘膜的低介电常数化。
对于降低布线电阻，在高性能的半导体元件中，采用布线材料由铝替换为铜，特别是在将铜布线埋入层间绝缘膜层的镶嵌结构的工艺应用中使用普遍。
此外，对于层间绝缘膜的低介电常数化，以往，就半导体器件的层间绝缘膜而言，使用通过CVD(化学汽相淀积：Chemical Vapor Deposition)法成膜的氧化硅(SiO2：介电常数为7.0左右)或氮化硅(Si-N：介电常数为4.0左右)等无机类材料。作为可沿袭以往工艺的低介电常数材料，最近，相继采用了添加氟的氧化硅膜(Si-O-F：介电常数为3.6左右)。
但是，添加氟的氧化硅膜的介电常数较高，将其作为层间绝缘膜使用时，由于降低层间电容的效果不够，因此在布线工艺达到90nm节点代之后的半导体器件中，需要具有更低介电常数的材料。
作为具有介电常数低于3.5的特性的层间绝缘膜材料，已提出各种材料，大致进行区分，目前正在研究在衬底上涂敷后通过加热形成膜的所谓旋涂玻璃材料或同样成膜形成的有机类材料，用CVD法成膜形成的方法。
作为旋涂玻璃材料，可举出包含硅倍半环氧乙烷氢(HydrogenSilsesquioxane)化合物或硅倍半环氧乙烷甲基(Methyl Silsesquioxane)化合物的材料。最好是包含以硅倍半环氧乙烷氢化合物或硅倍半环氧乙烷甲基化合物为主成份的材料。再有，在本说明书中，所谓主成份，指配比(摩尔比)最高的成份。
以硅倍半环氧乙烷氢化合物作为主要成分的涂敷溶液是使以通式(HSiO3/2)n表示的化合物溶解于甲基异丁脂甲酮等溶剂中的溶液。在衬底上涂敷该溶液，在100-250℃左右的温度下中间加热之后，在氮气气氛等惰性气体气氛内以350-450℃的温度加热，以梯形结构形成Si-O-Si键，最终形成以SiO为主成份的绝缘膜。
以硅倍半环氧乙烷甲基化合物作为主要成分的涂敷溶液是使以通式(CH3SiO3/2)n表示的化合物溶解于甲基异丁脂甲酮等溶剂中的溶液。在衬底上涂敷该溶液，在100-250℃左右的温度下中间加热之后，在氮气气氛等惰性气体气氛内以350-450℃的温度加热，以梯形结构形成Si-O-Si键，最终形成以SiO为主成份的绝缘膜。
作为有机绝缘膜材料，已知碳化氢类树脂的聚酰亚胺、聚对二甲苯、聚丙炔乙醚、聚丙炔、苯基环丁烷、聚萘等高分子材料。这些材料包含碳原子，因而使膜的密度降低，并且分子(单体)本身的极化率小，因而实现了低介电常数。
作为进一步降低上述那样的旋涂玻璃膜、有机膜、CVD膜之类的层间绝缘膜的介电常数的方法，已知在膜中形成微小空隙的多孔膜。有关上述材料或工艺，已在“International Technology Roadmap for Semiconductors”(1999年编)第163-186页，特开2000-340569号公报、特开2001-274239号公报中公开。
可是，在上述现有技术中，与CVD成膜的氧化硅膜或氮化硅膜相比，具有介电常数低于3.5的特性的层间绝缘膜存在其绝缘膜硬度和杨氏模量之类的机械强度实质上偏低那样的问题。
在这样的绝缘膜中，为了进一步降低介电常数，在膜中形成微小空隙来多孔化，这在使机械强度更加劣化方面，不具有现实意义。
作为降低绝缘膜的介电常数的方法，有时使用聚酰亚胺等具有绝缘性的有机聚合物。有机聚合物由于其介电常数低于4，因而在这点上较好，但与无机膜相比，存在物理机械强度较低，并且吸湿性或透湿性高的缺点。此外，作为层间绝缘膜使用时，元件结构的机械强度低和因吸湿水分而刻蚀布线等，因而在元件的可靠性上会出现问题。
[非专利文献1]
“International Technology Roadmap for Semiconductors“(1999年编)第163-186页
[专利文献1]
特开2000-340569号公报
[专利文献2]
特开2001-274239号公报
因此，特别是在采用将降低了布线电阻的铜布线埋入层间绝缘膜层中的镶嵌结构的多层布线半导体元件中，正在研究既可抑制元件结构的机械强度低同时又使层间绝缘膜整体的介电常数降低的方法。
发明内容
本发明在上述技术背景下，提出以下方法，实施上述那样的低介电常数的膜和高介电常数的膜的层叠结构，并且，使各种材料的组合或结构最佳化，由此实现绝缘膜本身的电特性和机械特性的兼顾。
特别是，在采用将降低了布线电阻的铜布线埋入层间绝缘膜层中的镶嵌结构的层叠结构的半导体器件中，可实现如下的半导体器件：既可抑制层间绝缘膜的机械强度降低，同时又可尽可能减小通过布线传输的信号的延迟，从而高可靠地具有高性能的特性。
本发明的半导体器件，在形成了晶体管元件和半导体电路部的衬底上，层叠多层布线层而形成，该布线层包括第一绝缘层、第二绝缘层、第三绝缘层、以及贯通这三层而形成的导体布线。此时，构成各布线层的第一和第三绝缘层由碳化氮化硅膜、碳化硅或氧化硅构成，而布线层中，位于下层部的布线层的第二绝缘层包含氧化硅，位于上层部的布线层的第二绝缘层包含添加氟的氧化硅或添加碳的氧化硅。
此时，作为导体布线，在将铜布线作为构成要素的情况下，第一绝缘膜成为为了埋入铜布线而将绝缘膜开口时的刻蚀停止膜。而第三绝缘层成为铜布线的扩散阻挡膜。
以往，刻蚀停止膜和扩散阻挡膜使用氮化硅膜，在本发明中，使用由介电常数比氮化硅膜低的碳化氮化硅膜(Si-C-N：介电常数4.6左右)、碳化硅(Si-C：介电常数4.4左右)或氧化硅构成的膜，所以在形成了多层层叠结构的布线层整体中，也可以降低其介电常数。
在布线层中，通过将位于上层部的布线层的第二绝缘层形成为介电常数比氧化硅膜小的添加氟的氧化硅膜或添加碳的氧化硅膜(介电常数2.9左右)，与构成布线层的所有第二绝缘层为氧化硅的情况相比，可以降低布线层整体的介电常数。
此外，本发明的半导体器件中，位于下层部的布线层的第二绝缘层由介电常数低于3.0的绝缘膜材料构成，位于上层部的布线层的第二绝缘层由添加了氟的氧化硅膜或添加了碳的氧化硅膜构成。即，第二绝缘层的构成成分在位于上层部的布线层和位于下层部的布线层中有所不同，与前者比较，后者的绝缘膜的介电常数变小了。
此外，本发明的半导体器件中，位于下层部的布线层的第二绝缘层具有介电常数低于3.0的特性，是含有SiO的绝缘膜，并且绝缘膜中存在的微小空隙的半数以上具有0.05nm以上、4nm以下的直径。在本发明中，期望微小空隙的主要结构为直径0.05nm以上、4nm以下。在本发明中，通过在膜中有微小空隙，来降低膜的密度，通过使用含有作为单膜的介电常数小到低于3.0的SiO的绝缘膜，可在多层层叠结构的布线层整体中进一步降低介电常数。
此时，通过采用在绝缘膜中形成微小的空隙使密度降低，并接近于真空的介电常数的方法，使绝缘膜的介电常数比氧化硅膜的介电常数低，特别是通过控制该微小空隙的尺寸和密度，可以形成具有任意的介电常数的绝缘膜。
但是，如果微小空隙的直径增大，则作为绝缘膜自身结构体的机械强度下降，或流过绝缘膜的漏泄电流增大，产生作为绝缘膜特征的绝缘耐压下降等新问题，所以就绝缘膜中含有的空隙的尺寸来说，需要十分注意。
因此，在本发明中，通过控制空隙直径的范围，来抑制绝缘膜的机械强度和绝缘耐压的下降。此时，在微小空隙的半数以上有0.05nm以上、4nm以下的直径时，可不使绝缘膜的膜强度下降，获得可靠性高的半导体器件。
具有上述微小空隙的绝缘膜，用对硅倍半环氧乙烷氢化合物或硅倍半环氧乙烷甲基化合物作为主要成分的膜进行加热后获得的以SiO作为主要成分的绝缘膜来形成。
以硅倍半环氧乙烷氢化合物作为主要成分的涂敷溶液是使以通式(HSiO3/2)n表示的化合物溶解于甲基异丁脂甲酮等溶剂中的溶液。而以硅倍半环氧乙烷甲基化合物作为主要成分的涂敷溶液是使以通式(CH3SiO3/2)n表示的化合物溶解于甲基异丁脂甲酮等溶剂中的溶液。
将这些溶液涂敷在衬底上，在100～250℃左右的温度下中间加热后，通过在氮气气氛等惰性气体气氛内350～450℃的温度下进行加热，梯形结构地形成Si-O-Si的键，最终形成以SiO为主要成分的绝缘膜。
在以加热硅倍半环氧乙烷氢化合物或硅倍半环氧乙烷甲基化合物为主要成分的膜所获得的SiO作为主要成分的绝缘膜中，作为控制绝缘膜中存在的空隙直径的方法，例如可列举以下方法：使硅倍半环氧乙烷(Silsesquioxane)化合物溶液含有甲基异丁脂甲酮等溶剂以外的成分，将膜中原成分分解了的痕迹作为空隙来形成，通过基于成膜温度来改变分解动作，从而控制空隙形成，可将空隙直径范围收敛在选择性的范围内。
作为涂敷用于上述绝缘膜形成的溶液的方法，可列举旋转涂敷或缝隙涂敷或印刷方式。而且，因对该膜加热而形成绝缘膜，所以即使在高密度地形成微细的布线情况下，与基于CVD法的绝缘膜比较，台阶差的覆盖性良好，在可消除表面台阶差方面具有优势。
此外，对于Si晶片的大口径化来说，在使用CVD法形成绝缘膜时需要大型的成膜装置，设备成本对元件成本产生大的影响。相反，在本发明中以涂敷·加热方式来形成绝缘膜，所以可大幅度降低设备成本，可以期待抑制制造生产线的投资成本、以及元件成本的极大效果。
在用CVD法形成绝缘膜的情况下，使用以烷基硅烷化合物、烷氧基硅烷化合物为主要成分的源气体，按照ECR(电子回旋加速器谐振源ElectronCyclotron Resonance)等离子体CVD法等，最终形成以SiO为主要成分的绝缘膜。
这种情况下，作为控制绝缘膜中存在的空隙直径的方法，例如可列举以下方法：作为源气体，含有热分解温度高的成分，通过成膜时350℃～450℃的加热，将膜中原成分分解了的痕迹作为空隙来形成。
在这样的方法中，通过选择各种热分解温度高的成分，可基于成膜温度来改变分解动作，由此控制空隙形成，从而可将空隙直径范围收敛在选择性的范围内。
此外，在本发明的半导体器件中，在元器件周边设置可包围元器件周边的由形成导体布线的材料构成的隔壁层(在本发明中称为保护环)，以防止来自半导体器件周边部的吸湿、透湿。由此，根据本发明，遮蔽从元件周边、衬底与层间绝缘膜的界面透过层间绝缘膜内的水分，可提高元件自身的抗湿可靠性。
附图说明
图1是第1实施例中制作的层叠结构的半导体器件的剖面图。
图2是用于说明第1实施例中制作的半导体器件的工序图。
图3是用于说明绝缘膜中存在的空隙直径分布的图。
图4是用于说明绝缘膜中存在的空隙直径分布的图。
图5是用于说明第17实施例中制作的层叠结构的半导体器件的工序图。
图6是用于说明第19实施例中制作的半导体逻辑器件的剖面图。
图7是用于说明第20实施例中制作的树脂密封型半导体器件的剖面图。
图8是用于说明第21实施例中制作的晶片级芯片尺寸封装结构半导体器件的剖面图。
图9是用于说明第22实施例中制作的具有保护环结构的半导体器件的剖面图及平面图。
附图中各附图标记分别表示：
101半导体衬底，102第一布线层的第一绝缘膜，103第一布线层的第二绝缘膜，104第一布线层的第三绝缘膜/笫二布线层的第一绝缘膜，105第二布线层的第二绝缘膜，106第二布线层的第三绝缘膜/第三布线层的第一绝缘膜，107第三布线层的第二绝缘膜，108第三布线层的第三绝缘膜/第四布线层的第一绝缘膜，109第四布线层的第二绝缘膜，110第四布线层的第三绝缘膜/第五布线层的第一绝缘膜，111第五布线层的第二绝缘膜，112第五布线层的第三绝缘膜/第六布线层的第一绝缘膜，113第六布线层的第二绝缘膜，114最上层氮化硅膜，115导体布线层，117开口，118开口，119布线沟，120阻挡金属膜，121导体层，501半导体衬底，502第一布线层的第一绝缘膜，503第一布线层的第二绝缘膜，504第一布线层的第三绝缘膜/第二布线层的第一绝缘膜，505第二布线层的第二绝缘膜，506第二布线层的第三绝缘膜，517开口，518开口，519布线沟，520阻挡金属膜，521导体层，601半导体衬底，602元件分隔膜区域，603MOS晶体管，604氧化硅膜，605BPSG(硼·磷硅酸盐玻璃)膜，606导电栓塞，607第一布线层的第一绝缘膜，608第一布线层的第二绝缘膜，609第一布线层的及三绝缘膜/第二布线层的第一绝缘膜，610第二布线层的第二绝缘膜，611第二布线层的第三绝缘膜，612第三布线层的第一绝缘膜，613第三布线层的第二绝缘膜，614第三布线层的第三绝缘膜/第四布线层的第一绝缘膜，615第四布线层的第二绝缘膜，616第四布线层的第三绝缘膜，617第五布线层的第一绝缘膜，618第五布线层的第二绝缘膜，619第五布线层的第三绝缘膜/第六布线层的第一绝缘膜，620第六布线层的第二绝缘膜，621第六布线层的第三绝缘膜，622最上层氮化硅膜，623导体布线层，701半导体逻辑器件，702表面保护膜，703树脂密封部，704金线，705导电壳，706外部端子，801半导体衬底，802 SiN膜，803焊盘部，804绝缘膜层，805再排列布线，806绝缘膜层，807凸点金属层，808凸点，901半导体衬底，902氮化硅膜，903划线，904保护环层，905元件装置周边保护环层，906半导体元件
具体实施方式
以下，参照附图说明本发明的实施方式。
(第1实施例)
在第1实施例中，制作图1所示的具有6层布线层100的Cu布线双镶嵌结构的6层布线半导体元件。
一般，在用众所周知的方法形成了MOS晶体管等构成元件(图示省略)的半导体衬底101上，用CVD法形成厚度为40nm的成为第一布线层100a的第一绝缘层的碳化氮化硅膜102。该第一绝缘层在形成布线图形的开口时成为刻蚀停止膜。
接着，用CVD法形成厚度为400nm的成为第一布线100a的第二绝缘层的氧化硅膜103。
然后，用CVD法形成厚度为40nm的成为第一布线层100a的第三绝缘层的碳化氮化硅膜104。该膜在作为第二布线层100b的第一绝缘层来形成布线图形的开口时起刻蚀停止膜或Cu扩散阻挡膜的作用。
接着，在碳化氮化硅膜104上形成开口117。使用光抗蚀剂，用公知的技术形成抗蚀剂图形，使用可除去碳化氮化硅膜的刻蚀气体，以抗蚀剂为掩模，用干法刻蚀方式形成开口(图2(a))。此时，开口成为第一布线层100a的布线尺寸。
然后，用与形成第一布线层100a同样的方法，形成厚度为400nm的成为第二布线层100b的第二绝缘层的氧化硅膜105，厚度为40nm的成为第三绝缘层的碳化氮化硅膜106。
接着，在碳化氮化硅膜上形成开口118(图2(b))。使用光抗蚀剂，用公知的技术形成抗蚀剂图形，使用可除去碳化氮化硅膜的刻蚀气体，以抗蚀剂为掩模，用干法刻蚀方式形成开口。
然后，以碳化氮化硅膜为掩模，采用可除去氧化硅膜的CF系气体，用干法刻蚀方式，在氧化硅膜105上形成开口，在其下部碳化氮化硅膜104的开口117露出。
接着，以碳化氮化硅膜104的开口117为掩模，在氧化硅膜103上形成开口，在其下部使碳化氮化硅膜102露出。
其次，切换成可除去碳化氮化硅膜的刻蚀气体，以氧化硅膜103为掩模，干法刻蚀除去碳化氮化硅膜102，形成到半导体衬底101贯通的开口。此时，碳化氮化硅膜104也被刻蚀，扩大到与最上层的碳化氮化硅膜的开口118相同的尺寸。由此，形成到半导体衬底101贯通的布线沟119(图2(c))。
然后，在布线沟119内面形成阻挡金属膜120之后，用公知的电镀法进行Cu121的填充。在本实施例中，阻挡金属用TiN。
接着，通过除去最上层的碳化氮化硅膜上存在的不需要的Cu膜、洗净表面，同时形成连接用的栓塞和布线。除去Cu膜时，使用作为磨料采用氧化铝或硅石，采用由Cu络合剂、界面活性剂等添加剂构成的研磨剂的化学机械抛光法(Chemical Mechanical Polishing)较好。
在该研磨工艺中，还研磨除去与最上层接触的碳化氮化硅膜106。由此，制作形成了Cu布线(包括120和121)的双镶嵌结构(图2(d))。
接着，再次实施同样的工序，形成第三布线层100c-第6布线层100f，获得6层Cu布线结构。此时，绝缘层106、108、110、112由用CVD法成膜的碳化氮化硅膜构成，绝缘层107、109由氧化硅膜构成。并且，绝缘层111、113由添加氟的氧化硅膜构成。
接着，在最上层形成氮化硅膜114，制作配有6层Cu布线115的多层布线半导体元件(图1)。
由此，通过用介电常数比氮化硅膜低的碳化氮化硅膜作为刻蚀停止膜或扩散阻挡膜，并且，在多层结构的上层部中，用介电常数比氧化硅膜小的添加氟的氧化硅膜，获得层间绝缘膜整体的介电常数降低了的高性能的半导体器件。
(第2实施例)
用与第1实施例同样的方法，在本实施例中，即使对于绝缘层107、109，也用CVD法成膜添加氟的氧化硅膜。其次，在最上层形成氮化硅膜114，制作配置6层的Cu布线115的多层布线半导体元件。
由此，通过用介电常数比氮化硅膜低的碳化氮化硅膜作为刻蚀停止膜或扩散阻挡膜，并且，在多层结构的1/3以上的上层部中，用介电常数比氧化硅膜小的添加氟的氧化硅膜，获得层间绝缘膜整体的介电常数降低了的高性能的半导体器件。
(第3实施例)
用与第1实施例同样的方法，在本实施例中，对于绝缘层102、104、106、108、110、112，用CVD法成膜碳化硅膜。其次，在最上层形成氮化硅膜114，制作配置6层的Cu布线115的多层布线半导体元件。
由此，通过用介电常数比氮化硅膜低的碳化硅膜作为刻蚀停止膜或扩散阻挡膜，获得层间绝缘膜整体的介电常数降低了的高性能的半导体器件。
(第4实施例)
用与第2实施例同样的方法，在本实施例中，对于绝缘层102、104、106、108、110、112，用CVD法成膜碳化硅膜。其次，在最上层形成氮化硅膜114，制作配置6层的Cu布线115的多层布线半导体元件。
由此，通过用介电常数比氮化硅膜低的碳化硅膜作为刻蚀停止膜或扩散阻挡膜，获得层间绝缘膜整体的介电常数降低了的高性能的半导体器件。
(第5实施例)
用与第1实施例同样的方法，在本实施例中，对于绝缘层111、113，用CVD法成膜添加碳的氧化硅膜，制作配置6层的Cu布线115的多层布线半导体元件。
由此，通过在多层结构的上层部中，采用介电常数比氧化硅膜小的添加碳的氧化硅膜，获得层间绝缘膜整体的介电常数降低了的高性能的半导体器件。
(第6实施例)
用与第2实施例同样的方法，在本实施例中，对于绝缘层107、109、111、113，用CVD法成膜添加碳的氧化硅膜，制作配置6层的Cu布线115的多层布线半导体元件。
此外，通过在多层结构的1/3以上的上层部中，采用介电常数比氧化硅膜低的添加碳的氧化硅膜，获得层间绝缘膜整体的介电常数降低了的高性能的半导体器件。
(第7实施例)
用与第5实施例同样的方法，在本实施例中，对于绝缘层102、104、106、108、110、112，用CVD法成膜碳化硅膜。其次，在最上层形成氮化硅膜114，制作配置6层的Cu布线115的多层布线半导体元件。
由此，通过用介电常数比氮化硅膜低的碳化硅膜作为刻蚀停止膜或扩散阻挡膜，获得层间绝缘膜整体的介电常数降低了的高性能的半导体器件。
(第8实施例)
用与第6实施例同样的方法，在本实施例中，对于绝缘层102、104、106、108、110、112，用CVD法成膜碳化硅膜。其次，在最上层形成氮化硅膜114，制作配置6层的Cu布线115的多层布线半导体元件。
由此，通过用介电常数比氮化硅膜的低的碳化硅膜作为刻蚀停止膜或扩散阻挡膜，获得层间绝缘膜整体的介电常数降低了的高性能的半导体器件。
(第9实施例)
用与第1实施例同样的方法，在本实施例中，对于绝缘层103、105、107、109，用CVD法成膜添加碳的氧化硅膜，制作配置6层的Cu布线115的多层布线半导体元件。
由此，通过在多层结构的下层部中，采用介电常数低的添加碳的氧化硅膜作为绝缘膜，并且，在多层结构的上层部中，采用介电常数比氧化硅膜小的添加氟的氧化硅膜，获得层间绝缘膜整体的介电常数降低了的高性能的半导体器件。
(第10实施例)
用与第2实施例同样的方法，在本实施例中，对于绝缘层103、105，用CVD法成膜添加碳的氧化硅膜，制作配置6层的Cu布线115的多层布线半导体元件。
由此，通过在多层结构的下层部中，采用介电常数低的添加碳的氧化硅膜作为绝缘膜，并且，在多层结构的1/3以上的上层部中，采用介电常数比氧化硅膜小的添加氟的氧化硅膜，获得层间绝缘膜整体的介电常数降低了的高性能的半导体器件。
(第11实施例)
用与第3实施例同样的方法，在本实施例中，对于绝缘层103、105、107、109，用CVD法成膜添加碳的氧化硅膜，制作配置6层的Cu布线115的多层布线半导体元件。
由此，通过在多层结构的下层部中，采用介电常数低的添加碳的氧化硅膜作为绝缘膜，并且，在多层结构的上层部中，采用介电常数比氧化硅膜小的添加氟的氧化硅膜，和采用介电常数比氮化硅膜低的碳化硅膜作为刻蚀停止膜或扩散阻挡膜，获得层间绝缘膜整体的介电常数降低了的高性能的半导体器件。
(第12实施例)
用与第4实施例同样的方法，在本实施例中，对于绝缘层103、105，用CVD法成膜添加碳的氧化硅膜，制作配置6层的Cu布线115的多层布线半导体元件。
由此，通过在多层结构的下层部中，采用介电常数低的添加碳的氧化硅膜作为绝缘膜，并且，在多层结构的1/3以上的上层部中，采用介电常数比氧化硅膜小的添加氟的氧化硅膜，和采用介电常数比氮化硅膜低的碳化硅膜作为刻蚀停止膜或扩散阻挡膜，获得层间绝缘膜整体的介电常数降低了的高性能的半导体器件。
(第13实施例)
用与第1实施例同样的方法，在本实施例中，对于绝缘层103、105、107、109，用涂敷法在衬底上形成以硅倍半环氧乙烷氢化合物为主成份的甲基异丁脂甲酮溶液之后，在氮气气氛中，用电炉进行100℃10分钟，然后150℃10分钟，230℃10分钟的加热。
然后，用氮气气氛中的炉体，通过进行350℃30分钟的加热，以梯形结构形成Si-O-Si键，最终形成以SiO为主成份，在膜中具有控制空隙形成的微小空隙的绝缘膜，制作配置6层的Cu布线115的多层布线半导体元件。用可刻蚀SiO的CF系气体，以干法刻蚀方式形成开口。
本实施例的情况如图3所示，为存在微小空隙的绝缘膜，其介电常数为2.3左右，所述微小空隙具有主要包含直径为0.05nm以上4nm以下的空隙的分布特性。
基于用理学电机(股份公司)制造的X线薄膜结构分析装置(型号：ATX?G)获得的X线反射测量数据和漫散射X线测量数据，与基于设想为球状散射体的散射函数的理论散射强度进行比较来计算散射体的直径分布，由此求出直径分布。
此外，上述在膜中具有微小空隙的绝缘膜具有杨氏模量为12Ga的特性。这种特性，采用使用美国MTS系统公司制的NanoindenterXP的硬度计测量法，关于在Si晶片上形成的膜厚250nm的该膜、通过在总膜厚的1/5的表层点的硬度，求出上述膜硬度。
杨氏模量也是在总膜厚的1/5表层点的值，基于熔融石英的泊松比0.17进行换算。用同样的方法求出的相同程度的膜厚的p？TEOS膜，具有杨氏模量为70Ga的特性。
由此，上述在膜中具有微小空隙的的绝缘膜，为具有p？TEOS膜的约17％的杨氏模量的膜，因而获得与特开2000？340569号公报中记载的低介电常数膜相比，在机械特性上更好的低介电常数绝缘膜。
由此，通过在多层结构的下层部中，采用介电常数为2.5以下且膜强度好的绝缘膜，并且，在多层结构的上层部中，采用介电常数比氧化硅膜小的添加氟的氧化硅膜，使层间绝缘膜整体的介电常数降低，获得抑制了元件结构的机械强度降低的高性能的半导体器件。
(第14实施例)
用与第13实施例同样的方法，在本实施例中，对于绝缘层102、104、106、108、110、102，用CVD法成膜碳化硅膜。
然后，在最上层形成氮化硅膜114，制作配置6层的Cu布线115的多层布线半导体元件。
由此，通过采用介电常数比氮化硅膜低的碳化硅膜作为刻蚀停止膜或扩散阻挡膜，并且采用在膜中具有微小空隙的绝缘膜来规定空隙直径，获得机械特性优异的低介电常数绝缘膜。
而且，通过再在多层层叠结构的下层部中，采用介电常数低于2.5的膜强度优异的绝缘膜作为第二绝缘层，并且在多层结构的上层部中，采用介电常数比氧化硅膜小的添加氟的氧化硅膜作为第二绝缘层，使层间绝缘膜整体的介电常数降低，获得抑制了元件结构的机械强度降低的高性能的半导体器件。
(第15实施例)
用与第13实施例同样的方法，在本实施例中，对于绝缘层103、105、107、109，在用涂敷法在衬底之上形成以硅倍半环氧乙烷氢化合物为主成份的甲基异丁脂酮甲酮溶液之后，在氮气气氛中，用电炉进行100℃10分钟，然后150℃10分钟，230℃10分钟的加热。
然后，用氮气气氛中的炉体，通过进行350℃30分钟的加热，以梯形结构形成Si-O-Si键，最终形成以SiO为主成份，在膜中具有控制空隙形成的微小空隙的绝缘膜，制作配置6层的Cu布线115的多层布线半导体元件。用可刻蚀SiO的气体，以干法刻蚀方式形成开口。
本实施例的情况如图4所示，为存在微小空隙的绝缘膜，其介电常数为2.7左右，所述微小空隙具有主要包含直径为0.05nm以上1nm以下的空隙的分布特性。
基于用X线薄膜结构分析装置获得的X线反射测量数据和漫散射X线测量数据，与基于设想为球状散射体的散射函数的理论散射强度进行比较来计算散射体的直径分布，由此求出直径分布。
此外，上述在膜中具有微小空隙的绝缘膜具有杨氏模量为11Ga的特性。这种特性，采用使用NanoindenterXP的硬度计测量法，关于在Si晶片上形成的膜厚250nm的该膜、通过在总膜厚的1/5的表层点的硬度，求出上述膜硬度。
杨氏模量也是在总膜厚的1/5表层点的值，基于熔融石英的泊松比0.17进行换算。用同样的方法求出的相同程度的膜厚的p？TEOS膜，具有杨氏模量为70Ga的特性。
由此，上述在膜中具有微小空隙的的绝缘膜，为具有p？TEOS膜的约16％的杨氏模量的膜，因而获得与特开2000？340569号公报中记载的低介电常数膜相比，在机械特性上更好的低介电常数绝缘膜。
根据上述，通过在多层层叠结构的下层部中，采用介电常数为3.0以下且膜强度好的绝缘膜作为第二绝缘层，并且，在多层层叠结构的上层部中，采用介电常数比氧化硅膜小的添加氟的氧化硅膜作为第二绝缘层，使层间绝缘膜整体的介电常数降低，获得抑制了元件结构的机械强度降低的高性能的半导体器件。
(第16实施例)
用与第15实施例同样的方法，在本实施例中，对于绝缘层102、104、106、108、110、102，用CVD法成膜碳化硅膜。然后，在最上层形成氮化硅膜114，制作配置6层的Cu布线115的多层布线半导体元件。
由此，通过采用介电常数比氮化硅膜的低的碳化硅膜作为刻蚀停止膜或扩散阻挡膜，并且采用在膜中具有微小空隙的绝缘膜来规定空隙直径，获得机械特性好的低介电常数绝缘膜。而且，通过在多层层叠结构的下层部中，采用介电常数为3.0以下且膜强度好的绝缘膜作为第二绝缘层，并且在多层结构的上层部中，采用介电常数比氧化硅膜小的添加氟的氧化硅膜作为第二绝缘层，使层间绝缘膜整体的介电常数降低，获得抑制了元件结构的机械强度降低的高性能的半导体器件。
(第17实施例)
第17实施例是适于形成Cu布线双镶嵌结构的例子，用图5(a)-5(d)的工序图进行说明。
一般，在用公知的方法形成了MOS晶体管等构成元件(图示省略)的半导体衬底501上，用CVD法形成厚度为40nm的成为第一布线层的第一绝缘层的碳化氮化硅膜502。该第一绝缘层在形成布线图形的开口时成为刻蚀停止膜。
然后，用涂敷法在衬底之上形成以硅倍半环氧乙烷氢化合物为主成份的甲基异丁脂酮甲酮溶液之后，在氮气气氛中，用电炉进行100℃10分钟，然后150℃10分钟，230℃10分钟的加热。然后，用氮气气氛中的炉体，通过进行350℃30分钟的加热，以梯形结构形成Si-O-Si键，最终形成以SiO为主成份的绝缘膜作为第一布线层的第二绝缘层503，该绝缘膜如图3所示那样，为存在微小空隙的绝缘膜，其介电常数为2.3左右，所述微小空隙具有主要包含直径为0.05nm以上4nm以下的空隙的分布特性。
接着，用CVD法形成厚度为40nm的成为第一布线层的第三绝缘层的碳化氮化硅膜504。该膜在作为第二布线层的第一绝缘层来形成布线图形的开口时起刻蚀停止膜或Cu扩散阻挡膜的作用。
接着，在碳化氮化硅膜504上形成开口517。使用光抗蚀剂，用公知的技术形成抗蚀剂图形，使用可除去碳化氮化硅膜的刻蚀气体，以抗蚀剂为掩模，用干法刻蚀方式形成开口(图5(a))。此时，开口成为第一布线层的布线尺寸。
然后，用与形成第一布线层的第二绝缘层503相同的方法，形成厚度为400mn的成为第二布线层的第二绝缘层的绝缘层505，绝缘层505存在微小空隙且介电常数为2.3左右，所述微小空隙具有如图3所示那样主要包含直径为0.05nm以上4nm以下的空隙的分布特性，和形成厚度为40nm的成为第三绝缘层的碳化氮化硅膜506。
接着，在碳化氮化硅膜上形成开口518(图5(b))。使用光抗蚀剂，用公知的技术形成抗蚀剂图形，使用可除去碳化氮化硅膜的刻蚀气体，以抗蚀剂为掩模，用干法刻蚀方式形成开口。
然后，以碳化氮化硅膜为掩模，采用可除去具有微小空隙的SiO膜的气体，用干法刻蚀方式，在绝缘层505上形成开口，在其下部碳化氮化硅膜504的开口517露出。
接着，以碳化氮化硅膜504的开口517为掩模，在绝缘层503上形成开口，在其下部使碳化氮化硅膜502露出。其次，切换成可除去碳化氮化硅膜的刻蚀气体，以绝缘层503的开口为掩模，干法刻蚀除去碳化氮化硅膜502，形成到半导体衬底501贯通的开口。此时，碳化氮化硅膜504也被刻蚀，扩大到与最上层的碳化氮化硅膜的开口518相同的尺寸。由此，形成到半导体衬底501贯通的布线沟519(图5(c))。
然后，在布线沟119内面形成阻挡金属膜120之后，用公知的电镀法进行Cu121的填充。在本实施例中，阻挡金属用TiN。
接着，通过用化学机械抛光法除去最上层的碳化氮化硅膜上存在的不需要的Cu膜、洗净表面，同时形成连接用的栓塞和布线。在该研磨工序中，不研磨除去与最上层接触的碳化氮化硅膜而残留。由此，制作形成了Cu布线(包括520和521)的双镶嵌结构(图5(d))。
如上所述，通过使用介电常数低的膜作为层间绝缘层的主要构成层的第二绝缘层503，获得层间绝缘层整体的介电常数降低了的高性能的半导体器件。
本实施例的结构是二层层叠布线层的结构，但通过二次以上反复层叠绝缘层也可获得具有多层布线层结构的半导体器件。
(第18实施例)
与第17实施例同样，在本实施例中，对于第二绝缘层503，如图4所示，形成存在微小空隙且介电常数为2.7左右的SiO绝缘膜，所述微小空隙具有主要包含直径为0.05nm以上1nm以下的空隙的分布特性，制作形成Cu布线的双镶嵌结构。
由此，关于作为层间绝缘层主要构成层的第二绝缘层503通过使用介电常数低的膜，获得层间绝缘层整体的介电常数降低了的高性能的半导体器件。此外，通过二次以上反复层叠绝缘层也可容易地获得具有多层布线结构的半导体器件。
(第19实施例)
图6是第19实施例的半导体逻辑元件的剖面图。用已知的STI(浅沟槽隔离：Shallow Trench Isolation)在半导体衬底601上形成元件分隔膜区域602，在该元件分隔膜区域602内部形成MOS晶体管603(为了容易看清图，省略了晶体管部的阴影线)。然后，用已知的CVD法在包含MOS晶体管603的半导体衬底601的表面上顺序形成50nm左右的氧化硅膜604和500nm左右的BPSG(硼·磷硅酸盐玻璃)膜605之后，在例如800-900℃的氮气气氛下进行回流退火
接着，用硅磨粒，采用化学机械抛光法，使BPSG膜605的表面平坦化之后，形成接触孔，在该接触孔内，用CVD法进行钨的埋入，形成导电栓塞606。此时，用公知的刻蚀法除去BPSG膜605表面上存在的不需要的钨。
接着，与第17实施例同样，用CVD法形成厚度为40nm的成为第一布线层的第一绝缘层的碳化氮化硅膜607。该第一绝缘层在形成布线图形的开口时成为刻蚀停止膜。
然后，用涂敷法在衬底之上形成以硅倍半环氧乙烷氢化合物为主成份的甲基异丁脂甲酮溶液之后，在氮气气氛中，用电炉进行100℃10分钟，然后150℃10分钟，230℃10分钟的加热。然后，用氮气气氛中的炉体，通过进行350℃30分钟的加热，以梯形结构形成Si-O-Si键，最终形成以SiO为主成份，如图3所示那样，存在微小空隙且介电常数为2.3左右的绝缘膜，所述微小空隙具有主要包含直径为0.05nm以上4nm以下的空隙的分布特性，来作为第一布线层的第二绝缘层608。
接着，用CVD法形成厚度为40nm的成为第一布线层的第三绝缘层的碳化氮化硅膜609。该膜在作为第二布线层的第一绝缘层来形成布线图形的开口时起刻蚀停止膜或Cu扩散阻挡膜的作用。
接着，在碳化氮化硅膜609上形成开口。使用光抗蚀剂，用公知的技术形成抗蚀剂图形，使用可除去碳化氮化硅膜的刻蚀气体，以抗蚀剂为掩模，用干法刻蚀方式形成开口。此时，开口成为第一布线层的布线尺寸。
然后，用与形成第一布线层的第二绝缘层608相同的方法，形成厚度为400nm的第二布线层的第二绝缘层610，形成厚度为40nm的成为第三绝缘层的碳化氮化硅膜611。
接着，在碳化氮化硅膜上形成开口。然后，以碳化氮化硅膜为掩模，采用可除去具有微小空隙的SiO膜的气体，用干法刻蚀方式，在绝缘层610上形成开口，在其下部碳化氮化硅膜609露出。
接着，以碳化氮化硅膜609的开口为掩模，在绝缘层608上形成开口，在其下部使碳化氮化硅膜607露出。其次，切换成可除去碳化硅膜的刻蚀气体，以绝缘层608的开口为掩模，干法刻蚀除去碳化氮化硅膜607，形成到导电栓塞606贯通的开口。
此时，碳化氮化硅膜609也被刻蚀，扩大到与最上层的碳化硅膜的开口相同的尺寸。由此，形成到导电栓塞606贯通的布线沟。
然后，在布线沟内面形成阻挡金属膜之后，用公知的电镀法进行Cu的填充。在本实施例中，阻挡金属用TiN。接着，通过用化学机械抛光法除去最上层的碳化氮化硅膜上存在的不需要的Cu膜、洗净表面，同时形成连接用的栓塞和布线。在该研磨工序中，不研磨除去与最上层接触的碳化硅膜611而使其残留。由此，制作形成了Cu布线的双镶嵌结构。
重复以上工序，形成四层布线结构体。
接着，重复同样的工序，层叠2层的布线结构。此时，用碳化氮化硅膜形成厚度为40nm的绝缘层617、619、621。此外，用添加氟的氧化硅膜形成厚度为600nm的绝缘层618、620。其次，在最上层形成氮化硅膜622，制作配有6层Cu布线623的多层布线半导体元件。
由此，通过使用介电常数比氮化硅膜低的碳化硅膜作为刻蚀停止膜或扩散阻挡膜，在多层层叠结构的下层部中，使用介电常数低于2.5的膜强度好的绝缘膜作为第二绝缘层，此外，在其上层部中，使用介电常数比氧化硅膜小的添加氟的氧化硅膜作为第二绝缘层，获得层间绝缘层整体的介电常数降低了的高性能的半导体器件。
(第20实施例)
图7表示第20实施例的树脂密封的半导体逻辑器件的剖面图。除了第19实施例中获得的键合焊盘部以外，将形成了聚酰亚胺表面保护膜702的状态下的半导体逻辑器件701固定于另外设置的双键合工序中的引线框架上。然后，用引线接合器在设置于半导体逻辑器件701中的键合焊盘部和引线框架的外部端子705之间布线了金线704。
接着，使用日立化成工业(股份公司)制造的含有硅石的联苯系环氧树脂，形成树脂密封部703以便包住半导体逻辑器件701、外部端子705等。密封条件为成形温度180℃、成形压力70kg/cm2，但不限于此。最后，通过将外部端子706弯曲成规定的形状，获得树脂密封型半导体逻辑装置的完成品。
在树脂密封的半导体逻辑器件的层间绝缘膜的一部分上，使用介电常数小但充分抑制了机械强度下降的绝缘膜，所以在引线键合工艺和树脂密封工艺中，对于在半导体逻辑元件上的应力，在元件内部不产生裂纹，可获得树脂密封品。
此外，不用说，作为半导体逻辑元件的特性，可获得第19实施例中说明的同样效果，而且由于进行树脂密封，所以对于外部环境可发挥稳定的特性。
(第21实施例)
图8是用于说明第21实施例的剖面图，是将第19实施例中说明的半导体逻辑元件用于晶片级芯片尺寸封装结构的产品制造中的情况。
在半导体逻辑元件801的最上层氮化硅膜802上，以使键合焊盘部803露出的形状形成聚酰亚胺绝缘膜804。接着，形成再排列布线805。在本实施例中，再排列布线由溅射法成膜TiN、Cu、Ni的这三层构成，在成膜后按照公知的光刻技术来形成布线图形。
进而在其上形成聚酰亚胺绝缘膜806。贯通该聚酰亚胺绝缘膜层806，在再排列布线805的一部分区域中设置用于进行电连接的下凸点金属层807。下凸点金属层形成Cr、Ni、Au这三层。在该下凸点金属层807之上形成焊接凸点808。
可高速驱动的半导体逻辑元件本身可通过第19实施例中记述的方法形成在晶片上，所以根据本实施例，可实现晶片状态下具有焊接凸点的半导体逻辑元件封装器件。
通过采用介电常数低的层间绝缘膜层，与现有产品相比，已经获得高性能的半导体逻辑元件。但是，在将封装半导体产品封装搭载在印刷电路板等上时，通过采用本实施例的封装结构，可高速进行元件和印刷电路板间的信号传播，可进一步发挥半导体逻辑元件的性能。
(第22实施例)
图9表示用于说明第22实施例的元件端部的剖面图(图9(a))和晶片平面示意图(图9(b))。
在硅衬底901中形成MOS晶体管等半导体元件906和包含这些元件的半导体电路部，在该衬底901之上形成上述说明的布线层。然后，使用由构成布线层的导体组成的材料来配置保护环层905，以便包围该半导体元件906和包含这些元件的半导体电路部。通过该保护环层905，可以防止来自外部的水分浸入半导体元件906和包含这些元件的半导体电路部。该保护环层905在形成导体布线的工序中形成。
由此，特别是在采用具有空隙的绝缘膜作为表示低介电常数特性的层间绝缘膜的情况下，可解决向孔内部的水分透过和吸附的问题，可以提供使半导体元件自身的抗湿可靠性提高的半导体器件。
以上，用实施例详细地进行了说明，但用于实现本发明及实施例的许多条件等不限定于这些实施例。
如以上说明，在具有采用了在层间绝缘膜层中埋入降低了布线电阻的铜布线的镶嵌结构的多层层叠布线的半导体元件中，通过使用介电常数比氮化硅膜小的膜作为刻蚀停止膜和扩散阻挡膜，并且使多层层叠结构的下层部和上层部的绝缘膜有所不同，可以提高元件整体的机械强度，并且可以获得降低层间绝缘膜整体的介电常数的高性能的半导体器件。

Claims (12)

1.一种半导体器件，在衬底上层叠了多个布线层，其特征在于：
所述布线层分别包括：
第一绝缘层、第二绝缘层和第三绝缘层；以及
贯通所述第一至第三绝缘层形成的导体布线；
所述第一绝缘层和所述第三绝缘层包含碳化氮化硅膜、碳化硅和氧化硅的至少其中之一；
在所述布线层中位于下层部的布线层的第二绝缘层包含氧化硅；
在所述布线层中位于上层部的布线层的第二绝缘层包含添加氟的氧化硅和添加碳的氧化硅的至少其中之一。
2.一种半导体器件，在衬底上层叠了多个布线层，其特征在于：
所述布线层分别包括：
第一绝缘层、第二绝缘层和第三绝缘层；以及
贯通所述第一至第三绝缘层形成的导体布线；
所述第一绝缘层和所述第三绝缘层包含碳化氮化硅膜、碳化硅和氧化硅的至少其中之一；
在所述布线层中位于下层部的布线层的第二绝缘层的介电常数小于在所述布线层中位于上层部的布线层的第二绝缘层的介电常数。
3.如权利要求1或2所述的半导体器件，其特征在于，在所述布线层中位于所述下层部的布线层的第二绝缘层的介电常数低于3.0。
4.如权利要求1～3中任一项所述的半导体器件，其特征在于，在所述布线层中位于所述下层部的布线层的第二绝缘层有微小空隙。
5.如权利要求4所述的半导体器件，其特征在于，半数以上的所述微小空隙的直径为0.05nm以上、4nm以下。
6.如权利要求1～5中任一项所述的半导体器件，其特征在于，在所述布线层中位于所述下层部的布线层的第二绝缘层含有SiO。
7.如权利要求1～6中任一项所述的半导体器件，其特征在于，在所述布线层中位于所述下层部的布线层的第二绝缘层是对包含硅倍半环氧乙烷氢化合物或硅倍半环氧乙烷甲基化合物的膜进行加热后获得的绝缘膜。
8.如权利要求1～6中任一项所述的半导体器件，其特征在于，在所述布线层中位于所述下层部的布线层的第二绝缘层由包含烷基硅烷化合物、烷氧基硅烷化合物的膜构成。
9.如权利要求1～8中任一项所述的半导体器件，其特征在于，在所述布线层中位于下层部的所述布线层的所述第二绝缘层的构成成分与在所述布线层中位于上层部的所述布线层的所述第二绝缘层的构成成分有所不同。
10.如权利要求1～9中任一项所述的半导体器件，其特征在于，相邻的所述布线层中，配置于下层的布线层的第三绝缘层兼作配置于上层的布线层的第一绝缘层。
11.一种半导体器件，其特征在于，包括：
衬底；
半导体元件，被设置在所述衬底上；
布线层，包括第一绝缘层、由介电常数低于3.0的绝缘膜材料构成的第二绝缘层、第三绝缘层和导体布线；以及
保护环层，使用构成所述布线层的材料，以可包围所述半导体元件的周边来配置。
12.如权利要求11所述的半导体器件，其特征在于，所述第二绝缘层是在内部具有直径为0.05nm以上、4nm以下的微小空隙的氧化硅膜。
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