CN107004663A - 具有存储器封装下的控制器的存储器装置及相关的系统及方法 - Google Patents

具有存储器封装下的控制器的存储器装置及相关的系统及方法 Download PDF

Info

Publication number
CN107004663A
CN107004663A CN201580062595.6A CN201580062595A CN107004663A CN 107004663 A CN107004663 A CN 107004663A CN 201580062595 A CN201580062595 A CN 201580062595A CN 107004663 A CN107004663 A CN 107004663A
Authority
CN
China
Prior art keywords
memory
package
encapsulation
controller
storage arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201580062595.6A
Other languages
English (en)
Inventor
倪胜锦
黄宏远
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of CN107004663A publication Critical patent/CN107004663A/zh
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/1319—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/29294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/2939—Base material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/8185—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/81855—Hardening the adhesive by curing, i.e. thermosetting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/8185—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/81855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/81856—Pre-cured adhesive, i.e. B-stage adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83874—Ultraviolet [UV] curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92227—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/1033—Gallium nitride [GaN]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1437—Static random-access memory [SRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1438—Flash memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1443—Non-volatile random-access memory [NVRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Non-Volatile Memory (AREA)
  • Geometry (AREA)

Abstract

本文揭示具有存储器封装堆叠下的控制器的存储器装置及相关的系统及方法。在一个实施例中，存储器装置经配置以耦合到主机且可包含衬底、存储器封装的堆叠及定位于所述堆叠与所述衬底之间的控制器。所述控制器可基于来自所述主机的命令而管理由所述存储器封装存储的数据。

Description

具有存储器封装下的控制器的存储器装置及相关的系统及 方法
技术领域
所揭示的实施例涉及具有存储器封装及控制器的存储器装置。在若干实施例中，本发明涉及包含位于存储器封装的堆叠下的嵌入式控制器的存储器装置。
背景技术
快闪存储器常用于存储智能电话、导航系统(例如汽车导航系统)、数码相机、MP3播放器、计算机及许多其它消费型电子装置的数据。通用串行总线(USB)装置、存储器卡、嵌入式磁盘驱动器及其它数据存储装置通常包含快闪存储器，这是归因于快闪存储器的小形状因子。电子装置中的专用存储器控制器可管理存储于快闪存储器上的数据。不幸地，这些专用存储器控制器会减少电子装置中的其它组件的可用空间。为减小电子装置的大小，可将存储器控制器集成到主机处理器中以(例如)增加其它电子组件的可用空间。举例来说，主机处理器可具有管理由快闪存储器存储的数据的集成存储器控制器(IMC)，但这些IMC与特定类型的存储器兼容且通常无法支持新型存储器，例如针对未来标准(例如嵌入式多媒体卡(eMMC)标准规格的未来版本)而设计的新“与非”存储器。由于IMC将电子装置限制于特定类型的快闪存储器，所以所述电子装置无法使用具有较高存储密度、改进性能或增强功能的新存储器。
存储器控制器还可嵌入于多裸片存储器封装内。举例来说，常规eMMC存储器可为具有嵌入式多媒体卡(MMC)控制器的单高容量“与非”封装(例如具有堆叠裸片的“与非”封装)。所述嵌入式MMC控制器可使主机处理器免于执行需要大量计算资源的“与非”存储器管理(例如写入、读取、擦除、错误管理等等)。因为“与非”裸片具有难以测试的小特征，所以在封装之前不测试个别“与非”裸片。多裸片“与非”封装可经测试以识别待舍弃的坏封装(例如，具有坏“与非”裸片的封装)。不幸地，坏“与非”封装中的嵌入式MMC控制器还被舍弃，从而导致制造成本增加。
附图说明
图1是根据本发明的实施例而配置的存储器装置的横截面图。
图2是根据本发明的实施例而配置的多裸片存储器封装的横截面图。
图3A到3E是说明根据本发明的实施例的各种制造阶段中的存储器装置的横截面图。
图4是根据本发明的另一实施例而配置的存储器装置的横截面图。
图5是说明根据本发明的实施例的合适用于存储器装置的实施方案的框电路图。
图6是包含根据本发明的实施例而配置的存储器装置的系统的示意图。
具体实施方式
下文将描述存储器装置及相关系统及方法的一些实施例的特定细节。术语“存储器装置”一般是指具有封装衬底、一或多个多裸片存储器封装及控制器的封装。所述控制器可定位于所述存储器封装下且可对每一存储器封装提供存储器管理。在一些实施例中，存储器装置可为具有合适用于移动装置(例如智能电话、平板计算机、MP3播放器等等)、数码相机、路由器、游戏系统、导航系统、计算机及其它消费型电子装置的多裸片存储器封装的快闪存储器(例如eMMC存储器、通用快闪存储装置等等)。举例来说，所述多裸片存储器封装可为(例如)快闪存储器封装，例如“与非”封装、“或非”封装等等。相关领域的技术人员还应了解，本发明可具有额外实施例，且可在无下文参考图1到6而描述的实施例的一些细节的情况下实践本发明。
图1是根据本发明的实施例而配置的存储器装置100的横截面图。存储器装置100可包含封装衬底104(“衬底104”)、控制器106及布置成堆叠的第一、第二、第三及第四多裸片存储器封装108a、108b、108c、108d(统称为“存储器封装108”)。衬底104可电耦合到控制器106及存储器封装108，使得控制器106介接于存储器封装108与主机(例如电子装置的主机处理器)之间，所述主机与存储器装置100通信。控制器106可附着到衬底104。在一些实施例中，控制器106可定位于存储器封装108的堆叠下，使得存储器装置100具有相对较小占用面积。
控制器106可处置存储器管理，使得主机处理器免于执行其它任务。在各种实施例中，控制器106可包含电路、软件、固件、存储器或其组合且可经配置以管理快闪存储器(例如“与非”存储器、“或非”存储器等等)。在一些实施例中，控制器106可为包含半导体衬底(例如硅衬底、绝缘体上硅衬底、化合物半导体(例如氮化镓)衬底或其它合适衬底)的控制器裸片，且可具有各种集成电路组件或功能特征中的任何者，例如动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)、其它形式的集成电路装置(其包含处理电路、成像组件及/或用于管理存储器或其它组件的其它半导体装置)。举例来说，控制器106可为经配置以与“与非”存储器一起使用的多媒体控制器裸片(例如MMC控制器裸片)且可包含电路、寄存器、接口模块(例如用于与主机介接的模块，用于与存储器封装介接的模块等等)及/或用于提供所要功能的其它模块。
衬底104可包含第一接合垫120及第二接合垫122。第一接合垫120可通过第一线接合140而耦合到控制器106的对应接合垫130，且第二接合垫122可通过第二线接合142而耦合到存储器封装108中的每一者的对应封装接点132(识别一者)。在一个实施例中，衬底104是将控制器106电耦合到每一存储器封装108的单个中介层。衬底104可包含(例如)具有电连接器144(以虚线示意性地展示)(例如金属迹线、通孔或其它合适连接器)的印刷电路板、多媒体卡衬底或其它合适中介层。电连接器144可使控制器106、第一接合垫120及/或第二接合垫122彼此耦合及/或经由衬底104的下侧处的封装接点150(识别一者)及互连件152(识别一者)而耦合到外部电路(图中未展示)。互连件152可为凸块接合件或其它合适连接特征。
控制器106可通过粘合剂160而附着到封装衬底104。粘合剂160可为粘合剂材料(例如环氧树脂、粘胶(adhesive paste)等等)、粘合剂叠层(例如胶带、裸片附着或切块裸片附着膜等等)或其它合适材料。第一存储器封装108a可通过覆盖控制器106及线接合140的粘合剂162而附着到衬底104。接着，额外存储器封装108b到108d通过粘合剂164而彼此附着。在一些实施例中，粘合剂160、162、164可包括相同或类似材料。粘合剂162可具有比粘合剂164厚的厚度以容纳控制器106与存储器封装108a之间的线接合140的部分。粘合剂164的厚度可足够大以确保线接合142穿过相邻存储器封装108之间的间隙166(识别一者)。存储器装置100可进一步包含封装壳115，其包括至少部分囊封存储器封装108及线接合142的囊封剂116。
图2是根据本发明的实施例而配置的存储器封装108的横截面图。存储器封装108可包含多个存储器半导体裸片200(识别一者)及存储器封装衬底202(“封装衬底202”)。封装衬底202可包含多个第一接合垫208a及多个第二接合垫208b。第一接合垫208a可耦合到(例如，线接合到)第一群组的半导体裸片200(例如两组的四个裸片)的对应接合垫209a(识别一者)，且第二接合垫208b可耦合到(例如，线接合到)第二群组的半导体裸片200(例如两组的四个裸片)的对应接合垫209b(识别一者)。在一些实施例中，接合垫208a的阵列电耦合到每一半导体裸片200的阵列的接合垫209a。可基于相应接合垫209a、209b的配置、数目及大小而选择接合垫208a、208b的配置、数目及大小。在一些实施例中，一行接合垫208b电耦合到每一半导体裸片200的一行接合垫209b。封装衬底202可包含(例如)具有电连接器(例如金属迹线、通孔或其它合适连接器)的中介层、印刷电路板或其它合适衬底，所述电连接器包含用于将存储器封装108电耦合到衬底104(图1)的封装接点132(例如接合垫)、互连件(例如凸块接合件)及/或其它特征。
图2展示呈垂直堆叠布置的半导体裸片200，其中相邻半导体裸片200彼此横向偏移。在其它实施例中，半导体裸片200可直接垂直堆叠于彼此上(即，无任何横向偏移)，或呈任何其它合适堆叠布置，且可由半导体衬底(例如硅衬底、绝缘体上硅衬底、化合物半导体(例如氮化镓)衬底或其它合适衬底)形成。半导体裸片200可为经切割或单一化裸片且可具有各种集成电路组件或功能特征中的任何者，例如非易失性存储器、快闪存储器(例如“与非”快闪存储器、“或非”快闪存储器等等)、DRAM、SRAM、其它形式的集成电路装置(例如处理电路、成像组件及/或其它半导体装置)。尽管所说明的存储器封装108包含16个存储器裸片200，但存储器封装108还可为具有16个以上或16个以下存储器裸片(例如一个裸片、两个裸片、四个裸片、八个裸片、十个裸片、二十个裸片等等)的多芯片封装。可基于存储器封装108的所要存储容量而选择裸片的数目。由于嵌入式控制器106可管理多个存储器封装，所以存储器封装中的一或多者(例如所有存储器封装108)可不具有用于存储器管理的任何嵌入式控制器裸片。
存储器封装108可进一步包含由至少部分囊封半导体裸片200的堆叠及线接合的囊封剂116(例如热固性材料、环氧树脂或其它合适材料)组成的封装壳215。封装壳215可提供免受周围环境(例如湿度)影响的遮蔽、电隔离(例如线接合之间的电隔离)及/或在处置期间对内部组件的保护。
图3A到3E是说明根据本发明的实施例的用于组装各种制造阶段中的存储器装置100的方法的横截面图。一般来说，控制器106可耦合到衬底104且接着第一存储器封装108a可耦合到衬底104，使得控制器106定位于第一存储器封装108a与封装衬底104之间。额外存储器封装可堆叠于存储器封装108a上。在将存储器封装108电耦合到衬底104之后，可由囊封剂116囊封存储器封装108。下文将详细讨论制造阶段的细节。
参考图3A，可沿衬底104(例如具有电路的硅晶片)的上表面240定位第一接合垫120及第二接合垫122，且可沿衬底104的下表面242定位封装接点150。控制器106通常具有比封装108小的占用面积，因此，控制器106可在堆叠封装组合件108之前附着且电耦合到衬底104。有利地，控制器106及其电连接件(例如线接合140)不会干扰存储器封装108的堆叠及附着。如图3A中所展示，可将携载粘合剂160的控制器106放置于衬底104的上表面240上，使得控制器106与接合垫120、122隔开以提供用于线接合的足够空隙。粘合剂160可为裸片附着粘胶或粘合剂元件，例如裸片附着膜或切块裸片附着膜(分别被所属领域的技术人员称为“DAF”或“DDF”)。在一个实施例中，粘合剂160可包含压力凝固粘合剂元件(例如胶带或膜)，当所述压力凝固粘合剂元件被压缩超过压力的阈值水平时，所述压力凝固粘合剂元件将控制器106粘着到衬底104。在另一实施例中，粘合剂160可为通过暴露于UV辐射而凝固的UV凝固胶带或膜。
图3B展示将控制器106附着到衬底104且形成第一线接合140之后的存储器装置100。控制器106的对置横向侧可具有通过线接合140而耦合到对应接合垫120(例如一行接合垫120)的阵列的接合垫130(例如一行接合垫130)。封装108a可携载呈合适于与线接合一起使用的“导线上膜(film-over-wire)”材料的形式的粘合剂162。在其它实施例中，可使用焊料或其它合适直接裸片附着技术来将控制器106直接耦合到衬底104。在此类实施例中，粘合剂162可为DAF或DDF。可将具有粘合剂162的存储器封装108a放置于衬底140的上表面240上，使得存储器封装108a横向向外延伸超过控制器106的外围。因而，可在组装期间将整个控制器106直接定位于存储器封装108a与衬底104之间。粘合剂162的厚度可足够大以防止存储器封装108a的下表面243与线接合140之间的接触以避免损坏线接合140。此外，可将接合垫120直接定位于存储器封装108a下以确保控制器106的电连接件不干扰后续线接合过程。
图3C展示将存储器封装108a附着到衬底104且形成第二线接合142之后的存储器装置100。可使用粘合剂164来将第二存储器封装108b附着到第一存储器封装108a。额外存储器封装(用隐线展示存储器封装108c)可堆叠于存储器封装108上且电耦合到衬底104。粘合剂164的厚度可经选择以维持相邻存储器封装108之间的所要距离以避免损坏线接合142。举例来说，粘合剂164可足够厚以防止线接合142与相邻存储器封装108之间的接触恰好位于此类线接合142上。
图3D展示已通过线接合142而将每一存储器封装108电耦合到衬底104之后的存储器装置100。每一存储器封装108的对置横向侧可具有通过线接合142而耦合到对应接合垫122(例如一行接合垫122)的阵列的接合垫132(例如一行接合垫132)。所说明的存储器装置100具有四个存储器封装108。在其它实施例中，存储器装置100可携载更多或更少存储器封装108，例如单个存储器封装108、两个存储器封装108、五个存储器封装108、八个存储器封装108、十个存储器封装108、十五个存储器封装108等等。存储器装置100除包含存储器封装108中的一或多者之外，还可包含其它封装或裸片，及/或可包含其它封装或裸片来代替存储器封装108中的一或多者。可基于存储器装置100的所要功能及尺寸而选择存储器封装及/或裸片的数目、配置及布置。
存储器封装108可布置成垂直堆叠，使得当从上观察时，存储器封装108相对于彼此而居中。此对准布置可提供具有相对较小占用面积的存储器装置100。在其它实施例中，垂直堆叠的存储器封装180可经彼此横向偏移以提供用于接近接合垫132的增大空隙。可基于(例如)线接合过程或其它后续过程而选择横向偏移的方向及距离。存储器封装108可堆叠成其它布置及配置以提供具有所要总大小的封装。
图3E展示囊封剂116至少部分囊封存储器封装108的堆叠及线接合142(识别一个群组的线接合)之后的存储器装置100。囊封剂116可包含(例如)热固性材料、树脂(例如环氧树脂)或其它合适材料(其提供(例如)机械支撑、免受周围环境(例如湿度)影响的遮蔽、及/或电隔离(例如线接合之间的电隔离))。在一些实施例中，可由囊封剂116完全囊封存储器封装108及线接合146。在囊封存储器封装108之后，处理可继续到后续制造阶段，例如形成球形接合件、单一化、切块或其它所要过程。
图3A到3E的制造过程可提高产品合格率，这是因为可在组装之前测试个别组件。存储器封装108可经个别测试以确保每一存储器封装108具有已知良好裸片(KGD)。举例来说，每一存储器封装108可经测试以测试存储器裸片108中的每一者(图2)。有利地，存储器封装108的衬底202(图2)可具有合适使用标准测试设备来测试的相对较大连接件。具有KGD的存储器封装108可经选择以用于组装成封装，同时可舍弃具有已知坏裸片的存储器封装108。因此，衬底104及控制器106仅与良好存储器封装108组装以提供高产率。此外，衬底104可具有用于测试组装之后的衬底104、控制器106、存储器封装108及/或其它内部组件的标准球栅阵列或其它合适特征(例如测试垫)。可识别且舍弃有缺陷的存储器装置100。
图4是根据本发明的另一实施例而配置的存储器装置300的横截面图。存储器装置300可包含大体上类似于结合图1到3E而描述的存储器装置100的特征的特征。存储器装置300可包含通过线接合142(识别一组)而电耦合到封装衬底104的存储器封装108，且控制器106可通过线接合140(被识别的一者)而电耦合到封装衬底104。存储器装置300还可包含存储器封装108a与衬底104之间的一或多个间隔物310。间隔物310可为硅或其它合适材料的经切割或单化部件，其经定尺寸以将第一存储器封装108a定位成略微高于控制器106及线接合140。粘合剂(例如粘胶、DAF、胶带等等)可用于将间隔物310紧固到衬底104及/或存储器封装108a。其它类型之间隔物310(例如b-阶段树脂)可用于使存储器封装108a与衬底104隔开达所要距离且用于紧固存储器封装108a。所述b-阶段树脂可经固化以将存储器封装108a完全粘着到衬底104。
囊封剂116可部分或完全囊封经堆叠的存储器封装108及线接合142，且囊封剂116还可延伸到第一存储器封装108a与衬底104之间的空腔320中。空腔320可由间隔物310的侧壁324、存储器封装108a的下表面243及衬底104的上表面240界定。在制造期间，囊封剂116可流动到空腔320中以至少部分囊封控制器106及线接合140，使得囊封剂116使将控制器106耦合到衬底104的电连接件电隔离。
图5是说明根据本发明的实施例的存储器装置的实施方案的框电路图。存储器装置500可为存储器装置100、300中的一者或可包含大体上类似于存储器装置100、300的特征的特征。存储器装置500可为管理主机502与存储器封装108中的每一者之间的数据传送的封装。控制器106可经配置以提供存储器控制且可包含用于提供功能的一或多个模块520。模块520可包含(但不限于)用于错误校正的错误校正码(ECC)模块、用于错误检测的错误检测码(EDC)模块、耗损均衡模块、用于将逻辑映射到物理块的地址映射模块、用于块管理(例如坏块管理、备用块管理等等)的模块、错误复原模块、用于分区保护的模块、用于从控制器106启动的模块或其它所要模块。控制器106可经由总线510而与主机502介接且可包含经由存储器总线514而可操作地耦合到存储器封装108的接口506。控制器106可为根据多媒体卡规格(例如规格版本4.4、4.41等等)而设计的MMC控制器。在一些嵌入式多媒体卡(eMMC)实施例中，控制器106可具有总线510，其提供双向数据信号(例如用于单位数据传送、4位数据传送、8位数据传送等等的数据信号)，从主机502接收命令信号，对主机502作出响应，及/或时控用于使总线传送同步的信号。
主机502可包含具有处理能力的装置且能够与存储器装置500介接。主机502可为移动装置的组件(例如主机控制器、硬件、处理器、驱动器等等)、个人计算机、游戏机或能够将命令输入提供到存储器装置500的其它电子装置。控制器106可基于来自主机502的命令输入而管理数据(例如写入、读取、擦除数据)。
本文所描述的存储器装置中的任一者可并入到许多更大及/或更复杂系统中的任何者(例如图6中所示意性地展示的系统600)中。系统600可包含存储器装置602、电源604、主机606(例如I/O驱动器)、处理器608及/或其它子系统或组件610。存储器装置602可为存储器装置100、300、500中的一者或包含大体上类似于上文所描述的存储器装置的特征的特征。主机606可包含大体上类似于图5的主机502的特征。所得系统600可执行各种功能中的任何者，例如存储器存储、数据处理及/或其它合适功能。因此，代表性系统600可为(但不限于)手持式装置(例如移动电话、平板计算机、数字阅读器及数字音频播放器)、计算机、数码相机、电器及车辆(例如汽车、轮船、飞机)。系统600的组件可容纳于单个单元中或分布于多个互连单元中(例如，通过通信网路)。如果存储器装置602是可移除的，那么其可由另一存储器装置(例如具有更先进功能的新存储器装置)替换。存储器装置中的每一者可具有嵌入式控制器，其经配置以管理存储器来避免主机606与板上存储器之间的不兼容。
可基于电子装置的大小而选择本文所揭示的存储器装置的大小。举例来说，图1的存储器装置100或图4的存储器装置300可具有约4mm到约7mm的范围内的高度、约13mm到约17mm的范围内的宽度及约17mm到约25mm的范围内的长度。存储器封装108(参阅图1及2)可具有约0.75mm到约1.5mm的范围内的高度(例如1.2mm)、约12mm到约16mm的范围内的宽度及约16mm到约20mm的范围内的长度。
本文所描述的存储器装置可并入到各种类型的存储装置中。具有“与非”封装的存储器装置(例如图1中的存储器装置100或图4中的存储器装置300)可并入到USB驱动、存储器卡、固态磁盘驱动器或其它高密度存储器存储装置中。具有“或非”封装的存储器装置(例如图1中的存储器装置100或图4中的存储器装置300)可为嵌入式装置的部分。本文所揭示的存储器装置可使用不同类型的堆叠封装(PIP)技术、系统级封装(SIP)技术或其它所要封装技术且可具有(例如)球栅阵列。举例来说，图1中的存储器装置100或图4中的存储器装置300可为具有标准球栅阵列的封装。
本文所揭示的至少一些实施例是包括封装衬底、具有半导体裸片的多个堆叠存储器封装、控制器及囊封剂的存储器装置。所述控制器附着到所述封装衬底且定位于所述存储器封装与所述封装衬底之间。所述控制器经配置以管理所述存储器封装中的每一者。所述囊封剂由所述封装衬底携载且囊封所述存储器封装中的一或多者。
在一些实施例中，存储器装置包括衬底、用于存储的多个堆叠构件、用于控制的构件及囊封剂。用于控制的所述构件附着到用于存储的所述构件且定位于用于存储的所述多个堆叠构件与所述衬底之间。用于控制的所述构件经配置以管理用于存储的所述构件中的每一者。用于存储的每一构件可为存储器封装。所述囊封剂可由所述衬底携载且可囊封用于存储的所述多个堆叠构件。
在一些实施例中，多媒体装置包括中介层、电耦合到所述中介层的存储器构件的堆叠、及多媒体控制构件。所述多媒体控制构件附着到所述中介层且定位于存储器构件的所述堆叠与所述中介层之间。所述多媒体控制构件可经配置以管理主机与所述存储器构件中的每一者之间的数据传送。囊封剂可囊封存储器构件的所述堆叠。每一存储器构件可为多芯片存储器封装。
应从上文了解，本文已出于说明目的而描述本发明的特定实施例，但可在不背离本发明的情况下作出各种修改。如果上下文允许，那么单数或复数术语还可分别包含复数或单数术语。除非用语“或”与明示(其指示所述用语应仅限于意味排除与列表的两个或两个以上项目有关的其它项目的单个项目)相关，否则这列表中的“或”的使用应被解译为包含(a)所述列表中的任何单个项目、(b)所述列表中的所有项目或(c)所述列表中的项目的任何组合。此外，术语“垂直”、“横向”、“上”及“下”可指代存储器装置中的特征鉴于图中所展示的定向的相对方向或位置。然而，这些术语应被广义地解释为包含具有其它定向的存储器装置及其组件(例如，在其侧上翻转或经反转)。
还可在其它实施例中组合或消除特定实施例的上下文中所描述的新技术的某些方面。此外，尽管已在所述实施例的上下文中描述与新技术的某些实施例相关的优点，但其它实施例还可展现此类优点且未必需要所有实施例展现落于本发明的范围内的此类优点。因此，本发明及相关技术可涵盖本文未明确展示或描述的其它实施例。

Claims (26)

1.一种存储器装置，其包括：
封装衬底；
多个堆叠存储器封装，其具有半导体裸片；
控制器，其附着到所述封装衬底且定位于所述多个堆叠存储器封装与所述封装衬底之间，其中所述控制器经配置以管理所述存储器封装中的每一者；及
囊封剂，其由所述封装衬底携载且囊封存储器封装的所述堆叠。
2.根据权利要求1所述的存储器装置，其中所述控制器经配置以管理到所述存储器封装中的每一者的数据传送及来自所述存储器封装中的每一者的数据传送。
3.根据权利要求1或2中任一权利要求所述的存储器装置，其中所述封装衬底包含多个第一接合垫及多个第二接合垫，且其中所述存储器装置进一步包含
多个第一线接合，其将所述多个第一接合垫耦合到所述存储器封装；及
多个第二线接合，其将所述多个第二接合垫耦合到所述控制器。
4.根据权利要求1到3中任一权利要求所述的存储器装置，其中所述存储器封装中的每一者包含衬底、多个存储器半导体裸片、及至少部分囊封所述存储器半导体裸片的封装壳。
5.根据权利要求1到4中任一权利要求所述的存储器装置，其中所述存储器封装中的每一者电连接到所述封装衬底的多芯片封装。
6.根据权利要求1到5中任一权利要求所述的存储器装置，其中所述存储器封装中的每一者通过裸片附着粘合剂而附着到所述存储器封装的相邻一者。
7.根据权利要求1到6中任一权利要求所述的存储器装置，其中所述多个堆叠存储器封装包含第一存储器封装及第二存储器封装，其中所述第一存储器封装附着到所述封装衬底，且所述第二存储器封装通过裸片附着粘合剂而附着到所述第一存储器封装。
8.根据权利要求1到7中任一权利要求所述的存储器装置，其中所述存储器封装包括快闪存储器且包含“与非”存储器及/或“或非”存储器。
9.根据权利要求1到8中任一权利要求所述的存储器装置，其中所述存储器封装中的每一者是不具有嵌入式控制器的“与非”封装。
10.根据权利要求1到9中任一权利要求所述的存储器装置，其中所述控制器定位于所述堆叠中的所述存储器封装的底部一者与所述封装衬底之间。
11.根据权利要求1到10中任一权利要求所述的存储器装置，其进一步包括存储器封装的所述堆叠与所述封装衬底之间的间隔物，且其中所述间隔物与所述控制器横向隔开。
12.根据权利要求1到11中任一权利要求所述的存储器装置，其中所述控制器经配置以命令所述存储器封装读取数据、擦除数据及/或写入资料。
13.根据权利要求1到12中任一权利要求所述的存储器装置，其中所述控制器定位于所述存储器封装中的每一者外。
14.一种经配置以耦合到主机的多媒体装置，所述多媒体装置包括：
中介层；
多芯片存储器封装的堆叠，其电耦合到所述中介层；
多媒体控制器裸片，其附着到所述中介层且定位于多芯片存储器封装的所述堆叠与所述中介层之间，其中所述多媒体控制器裸片经配置以管理所述主机与所述多芯片存储器封装中的每一者之间的数据传送；及
囊封剂，其囊封多芯片存储器封装的所述堆叠。
15.根据权利要求14所述的多媒体装置，其中所述多媒体控制器裸片耦合到所述存储器封装中的每一者。
16.根据权利要求14或15中任一权利要求所述的多媒体装置，其中所述多媒体控制器裸片经配置以提供错误校正、块管理、耗损均衡及/或物理到逻辑映射。
17.根据权利要求14到16中任一权利要求所述的多媒体装置，其中所述多媒体控制器裸片包含耦合到所述多芯片存储器封装中的每一者的存储器接口。
18.根据权利要求14到17中任一权利要求所述的多媒体装置，其中每一多芯片存储器封装是“与非”封装。
19.一种制造存储器封装的方法，所述方法包括：
将控制器附着到封装衬底；
将第一存储器封装附着到所述封装衬底，使得所述控制器定位于所述第一存储器封装与所述封装衬底之间；
将第二存储器封装附着到所述第一存储器封装；且
囊封所述第一存储器封装及所述第二存储器封装。
20.根据权利要求19所述的方法，其进一步包括
将所述控制器线接合到所述封装衬底；及
将所述第一存储器封装及所述第二存储器封装线接合到所述封装衬底。
21.根据权利要求19或20中任一权利要求所述的方法，其进一步包括：使囊封剂流动到所述封装衬底与所述第一存储器封装之间的空腔中，使得所述囊封剂至少部分囊封所述控制器。
22.根据权利要求19到21中任一权利要求所述的方法，其中将所述第一存储器封装附着到所述封装衬底包含：将所述第一存储器封装附着到所述封装衬底，使得所述控制器的大部分直接定位于所述第一存储器封装与所述封装衬底之间。
23.根据权利要求19到21中任一权利要求所述的方法，其中将所述第一存储器封装附着到所述封装衬底包含：将所述第一存储器封装安装到所述封装衬底，使得将所述控制器耦合到所述封装衬底的线接合直接位于所述第一存储器封装与所述封装衬底之间。
24.根据权利要求19到23中任一权利要求所述的方法，其中所述控制器是多媒体控制器且所述第一存储器封装及所述第二存储器封装是“与非”封装及/或“或非”封装。
25.根据权利要求19到24中任一权利要求所述的方法，其进一步包括：测试所述第一封装及所述第二封装以在将所述第一存储器封装及所述第二存储器封装附着到所述封装衬底之前识别已知良好封装。
26.根据权利要求19到25中任一权利要求所述的方法，其进一步包括：在囊封所述第一存储器封装及所述第二存储器封装及额外存储器封装之前，将所述额外封装堆叠于所述第二存储器封装上。
CN201580062595.6A 2014-11-21 2015-11-19 具有存储器封装下的控制器的存储器装置及相关的系统及方法 Pending CN107004663A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/550,243 US9627367B2 (en) 2014-11-21 2014-11-21 Memory devices with controllers under memory packages and associated systems and methods
US14/550,243 2014-11-21
PCT/US2015/061592 WO2016081730A1 (en) 2014-11-21 2015-11-19 Memory devices with controllers under memory packages and associated systems and methods

Publications (1)

Publication Number Publication Date
CN107004663A true CN107004663A (zh) 2017-08-01

Family

ID=56010975

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580062595.6A Pending CN107004663A (zh) 2014-11-21 2015-11-19 具有存储器封装下的控制器的存储器装置及相关的系统及方法

Country Status (7)

Country Link
US (4) US9627367B2 (zh)
EP (1) EP3221888B1 (zh)
JP (2) JP6865498B2 (zh)
KR (1) KR101969249B1 (zh)
CN (1) CN107004663A (zh)
TW (3) TWI664703B (zh)
WO (1) WO2016081730A1 (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109887850A (zh) * 2019-02-18 2019-06-14 长江存储科技有限责任公司 一种3d封装多点焊接的方法及装置、设备及存储介质
CN110211952A (zh) * 2018-02-28 2019-09-06 东芝存储器株式会社 半导体装置
CN110718544A (zh) * 2018-07-12 2020-01-21 东芝存储器株式会社 半导体装置
CN110970414A (zh) * 2019-12-06 2020-04-07 华天科技（西安）有限公司 一种多芯片封装结构及制造方法
CN112436009A (zh) * 2019-08-08 2021-03-02 美光科技公司 包含结合衬垫下方的电路系统的存储器装置

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9627367B2 (en) * 2014-11-21 2017-04-18 Micron Technology, Inc. Memory devices with controllers under memory packages and associated systems and methods
KR102359370B1 (ko) * 2015-10-05 2022-02-09 에스케이하이닉스 주식회사 반도체장치
US10873145B2 (en) * 2016-12-29 2020-12-22 Intel Corporation Ground heat sink for dual inline memory module cooling
US20190067248A1 (en) 2017-08-24 2019-02-28 Micron Technology, Inc. Semiconductor device having laterally offset stacked semiconductor dies
US20190067034A1 (en) * 2017-08-24 2019-02-28 Micron Technology, Inc. Hybrid additive structure stackable memory die using wire bond
JP2019165046A (ja) * 2018-03-19 2019-09-26 東芝メモリ株式会社 半導体装置およびその製造方法
US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method
KR20190121560A (ko) 2018-04-18 2019-10-28 삼성전기주식회사 팬-아웃 반도체 패키지
KR102540050B1 (ko) 2018-07-05 2023-06-05 삼성전자주식회사 반도체 패키지
US20200117449A1 (en) * 2018-10-12 2020-04-16 Micron Technology, Inc. Accelerated Access to Computations Results Generated from Data Stored in Memory Devices
US11157213B2 (en) * 2018-10-12 2021-10-26 Micron Technology, Inc. Parallel memory access and computation in memory devices
US10461076B1 (en) 2018-10-24 2019-10-29 Micron Technology, Inc. 3D stacked integrated circuits having functional blocks configured to accelerate artificial neural network (ANN) computation
US11005501B2 (en) * 2019-02-19 2021-05-11 Micron Technology, Inc. Error correction on a memory device
EP3891806A4 (en) * 2019-04-15 2022-10-12 Yangtze Memory Technologies Co., Ltd. UNITED SEMICONDUCTOR DEVICES HAVING HETEROGENEOUS PROCESSOR AND MEMORIES AND METHODS FOR FORMING THEM
US11424212B2 (en) 2019-07-17 2022-08-23 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US11081468B2 (en) * 2019-08-28 2021-08-03 Micron Technology, Inc. Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding and related methods, devices and apparatuses
JP7293056B2 (ja) * 2019-09-12 2023-06-19 キオクシア株式会社 半導体装置およびその製造方法
KR20220055112A (ko) 2020-10-26 2022-05-03 삼성전자주식회사 반도체 칩들을 갖는 반도체 패키지
US20230015323A1 (en) * 2021-07-19 2023-01-19 Texas Instruments Incorporated Semiconductor package with topside cooling

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004034433A2 (en) * 2002-10-08 2004-04-22 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package
US20080237310A1 (en) * 2007-03-26 2008-10-02 Shanggar Periaman Die backside wire bond technology for single or stacked die package
US20100314740A1 (en) * 2009-06-15 2010-12-16 Samsung Electronics Co., Ltd. Semiconductor package, stack module, card, and electronic system
US20130049221A1 (en) * 2011-08-31 2013-02-28 Samsung Electronics Co., Ltd. Semiconductor package having plural semiconductor chips and method of forming the same

Family Cites Families (96)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6266753B1 (en) * 1997-07-10 2001-07-24 Cirrus Logic, Inc. Memory manager for multi-media apparatus and method therefor
TW495943B (en) * 2001-04-18 2002-07-21 Siliconware Precision Industries Co Ltd Semiconductor package article with heat sink structure and its manufacture method
US20030127719A1 (en) 2002-01-07 2003-07-10 Picta Technology, Inc. Structure and process for packaging multi-chip
US6930378B1 (en) * 2003-11-10 2005-08-16 Amkor Technology, Inc. Stacked semiconductor die assembly having at least one support
JP5197961B2 (ja) * 2003-12-17 2013-05-15 スタッツ・チップパック・インコーポレイテッド マルチチップパッケージモジュールおよびその製造方法
JP2005209882A (ja) * 2004-01-22 2005-08-04 Renesas Technology Corp 半導体パッケージ及び半導体装置
US20050269692A1 (en) * 2004-05-24 2005-12-08 Chippac, Inc Stacked semiconductor package having adhesive/spacer structure and insulation
US7253511B2 (en) * 2004-07-13 2007-08-07 Chippac, Inc. Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package
US20070090517A1 (en) 2005-10-05 2007-04-26 Moon Sung-Won Stacked die package with thermally conductive block embedded in substrate
SG135074A1 (en) * 2006-02-28 2007-09-28 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
US8710675B2 (en) * 2006-02-21 2014-04-29 Stats Chippac Ltd. Integrated circuit package system with bonding lands
US7420269B2 (en) * 2006-04-18 2008-09-02 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
JP2007311395A (ja) * 2006-05-16 2007-11-29 Toppan Printing Co Ltd 半導体装置及び半導体装置の製造方法
TW200828561A (en) 2006-12-20 2008-07-01 Powertech Technology Inc Stacked-chip package structure
JP2008166527A (ja) * 2006-12-28 2008-07-17 Spansion Llc 半導体装置およびその製造方法
US8609463B2 (en) * 2007-03-16 2013-12-17 Stats Chippac Ltd. Integrated circuit package system employing multi-package module techniques
JP2008299997A (ja) * 2007-06-01 2008-12-11 Toshiba Corp 半導体記憶装置
US20110024890A1 (en) * 2007-06-29 2011-02-03 Stats Chippac, Ltd. Stackable Package By Using Internal Stacking Modules
TW200915970A (en) * 2007-09-27 2009-04-01 Sanyo Electric Co Circuit device, circuit module and outdoor equipment
JP2009081325A (ja) * 2007-09-27 2009-04-16 Sanyo Electric Co Ltd 回路装置
TWI402952B (zh) * 2007-09-27 2013-07-21 Sanyo Electric Co 電路裝置及其製造方法
US10074553B2 (en) * 2007-12-03 2018-09-11 STATS ChipPAC Pte. Ltd. Wafer level package integration and method
US8399973B2 (en) * 2007-12-20 2013-03-19 Mosaid Technologies Incorporated Data storage and stackable configurations
US7867819B2 (en) * 2007-12-27 2011-01-11 Sandisk Corporation Semiconductor package including flip chip controller at bottom of die stack
JP2009206429A (ja) * 2008-02-29 2009-09-10 Toshiba Corp 記憶媒体
US8626355B2 (en) 2008-04-01 2014-01-07 Hewlett-Packard Development Company, L. P. Cooling provisioning management in a three dimensional package
JP2010010407A (ja) * 2008-06-27 2010-01-14 Toshiba Corp 半導体記憶装置
JP2010021306A (ja) * 2008-07-10 2010-01-28 Hitachi Ltd 半導体装置
US8004093B2 (en) * 2008-08-01 2011-08-23 Stats Chippac Ltd. Integrated circuit package stacking system
JP2010238898A (ja) * 2009-03-31 2010-10-21 Toshiba Corp 半導体装置
US7944029B2 (en) * 2009-09-16 2011-05-17 Sandisk Corporation Non-volatile memory with reduced mobile ion diffusion
JP5593053B2 (ja) * 2009-10-09 2014-09-17 ピーエスフォー ルクスコ エスエイアールエル 半導体装置
KR101624975B1 (ko) 2009-11-17 2016-05-30 삼성전자주식회사 3차원 반도체 기억 소자
KR101665556B1 (ko) * 2009-11-19 2016-10-13 삼성전자 주식회사 멀티 피치 볼 랜드를 갖는 반도체 패키지
TWI502723B (zh) * 2010-06-18 2015-10-01 Chipmos Technologies Inc 多晶粒堆疊封裝結構
KR101686553B1 (ko) * 2010-07-12 2016-12-14 삼성전자 주식회사 반도체 패키지 및 패키지 온 패키지
JP2012129464A (ja) * 2010-12-17 2012-07-05 Toshiba Corp 半導体装置およびその製造方法
US8531021B2 (en) * 2011-01-27 2013-09-10 Unimicron Technology Corporation Package stack device and fabrication method thereof
JP2012238725A (ja) * 2011-05-12 2012-12-06 Toshiba Corp 半導体装置とその製造方法、およびそれを用いた半導体モジュール
US8530350B2 (en) 2011-06-02 2013-09-10 Micron Technology, Inc. Apparatuses including stair-step structures and methods of forming the same
JP2012255704A (ja) * 2011-06-08 2012-12-27 Elpida Memory Inc 半導体装置
KR20120137051A (ko) * 2011-06-10 2012-12-20 삼성전자주식회사 솔리드 스테이트 드라이브 패키지 및 그의 제조 방법
JP2013021216A (ja) * 2011-07-13 2013-01-31 Toshiba Corp 積層型半導体パッケージ
KR101774938B1 (ko) * 2011-08-31 2017-09-06 삼성전자 주식회사 지지대를 갖는 반도체 패키지 및 그 형성 방법
WO2013071399A1 (en) * 2011-11-14 2013-05-23 Mosaid Technologies Incorporated Package having stacked memory dies with serially connected buffer dies
US8956968B2 (en) 2011-11-21 2015-02-17 Sandisk Technologies Inc. Method for fabricating a metal silicide interconnect in 3D non-volatile memory
US8780600B2 (en) * 2011-12-07 2014-07-15 Apple Inc. Systems and methods for stacked semiconductor memory devices
JP5840479B2 (ja) 2011-12-20 2016-01-06 株式会社東芝 半導体装置およびその製造方法
JP6122290B2 (ja) * 2011-12-22 2017-04-26 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． 再配線層を有する半導体パッケージ
KR101798571B1 (ko) 2012-02-16 2017-11-16 삼성전자주식회사 반도체 패키지
JP2013201218A (ja) * 2012-03-23 2013-10-03 Toshiba Corp 半導体装置とそれを用いた半導体モジュール
KR101906269B1 (ko) * 2012-04-17 2018-10-10 삼성전자 주식회사 반도체 패키지 및 그 제조 방법
KR101947722B1 (ko) * 2012-06-07 2019-04-25 삼성전자주식회사 적층 반도체 패키지 및 이의 제조방법
KR101909202B1 (ko) * 2012-10-08 2018-10-17 삼성전자 주식회사 패키지-온-패키지 타입의 패키지
KR20150056555A (ko) 2013-01-09 2015-05-26 샌디스크 세미컨덕터 (상하이) 컴퍼니, 리미티드 반도체 다이를 매립 및/또는 이격시키기 위한 독립적인 필름을 포함하는 반도체 디바이스
US9236368B2 (en) * 2013-01-28 2016-01-12 Sandisk Information Technology (Shanghai) Co., Ltd. Semiconductor device including embedded controller die and method of making same
US20140246781A1 (en) * 2013-03-04 2014-09-04 Kabushiki Kaisha Toshiba Semiconductor device, method of forming a packaged chip device and chip package
US9087846B2 (en) * 2013-03-13 2015-07-21 Apple Inc. Systems and methods for high-speed, low-profile memory packages and pinout designs
JP2014179484A (ja) * 2013-03-15 2014-09-25 Toshiba Corp 半導体記憶装置
KR101999114B1 (ko) * 2013-06-03 2019-07-11 에스케이하이닉스 주식회사 반도체 패키지
US9373527B2 (en) * 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
JP6067541B2 (ja) * 2013-11-08 2017-01-25 株式会社東芝 メモリシステムおよびメモリシステムのアセンブリ方法
US9600413B2 (en) * 2013-12-24 2017-03-21 Intel Corporation Common platform for one-level memory architecture and two-level memory architecture
CN104752491A (zh) * 2013-12-30 2015-07-01 晟碟半导体（上海）有限公司 用于半导体装置的间隔体层和半导体装置
CN104752380B (zh) * 2013-12-31 2018-10-09 晟碟信息科技（上海）有限公司 半导体装置
KR102317263B1 (ko) * 2014-03-11 2021-10-25 삼성전자주식회사 반도체 패키지 및 이를 포함하는 데이터 저장 장치
US9362161B2 (en) * 2014-03-20 2016-06-07 Stats Chippac, Ltd. Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package
US9384128B2 (en) * 2014-04-18 2016-07-05 SanDisk Technologies, Inc. Multi-level redundancy code for non-volatile memory controller
US9418974B2 (en) * 2014-04-29 2016-08-16 Micron Technology, Inc. Stacked semiconductor die assemblies with support members and associated systems and methods
US9406660B2 (en) * 2014-04-29 2016-08-02 Micron Technology, Inc. Stacked semiconductor die assemblies with die support members and associated systems and methods
KR102284652B1 (ko) * 2014-08-28 2021-08-02 삼성전자 주식회사 반도체 패키지
KR102210332B1 (ko) * 2014-09-05 2021-02-01 삼성전자주식회사 반도체 패키지
US9627367B2 (en) * 2014-11-21 2017-04-18 Micron Technology, Inc. Memory devices with controllers under memory packages and associated systems and methods
JP2016178196A (ja) * 2015-03-19 2016-10-06 株式会社東芝 半導体装置及びその製造方法
US10177128B2 (en) * 2015-04-01 2019-01-08 Sandisk Technologies Llc Semiconductor device including support pillars on solder mask
KR102324628B1 (ko) * 2015-07-24 2021-11-10 삼성전자주식회사 솔리드 스테이트 드라이브 패키지 및 이를 포함하는 데이터 저장 시스템
US9947642B2 (en) * 2015-10-02 2018-04-17 Qualcomm Incorporated Package-on-Package (PoP) device comprising a gap controller between integrated circuit (IC) packages
US10163871B2 (en) * 2015-10-02 2018-12-25 Qualcomm Incorporated Integrated device comprising embedded package on package (PoP) device
US10872832B2 (en) * 2015-12-16 2020-12-22 Intel Corporation Pre-molded active IC of passive components to miniaturize system in package
WO2018058416A1 (en) * 2016-09-29 2018-04-05 Intel Corporation Prepackaged stair-stacked memory module in a chip scale system in package, and methods of making same
US9978722B2 (en) * 2016-09-29 2018-05-22 Intel Corporation Integrated circuit package assembly with wire end above a topmost component
US10797039B2 (en) * 2016-12-07 2020-10-06 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a 3D interposer system-in-package module
TWI613772B (zh) * 2017-01-25 2018-02-01 力成科技股份有限公司 薄型扇出式多晶片堆疊封裝構造
US10147705B2 (en) * 2017-02-21 2018-12-04 Micron Technology, Inc. Stacked semiconductor die assemblies with die substrate extensions
US10485125B2 (en) * 2017-12-22 2019-11-19 Western Digital Technologies, Inc. Integrated USB connector and memory device
US10825696B2 (en) * 2018-07-02 2020-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Cross-wafer RDLs in constructed wafers
US11004803B2 (en) * 2018-07-02 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy dies for reducing warpage in packages
JP7042713B2 (ja) * 2018-07-12 2022-03-28 キオクシア株式会社 半導体装置
JP2020053655A (ja) * 2018-09-28 2020-04-02 キオクシア株式会社 半導体装置及び半導体装置の製造方法
US20200211760A1 (en) * 2018-12-28 2020-07-02 Texas Instruments Incorporated Molded inductor with magnetic core having mold flow enhancing channels
US11948917B2 (en) * 2019-04-23 2024-04-02 Intel Corporation Die over mold stacked semiconductor package
US11282791B2 (en) * 2019-06-27 2022-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a heat dissipation structure connected chip package
CN112151528A (zh) * 2019-06-28 2020-12-29 西部数据技术公司 包括相对表面上的接触指的半导体装置
US11282766B2 (en) * 2019-09-27 2022-03-22 Taiwan Semiconductor Manufacturing Company Package structure
US11587918B2 (en) * 2019-12-17 2023-02-21 Micron Technology, Inc. Semiconductor devices, semiconductor device packages, electronic systems including same, and related methods
JP2021125643A (ja) * 2020-02-07 2021-08-30 キオクシア株式会社 半導体装置およびその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004034433A2 (en) * 2002-10-08 2004-04-22 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package
US20080237310A1 (en) * 2007-03-26 2008-10-02 Shanggar Periaman Die backside wire bond technology for single or stacked die package
US20100314740A1 (en) * 2009-06-15 2010-12-16 Samsung Electronics Co., Ltd. Semiconductor package, stack module, card, and electronic system
US20130049221A1 (en) * 2011-08-31 2013-02-28 Samsung Electronics Co., Ltd. Semiconductor package having plural semiconductor chips and method of forming the same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110211952A (zh) * 2018-02-28 2019-09-06 东芝存储器株式会社 半导体装置
CN110211952B (zh) * 2018-02-28 2023-08-01 铠侠股份有限公司 半导体装置
CN110718544A (zh) * 2018-07-12 2020-01-21 东芝存储器株式会社 半导体装置
CN110718544B (zh) * 2018-07-12 2024-01-12 铠侠股份有限公司 半导体装置
CN109887850A (zh) * 2019-02-18 2019-06-14 长江存储科技有限责任公司 一种3d封装多点焊接的方法及装置、设备及存储介质
CN112436009A (zh) * 2019-08-08 2021-03-02 美光科技公司 包含结合衬垫下方的电路系统的存储器装置
CN112436009B (zh) * 2019-08-08 2024-05-07 美光科技公司 包含结合衬垫下方的电路系统的存储器装置
CN110970414A (zh) * 2019-12-06 2020-04-07 华天科技（西安）有限公司 一种多芯片封装结构及制造方法

Also Published As

Publication number Publication date
TW201717339A (zh) 2017-05-16
JP2018503929A (ja) 2018-02-08
JP7408588B2 (ja) 2024-01-05
US10128217B2 (en) 2018-11-13
US11658154B2 (en) 2023-05-23
US20180350776A1 (en) 2018-12-06
US20170170149A1 (en) 2017-06-15
EP3221888A4 (en) 2018-07-11
TW201633478A (zh) 2016-09-16
KR20170085065A (ko) 2017-07-21
US20200321318A1 (en) 2020-10-08
TWI649846B (zh) 2019-02-01
US9627367B2 (en) 2017-04-18
EP3221888A1 (en) 2017-09-27
TWI664703B (zh) 2019-07-01
KR101969249B1 (ko) 2019-04-15
TW201838116A (zh) 2018-10-16
US10727206B2 (en) 2020-07-28
EP3221888B1 (en) 2023-06-28
TWI578467B (zh) 2017-04-11
JP6865498B2 (ja) 2021-04-28
US20160148918A1 (en) 2016-05-26
JP2021073695A (ja) 2021-05-13
WO2016081730A1 (en) 2016-05-26

Similar Documents

Publication Publication Date Title
CN107004663A (zh) 具有存储器封装下的控制器的存储器装置及相关的系统及方法
CN101097905B (zh) 半导体器件及其制造方法
CN104253056B (zh) 具有穿通电极的半导体封装及其制造方法
US7094633B2 (en) Method for efficiently producing removable peripheral cards
CN100589121C (zh) 具有凸起部分的存储卡
CN101504939B (zh) 半导体器件
CN106256018A (zh) 具有支撑构件的堆叠式半导体裸片组合件及相关的系统及方法
CN105074918A (zh) 堆叠式存储器封装件、其制造方法和ic封装基板的插脚引线设计
US20060220201A1 (en) Structure of memory card packaging and method of forming the same
CN102456663A (zh) 半导体器件及其制造方法
CN111384053A (zh) 微控制器及其制作方法
CN105845640A (zh) 半导体封装及其制造方法、包括其的存储卡和电子系统
CN108701686A (zh) 具有复制裸片接合垫的半导体装置及相关联装置封装及其制造方法
KR20170061816A (ko) 계단식 에지를 가지는 몰딩된 스택 다이를 포함한 반도체 패키지
US8283664B2 (en) Disguising test pads in a semiconductor package
CN101488116B (zh) 通用串行总线装置
CN113161326A (zh) 包含组合存储器的半导体组合件及其制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20170801

RJ01 Rejection of invention patent application after publication