TW200828561A - Stacked-chip package structure - Google Patents

Stacked-chip package structure Download PDF

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Publication number
TW200828561A
TW200828561A TW95148022A TW95148022A TW200828561A TW 200828561 A TW200828561 A TW 200828561A TW 95148022 A TW95148022 A TW 95148022A TW 95148022 A TW95148022 A TW 95148022A TW 200828561 A TW200828561 A TW 200828561A
Authority
TW
Taiwan
Prior art keywords
electronic component
package structure
chip package
wafer
lead
Prior art date
Application number
TW95148022A
Other languages
Chinese (zh)
Inventor
Alex Liu
Chia-Chang Chang
Original Assignee
Powertech Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Priority to TW95148022A priority Critical patent/TW200828561A/en
Publication of TW200828561A publication Critical patent/TW200828561A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A stacked-chip package structure is provided. The package is configured an adhesive spacer between the upper electronic device and the lower electronic device and exploits the adhesive characteristic of the adhesive spacer to cover the lower electronic device and the wires, which surround the lower electronic device thereof, so as to sustain the upper electronic device, to protect the lower electronic device and to keep the continuity of wires.

Description

200828561 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種晶片封裝結構，特別是一種堆疊式晶片 封裝結構。 【先前技術】 者半導體製程之進步’以及使用者對電子產品輕薄短小特色之 要求與日倶增，使得降低晶片封裝體之尺寸變成各家廠商競爭之要 點，由既在之單片晶片封裝轉向多片晶片封裝，如堆疊式晶片封裝， 以縮小晶片封裝體在應用印刷電路板上之面積。請參閱第〗圖，所示 為習知之堆疊式晶片封裝結構剖面示意圖。如圖中所示，堆疊式晶片 封裝體係包含：一基板101，具有一主動面；一第一晶片102，係設置 於主動面上，且利用一黏著物（adhesion material) 103與主動 面固接；一間隔件（spacer) 121，係利用一黏著物122固接於 基板ιοί上，且設置於第一晶片102之一側；一第二晶片11〇, 係利用一黏著物固接於間隔件121上方；複數個引線墊 (wwbondpad) 1〇5、113，係設置於主動面上；複數條引線 104、U2，係分別設置於引線墊1〇5、113上，且分別連接第 一晶片102及第二晶片i10，用以分別電性連接基板ι〇ι與第 一晶片102及第二晶片110;及一封裝膠體13〇，係包覆且填 滿第一晶片102、第一晶片1()2周圍之引線刚及引線塾⑽、 間隔件m、第二晶片110及第二晶片11〇周圍之引線112盥 引線墊113間之空隙。 〃 白口之一曰日封裝體係利用間隔件m支撐封裝體上層之第 二晶片11G，使第二晶片m不至壓迫到第—晶片 然而，習知之_件m在制均諸 尺寸必須小於下層之第-晶片 200828561 線步驟（Wire Bonding);但，倘若間隔件12 110 裂；2、門里^^ 小之間隔件121上而導致第二晶片no斷 支撐力、替θ位置會受引線綱影響，會造成第二晶片⑽之 :：’而使仔第二晶片110傾斜下垂進而壓迫第一 及苐-晶片102周圍之引線辦；3、間隔件121: ，、，曰决，但弟一晶片Π0又已黏附於間隔件121之上，要 另121係為—非常困難之步驟，且非常容易損傷第二晶片⑽。 在^日^部份之堆疊式晶片封裝係為單邊設置咖件⑵之結構， 曰 時，谷易向下傾斜並壓迫到下層之引線104，導致下層第一 j .1〇2及其周邊之引、線104容易斷裂或與引線墊105脫落，造成電 性訊號之不連貫及封裝體的不&率增加。 【發明内容】 ^ 了解決上述問題，本發明目的之一係在提供一種堆疊式晶 片封裝結構’其聽上下兩層電子元件間安設—具餘性之支撐件， 用支撐件之!纟性包覆下層之電子元件及其周邊之彳丨線，並提供支 上層電子元件之力量。 〇本發明之又一目的係在提供一種堆疊式晶片封裝結構，透過支 撐件之設置，由於支撐件之黏性特性，可有效避免因上層電子元件壓 迫下層電子元件周圍之引線而導致封裝體良率不好之風險，進而可提 升產能、增加市場競爭力。 為了達到上述目的，本發明之一實施例提供一種堆疊式晶 片封裝結構，包含··一承載件，具有一主動面；一第一電子元件， 係"又置於主動面上，且利用一黏著物與主動面固接；複數個第 200828561 一引線墊，係設置於主動面上；複數條第一引線，係分別設置 於第—引線墊上，且連接第一電子元件，用以電性連接第/電 子疋件及承載件；一第二電子元件，其中，第二電子元件之/ 下表面具有一支撐件，用以包覆第一電子元件、第一引線蟄及 第一弓I線，並覆蓋部分主動面；複數個第二引線墊，係設置於 暴露出之主動面上；複數條第二引線，係分別設置於第二引線 墊上，且連接第二電子元件，用以電性連接第二電子元件及承 載件；以及一封裝膠體，係包覆第二電子元件、第二引線墊、 第二引線及支撐件。 以下藉由具體實施例配合所附的圖式詳加說明，當更容易瞭解本 發明之目的、技術内容、特點及其所達成之功效。 【實施方式】 以下係以-較佳實施例來·本發.堆疊式⑼封裝結構。200828561 IX. Description of the Invention: [Technical Field] The present invention relates to a chip package structure, and more particularly to a stacked chip package structure. [Prior Art] The advancement of semiconductor manufacturing process and the increasing demand for thin and light features of electronic products have made it possible to reduce the size of chip packages and become the main point of competition among manufacturers, from turning to single-chip packages. Multi-chip packages, such as stacked wafer packages, reduce the area of the chip package on the printed circuit board. Please refer to the figure for a cross-sectional view of a conventional stacked chip package structure. As shown in the figure, the stacked chip package system comprises: a substrate 101 having an active surface; a first wafer 102 disposed on the active surface and fixed to the active surface by an adhesive material 103 A spacer 121 is fixed on the substrate by an adhesive 122 and disposed on one side of the first wafer 102. A second wafer 11 is fixed to the spacer by an adhesive. Above the 121; a plurality of lead pads (wwbondpad) 1〇5, 113 are disposed on the active surface; a plurality of leads 104, U2 are respectively disposed on the lead pads 1〇5, 113, and are respectively connected to the first wafer 102 And the second wafer i10 is electrically connected to the substrate ιι and the first wafer 102 and the second wafer 110 respectively; and an encapsulant 13 包覆 is coated and filled with the first wafer 102 and the first wafer 1 ( The gap between the lead wire around the wire 2 and the lead wire 塾 (10), the spacer m, the second wafer 110, and the lead wire 112 around the second wafer 11 turns.曰 One of the white port packaging system supports the second wafer 11G of the upper layer of the package by using the spacer m, so that the second wafer m is not pressed to the first wafer. However, the conventional size must be smaller than the lower layer. The first-wafer 200828561 wire bonding (wire bonding); however, if the spacer 12 110 is cracked; 2, the small spacers 121 in the door cause the second wafer no breaking support force, and the θ position is subject to the lead The effect is that the second wafer (10) is::' and the second wafer 110 is tilted down to press the lead wires around the first and second wafers 102; 3. The spacers 121: ,,,,,,,, The wafer Π0 has been adhered to the spacer 121 again, and the other 121 is a very difficult step, and the second wafer (10) is very easily damaged. The stacked chip package in the ^^^ part is a structure in which the coffee maker (2) is unilaterally arranged, and when it is squat, the valley is inclined downward and pressed to the lower layer lead 104, resulting in the lower first layer j.1〇2 and its surroundings. The lead wire 104 is easily broken or peeled off from the lead pad 105, causing inconsistency in electrical signals and an increase in the ratio of the package. SUMMARY OF THE INVENTION In order to solve the above problems, one of the objects of the present invention is to provide a stacked chip package structure, which is mounted between two upper and lower electronic components, and has a support member with a balance. The underlying electronic component and its surrounding turns are coated and the power of the upper electronic component is provided. Another object of the present invention is to provide a stacked chip package structure. Through the arrangement of the support member, due to the adhesive property of the support member, the upper layer electronic component can be effectively prevented from being pressed by the lead wires around the lower electronic component. The risk of a bad rate can further increase production capacity and increase market competitiveness. In order to achieve the above object, an embodiment of the present invention provides a stacked chip package structure, comprising: a carrier having an active surface; a first electronic component, placed on the active surface, and utilizing a The adhesive is fixed to the active surface; a plurality of 200828561 lead pads are disposed on the active surface; a plurality of first leads are respectively disposed on the first lead pads, and the first electronic components are connected for electrical connection a second electronic component, wherein the second electronic component has a support member for covering the first electronic component, the first lead wire, and the first wire, And covering a part of the active surface; a plurality of second lead pads are disposed on the exposed active surface; a plurality of second leads are respectively disposed on the second lead pads, and are connected to the second electronic component for electrical connection a second electronic component and a carrier; and an encapsulant covering the second electronic component, the second lead pad, the second lead, and the support. The purpose, technical contents, features, and effects achieved by the present invention will become more apparent from the detailed description of the appended claims. [Embodiment] The following is a stacked (9) package structure in a preferred embodiment.

210，用以電性連接 封裝膠體230，係包 7 200828561 第二？丨線墊212、第二引線211及支樓 二電支撐件220係為一具有黏性之膠體，在第 第一電子元之Μ圓製造過程令，支撐件220即同時形成於 之下表面，隨著製程切單、黏晶直到封裝。 承载中’首先係將第-電子元件搬放置於 f 覆弟二電子元件2i〇 件 220 〇 複數個引腳(圖中未:見=:步^ 20】）透過複數條第一引線204與承載件 子元件=及^一引線塾施連接，以達到電性連接第一電 外部電子4 載件2G1之目的，以俾利堆疊式晶片封裝體與 ==。Ιΐ示:如印刷電路板)之訊號連接。待第 第_雷 111 6X70畢後’接著將第二電子元件210堆疊至 一支·Ρ件io 2〇2之上方，此時由於第二電子元件210係包含 2〇=Γ»此只需將第二電子元件21°往第-電子元件 將笛士 利用支樓件220之彈性膠體特性，支樓件220 元件搬、第—引線2〇4及第—引線塾205包覆住， = = = , 使得支撐件22〇可提供承載第二電子 里’並保濩第-引線204不會因為第二電子元件 成、,Λ迫而斷裂’或者是與第一引線墊205之連接脫落，造 成虎路徑之錢貫，進㈣響«體之良率之情事。 請參閱第3 g)，所示為依據本發明所實施一實施例之堆疊式薄 型小尺寸晶片封裝結構剖面示意圖。如圖中所示，堆疊式薄型小尺寸 b曰片封衣結構（Thm Small Qutline paekage,TS〇p)係包含·—承載件 301 (於此實施例中，承載件301係為一引線架Lead_frame)， 具有-主動面；-第-電子元件302 (於此實施例中，第一電 子7L件302係為-晶片），係設置於主動面上，且利用一黏著 物303铃主動面固接，複數個第一引線塾奶，係設置於主動 8 200828561 面上；複數條第—引線3G4 (如：金線），係分別設置於第— 电子疋件302及承載件斯；—第二電子元件加（於 例中，第二電子元件31〇係為—晶片），其中，第二電子元 下表面具有—支撐件32() ’用以包覆第—電子元件 广、、第一引線墊305及第一引線3〇4，並覆蓋承載件如1之 4分主動面；複數個H_312,躲置 面上；複數條第二引線3U (如：金線），係分別設 f210, used to electrically connect the encapsulant 230, the package 7 200828561 second? The wire pad 212, the second wire 211 and the second electrical support member 220 are a viscous colloid. During the manufacturing process of the first electronic component, the support member 220 is simultaneously formed on the lower surface. As the process is singulated, the die is bonded until it is packaged. In the carrying case, the first electronic component is first placed on the f-electronic electronic component 2i component 220, and the plurality of pins (not shown in the figure: see: step: 20) are transmitted through the plurality of first leads 204 and the bearing. The component components = and ^ a wire connection are connected to electrically connect the first electrical external electronic 4 carrier 2G1 to benefit the stacked chip package and ==. A signal connection such as a printed circuit board. After the first _Ray 111 6X70 is completed, then the second electronic component 210 is stacked above the Ρ 2 〇 2 〇 2, at this time, since the second electronic component 210 contains 2 〇 = Γ » The second electronic component 21° to the first electronic component encapsulates the elastic colloidal characteristics of the branch member 220, the component 220, the first lead 2〇4 and the first lead 205, === , so that the support member 22 can provide the second electronic device and ensure that the first lead wire 204 does not break due to the second electronic component, or the connection with the first lead pad 205, causing the tiger The path of the money, into (four) ringing the body of the rate of love. Referring to Fig. 3g), there is shown a cross-sectional view of a stacked thin small size chip package structure in accordance with an embodiment of the present invention. As shown in the figure, the stacked thin small-sized b-block sealing structure (Thm Small Qutline paekage, TS〇p) includes a carrier 301 (in this embodiment, the carrier 301 is a lead frame Lead_frame). And having an active surface; the first electronic component 302 (in this embodiment, the first electronic 7L device 302 is a wafer) is disposed on the active surface and is fixed by an adhesive 303 ring active surface a plurality of first lead wires are set on the active 8 200828561 surface; a plurality of first lead wires 3G4 (eg, gold wires) are respectively disposed on the first electronic component 302 and the carrier member; the second electron The component is added (in the example, the second electronic component 31 is a wafer), wherein the lower surface of the second electronic component has a support member 32()' for covering the first electronic component, and the first lead pad 305 and the first lead 3〇4, and cover the carrier part such as 1 4 points active surface; a plurality of H_312, hiding surface; a plurality of second lead 3U (such as: gold line), respectively set f

及2接第二電子元件31°’用以電性連接第二 Γ件301; 一封裝谬體330，係包覆第二電 子讀310、苐二引線塾312、第二弓^線311及支撐件32〇電 ==裝膠體340，設置於承载件301之另-表面與封裝膠 與上述第2圖所閣述之實施例相同的，支撐件3 具有黏性之膠體，在第二電子元件31G之晶圓製造過程^、 撐，320即同時形成於第二電子元件31()之下表面，隨 切早、黏曰曰曰直到封褒。薄型小尺寸晶片之堆疊封裝過程係2 圖所闡述之實施例大致相同，故在此不再贅述；惟，與上述 2圖所闡述之實施例之差異係在於：薄型小尺寸晶片之堆 過程係將第一電子元件3〇2、第二電子元件310、支撐件 引線* 305及第二引線塾312固設於—引線架（本實施例 即為承載件301)上，再透過於引線架之另一表面填充第二 封裝膠體340，以封住整個堆疊式薄型小尺寸晶片封裝體，並暴露 出部分引線架，以俾利薄型小尺寸晶片封裝體與外部電子裝置（圖 =未示，如印刷電路板）之連接。可以理解的，支撐件<32〇; 提供承載第二電子元件310之力量，並保護第一引線3〇4不會 因為第二電子元件31G之壓迫而斷裂，或者是與 ^ 305之連接脫落。 Μ踝墊 9 200828561 田凊繼續參閱第4圖，所示為依據本發明所實施又一實施例之堆 豐式球柵陣列晶片封裝結構剖面示意圖。與上述實施例不同的地方係 在於：於此實施例中，承載件撕係'為一基板（_她），第子 及第二電子元件41G皆為晶片，且堆疊式球栅_晶片封裝 (Ball Gnd Array Package, BGA Package) (如：錫球）’固設於基板（即承載件撕）之另一表面，師 430對應設置；堆疊式球柵陣列晶片封裝結構透過支撐件42〇可提供 承載第二電子元件410之力量，並保護第一引線樹不會And 2 connected to the second electronic component 31°' for electrically connecting the second component 301; a package body 330 covering the second electronic read 310, the second lead wire 312, the second bow wire 311 and the support The member 32 is electrically charged with the colloid 340 disposed on the other surface of the carrier 301 and the encapsulant is the same as the embodiment described in the second embodiment, the support member 3 has a viscous gel, and the second electronic component The 31G wafer fabrication process, the support, 320 is simultaneously formed on the lower surface of the second electronic component 31 (), with the early cutting, sticking until the sealing. The embodiment of the thin and small-sized wafer stacking process is substantially the same, and therefore will not be described herein; however, the difference from the embodiment described in the above 2 is that the thin-type small-sized wafer stacking process is The first electronic component 3〇2, the second electronic component 310, the support lead*305 and the second lead 312 are fixed on the lead frame (the carrier 301 in this embodiment), and then passed through the lead frame. The other surface is filled with the second encapsulant 340 to seal the entire stacked thin small-sized chip package and expose part of the lead frame to benefit the thin small-sized chip package and the external electronic device (Fig. = not shown, The connection of the printed circuit board). It can be understood that the support member <32〇; provides the power to carry the second electronic component 310, and protects the first lead 3〇4 from being broken due to the compression of the second electronic component 31G, or is disconnected from the ^305. . Μ踝垫 9 200828561 Tian Wei continued to refer to Fig. 4, which is a cross-sectional view showing a stacked-up ball grid array chip package structure according to still another embodiment of the present invention. The difference from the above embodiment is that in this embodiment, the carrier tearing is 'a substrate, the first and second electronic components 41G are all wafers, and the stacked ball grid_chip package ( Ball Gnd Array Package, BGA Package) (eg: solder ball) is fixed on the other surface of the substrate (ie, the carrier tear), and the teacher 430 is correspondingly disposed; the stacked ball grid array chip package structure is provided through the support member 42 Carrying the power of the second electronic component 410 and protecting the first lead tree does not

第二電子元件41〇之壓迫而斷裂，或者是與第一引線墊二之 連接脫落。 請同時參閱第5A圖及第5B圖，所示分別為依據本發明所實 施之不同實施例之堆疊式晶片封裝結構俯視示意圖。由於支撐件別 係為-具有彈性之勝體’可保護下層之第—電子元件撕狀周邊之 第-引線5〇4 ;因此，可以理解的，第—電子元件5〇2在承齡5〇1上 之位置、數量、形狀或大小皆不受限，並不岐―轉在第二電子元 件51〇應力中心點之位置上，可依照晶片封料局之需求而調整。 另外，在上層電子70件之晶圓製造過程中，倘若支撐件之厚度超 «I期，可於封裝過程中’加重堆疊上層電子元件時所f之向下壓力， 以控制堆疊式晶㈣裝體之總厚度，，補晶隨造過財之不良。 綜合上述，上述實施例中所_之承載件、第一電子元件' 二電子元件可依實際上之應用調整為：基板、⑽架、晶片、中㈣ (Interposer)、矽晶圓或印刷電路板之任一及其任咅之組人。 以上所述之實施例僅係為說明本發明之技術思相及特 點’其目的在使熟習此項技藝之人士能夠瞭解本發明之时並 據以實施’ mx之限定本發明之相，即大凡依本發 明所揭示之精神所作之均等變化或修飾，仍應涵蓋在本發明之 專利範圍内。 10 200828561 【圖式簡單說明】 第1圖所7F為習知之堆疊式晶片封裝結構勤示意圖。 第2圖所不為依據本翻所實施—實闕之堆疊式晶片封裝結構剖面 不意圖。 第3圖所示為依據本發明所實施—實關之堆疊式_小尺寸晶片封 裝結構剖面示意圖。 第4圖所7F為依據本發贿實施又—實施例之堆疊式球_列晶片封 裝結構剖面示意圖。The second electronic component 41 is pressed or broken, or is disconnected from the first lead pad 2. Please refer to FIG. 5A and FIG. 5B simultaneously, which are schematic top views of stacked chip package structures according to different embodiments of the present invention. Since the support member is a flexible body that can protect the first layer of the lower layer of the lower layer - the lead wire 5〇4; therefore, it can be understood that the first electronic component 5〇2 is at the age of 5〇. The position, number, shape or size of 1 is not limited, and it does not mean that it is transferred to the position of the stress center of the second electronic component 51, and can be adjusted according to the requirements of the wafer sealing bureau. In addition, in the wafer manufacturing process of the upper electronic 70 pieces, if the thickness of the support member exceeds the stage I, the downward pressure of the upper electronic component can be increased during the packaging process to control the stacked crystal (four) The total thickness of the body, the crystal is not good with the creation of wealth. In summary, the carrier of the above embodiment, the first electronic component 'two electronic components can be adjusted according to the actual application: substrate, (10) shelf, wafer, intermediate (inter), germanium wafer or printed circuit board Any one of them and their group. The above-described embodiments are merely illustrative of the technical spirit and characteristics of the present invention. The purpose of the present invention is to enable those skilled in the art to understand the present invention and to implement the 'mx'. Equivalent variations or modifications made in accordance with the spirit of the invention should still be included in the scope of the invention. 10 200828561 [Simplified Schematic] FIG. 1F is a schematic diagram of a conventional stacked chip package structure. Figure 2 is not implemented in accordance with the present embodiment - the stacked chip package structure profile is not intended. Figure 3 is a cross-sectional view showing the stacked-small-size wafer package structure implemented in accordance with the present invention. Fig. 4 is a cross-sectional view showing a stacked ball-column chip package structure according to the present invention.

第5A圖所示為依據 俯視示意圖。 本發明所實施之一實施例之堆疊式晶片封裝結構 第5B圖所示為依據 俯視不意圖。 本發明所實施之不同實施例之堆疊式晶片封裝結構 【主要元件符號說明】 101 基板 102 第一晶片 103、111、122 黏著物 104 、 112 引線 105 、 113 引線墊 110 第二晶片 121 間隔件 130 封裝膠體 201、301、401、501 承載件 202、302、402、502 第一電子元件 203 > 303 黏著物 11 200828561Figure 5A shows a schematic view of the top view. The stacked chip package structure of one embodiment of the present invention is shown in Fig. 5B as a plan view. Stacked wafer package structure of different embodiments implemented by the present invention [Main component symbol description] 101 substrate 102 first wafer 103, 111, 122 adhesive 104, 112 lead 105, 113 lead pad 110 second wafer 121 spacer 130 Encapsulant 201, 301, 401, 501 carrier 202, 302, 402, 502 first electronic component 203 > 303 adhesive 11 200828561

204、304、404、504 第一引線 205、305、405 第一引線墊 210、310、410、510 第二電子元件 211 ^ 311 第二引線 212 、 312 第二引線墊 220、320、420、520 支撐件 230、330、430 封裝膠體 340 第二封裝膠體 440 銲球 12204, 304, 404, 504 first lead 205, 305, 405 first lead pad 210, 310, 410, 510 second electronic component 211 ^ 311 second lead 212, 312 second lead pad 220, 320, 420, 520 Support 230, 330, 430 encapsulant 340 second encapsulant 440 solder ball 12

Claims (1)

200828561 十、申請專利範圍： 1. 一種堆疊式晶片封裝結構，包含： 一承載件’包含一主動面； 一第一電子元件，係設置於該主動面上，且利用一黏著物與 該主動面固接； 複數個第一引線墊，係設置於該主動面上； 複數條第一引線，係分別設置於該些第一引線墊上，且連接 該第一電子元件，用以電性連接該第一電子元件及該承載件； 一第二電子元件，其中，該第二電子元件之一下表面具有一 支撐件，用以包覆該第一電子元件、該些第一引線墊及該些第 一引線，並覆蓋部分該主動面； 複數個第二引線墊，係設置於暴露出之該主動面上； 複數條第二引線，係分別設置於該些第二引線墊上，且連接 該第二電子元件，用以電性連接該第二電子元件及該承載件； 及 一封裝膠體，係包覆該第二電子元件、該些第二引線墊、該 些第二引線及該支撐件。 2. 如請求項1所述之堆疊式晶片封裝結構，其中，該支撐件係為一具 有黏性之膠體。 3. 如請求項1所述之堆疊式晶片封裝結構，其中，該承載件係為一基 板。 4. 如請求項3所述之堆疊式晶片封裝結構，更包含複數個銲球，係固 設於該基板之另一表面，與該封裝膠體對應設置。 5. 如請求項4所述之堆疊式晶片封裝結構，其中，該些銲球之材質係 為錫。 6. 如請求項3所述之堆疊式晶片封裝結構，其中，該第一電子元件係 為一晶片。 13 200828561 7. 如請求項3所述之堆疊式晶片封裝結構，其中，該第二電子元件係 為一晶片。 8. 如請求項3所述之堆疊式晶片封裝結構，其中，該第一電子元件係 為中介層、引線架、基板、石夕晶圓、或印刷電路板之任一。 9. 如請求項3所述之堆疊式晶片封裝結構，其中，該第二電子元件係 為中介層、引線架、基板、矽晶圓、或印刷電路板之任一。 10. 如請求項1所述之堆疊式晶片封裝結構，其中，該承載件係為一引 線架。 11. 如請求項10所述之堆疊式晶片封裝結構，更包含一第二封裝膠 體，係設置於該引線架之另一表面與該封裝膠體對應設置。 12. 如請求項1所述之堆疊式晶片封裝結構，其中，該第一電子元件係 為中介層、引線架、晶片、基板、矽晶圓、或印刷電路板之任一。 13. 如請求項1所述之堆疊式晶片封裝結構，其中，該第二電子元件係 為中介層、引線架、晶片、基板、石夕晶圓、或印刷電路板之任一。 14. 如請求項1所述之堆疊式晶片封裝結構，其中，該些第一引線之材 質係為金。 15. 如請求項1所述之堆疊式晶片封裝結構，其中，該些第二引線之材 質係為金。 14200828561 X. Patent Application Range: 1. A stacked chip package structure comprising: a carrier member comprising an active surface; a first electronic component disposed on the active surface and utilizing an adhesive and the active surface a plurality of first lead pads are disposed on the active surface; a plurality of first leads are respectively disposed on the first lead pads, and are connected to the first electronic component for electrically connecting the first An electronic component and a second electronic component, wherein a lower surface of the second electronic component has a support member for covering the first electronic component, the first lead pads, and the first a lead wire covering a portion of the active surface; a plurality of second lead pads disposed on the exposed active surface; a plurality of second leads disposed on the second lead pads and connected to the second electron a component for electrically connecting the second electronic component and the carrier; and an encapsulant covering the second electronic component, the second lead pads, the second leads, and the support . 2. The stacked wafer package structure of claim 1, wherein the support member is a viscous colloid. 3. The stacked wafer package structure of claim 1, wherein the carrier is a substrate. 4. The stacked chip package structure of claim 3, further comprising a plurality of solder balls mounted on the other surface of the substrate and disposed corresponding to the encapsulant. 5. The stacked chip package structure of claim 4, wherein the solder balls are made of tin. 6. The stacked chip package structure of claim 3, wherein the first electronic component is a wafer. The stacked chip package structure of claim 3, wherein the second electronic component is a wafer. 8. The stacked chip package structure of claim 3, wherein the first electronic component is any one of an interposer, a lead frame, a substrate, a lithographic wafer, or a printed circuit board. 9. The stacked chip package structure of claim 3, wherein the second electronic component is any one of an interposer, a lead frame, a substrate, a germanium wafer, or a printed circuit board. 10. The stacked chip package structure of claim 1, wherein the carrier is a lead frame. 11. The stacked chip package structure of claim 10, further comprising a second encapsulant disposed on the other surface of the lead frame and corresponding to the encapsulant. 12. The stacked chip package structure of claim 1, wherein the first electronic component is any one of an interposer, a lead frame, a wafer, a substrate, a germanium wafer, or a printed circuit board. 13. The stacked chip package structure of claim 1, wherein the second electronic component is any one of an interposer, a lead frame, a wafer, a substrate, a Shihwa wafer, or a printed circuit board. 14. The stacked chip package structure of claim 1, wherein the first leads are of gold. 15. The stacked chip package structure of claim 1, wherein the second leads are of a gold material. 14
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CN103793691A (en) * 2014-01-28 2014-05-14 深圳市汇顶科技股份有限公司 Fingerprint identification device and mobile terminal with same
TWI578467B (en) * 2014-11-21 2017-04-11 美光科技公司 Memory devices with controllers under memory packages and associated systems and methods

Cited By (8)

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Publication number Priority date Publication date Assignee Title
CN103793691A (en) * 2014-01-28 2014-05-14 深圳市汇顶科技股份有限公司 Fingerprint identification device and mobile terminal with same
CN106407954A (en) * 2014-01-28 2017-02-15 深圳市汇顶科技股份有限公司 Fingerprint identification module, fingerprint identification device and mobile terminal having same
US9971923B2 (en) 2014-01-28 2018-05-15 Shenzhen GOODIX Technology Co., Ltd. Fingerprint identification device and mobile terminal having same
TWI578467B (en) * 2014-11-21 2017-04-11 美光科技公司 Memory devices with controllers under memory packages and associated systems and methods
US9627367B2 (en) 2014-11-21 2017-04-18 Micron Technology, Inc. Memory devices with controllers under memory packages and associated systems and methods
US10128217B2 (en) 2014-11-21 2018-11-13 Micron Technology, Inc. Memory devices with controllers under memory packages and associated systems and methods
US10727206B2 (en) 2014-11-21 2020-07-28 Micron Technology, Inc. Memory devices with controllers under memory packages and associated systems and methods
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