TWI649846B - 具有記憶體封裝下之控制器之記憶體裝置及相關之系統及方法 - Google Patents

具有記憶體封裝下之控制器之記憶體裝置及相關之系統及方法 Download PDF

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TWI649846B
TWI649846B TW106104970A TW106104970A TWI649846B TW I649846 B TWI649846 B TW I649846B TW 106104970 A TW106104970 A TW 106104970A TW 106104970 A TW106104970 A TW 106104970A TW I649846 B TWI649846 B TW I649846B
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Taiwan
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memory
package
controller
packages
substrate
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TW106104970A
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TW201717339A (zh
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倪勝錦
黃宏遠
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美商美光科技公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Abstract

本文揭示具有記憶體封裝堆疊下之控制器之記憶體裝置及相關之系統及方法。在一實施例中，一記憶體裝置經組態以耦合至一主機且可包含一基板、記憶體封裝之一堆疊及定位於該堆疊與該基板之間之一控制器。該控制器可基於來自該主機之命令而管理由該等記憶體封裝儲存之資料。

Description

具有記憶體封裝下之控制器之記憶體裝置及相關之系統及方法
所揭示之實施例係關於具有記憶體封裝及控制器之記憶體裝置。在一些實施例中，本發明係關於包含位於記憶體封裝之一堆疊下之嵌入式控制器之記憶體裝置。
快閃記憶體常用於儲存智慧型電話、導航系統(例如汽車導航系統)、數位相機、MP3播放器、電腦及諸多其他消費型電子裝置之資料。通用串列匯流排(USB)裝置、記憶體卡、嵌入式磁碟機及其他資料儲存裝置通常包含快閃記憶體，此係歸因於快閃記憶體之小外觀尺寸。電子裝置中之專屬記憶體控制器可管理儲存於快閃記憶體上之資料。不幸地，此等專屬記憶體控制器會減少電子裝置中之其他組件之可用空間。為減小電子裝置之大小，可將記憶體控制器整合至主機處理器中以(例如)增加其他電子組件之可用空間。例如，主機處理器可具有管理由快閃記憶體儲存之資料之整合記憶體控制器(IMC)，但此等IMC與特定類型之記憶體相容且通常無法支援新型記憶體，諸如針對未來標準(例如嵌入式多媒體卡(eMMC)標準規格之未來版本)而設計之新「反及」記憶體。由於IMC將電子裝置限制於特定類型之快閃記憶體，所以該等電子裝置無法使用具有較高儲存密度、改良效能或增強功能之新記憶體。 記憶體控制器亦可嵌入於多晶粒記憶體封裝內。例如，習知eMMC記憶體可為具有一嵌入式多媒體卡(MMC)控制器之一單一高容量「反及」封裝(例如具有堆疊晶粒之一「反及」封裝)。該嵌入式MMC控制器可使一主機處理器免於執行需要大量計算資源之「反及」記憶體管理(例如寫入、讀取、擦除、錯誤管理等等)。因為「反及」晶粒具有難以測試之小特徵，所以在封裝之前不測試個別「反及」晶粒。多晶粒「反及」封裝可經測試以識別待捨棄之不佳封裝(例如，具有壞「反及」晶粒之封裝)。不幸地，不佳「反及」封裝中之嵌入式MMC控制器亦被捨棄以導致製造成本增加。
下文將描述記憶體裝置及相關系統及方法之一些實施例之特定細節。術語「記憶體裝置」一般係指具有一封裝基板、一或多個多晶粒記憶體封裝及一控制器之一封裝。該控制器可定位於該等記憶體封裝下且可對各記憶體封裝提供記憶體管理。在一些實施例中，記憶體裝置可為具有適合用於行動裝置(例如智慧型電話、平板電腦、MP3播放器等等)、數位相機、路由器、遊戲系統、導航系統、電腦及其他消費型電子裝置之多晶粒記憶體封裝之快閃記憶體(例如eMMC記憶體、通用快閃儲存器等等)。例如，該等多晶粒記憶體封裝可為(例如)快閃記憶體封裝，諸如「反及」封裝、「反或」封裝等等。熟習相關技術者亦應瞭解，本發明可具有額外實施例，且可在無下文參考圖1至圖6而描述之實施例之一些細節之情況下實踐本發明。 圖1係根據本發明之一實施例而組態之一記憶體裝置100之一橫截面圖。記憶體裝置100可包含一封裝基板104 (「基板104」)、一控制器106及配置成一堆疊之第一、第二、第三及第四多晶粒記憶體封裝108a、108b、108c、108d (統稱為「記憶體封裝108」)。基板104可電耦合至控制器106及記憶體封裝108，使得控制器106介接於記憶體封裝108與一主機(例如一電子裝置之一主機處理器)之間，該主機與記憶體裝置100通信。控制器106可附著至基板104。在一些實施例中，控制器106可定位於記憶體封裝108之堆疊下，使得記憶體裝置100具有一相對較小佔用面積。 控制器106可處置記憶體管理，使得一主機處理器免於執行其他任務。在各種實施例中，控制器106可包含電路、軟體、韌體、記憶體或其等之組合且可經組態以管理快閃記憶體(例如「反及」記憶體、「反或」記憶體等等)。在一些實施例中，控制器106可為包含一半導體基板(諸如矽基板、絕緣體上矽基板、化合物半導體(例如氮化鎵)基板或其他適合基板)之一控制器晶粒，且可具有各種積體電路組件或功能特徵之任何者，諸如動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)、其他形式之積體電路裝置(其包含處理電路、成像組件及/或用於管理記憶體或其他組件之其他半導體裝置)。例如，控制器106可為經組態以與「反及」記憶體一起使用之一多媒體控制器晶粒(例如一MMC控制器晶粒)且可包含電路、暫存器、介面模組(例如用於與主機介接之模組，用於與記憶體封裝介接之模組等等)及/或用於提供所要功能之其他模組。 基板104可包含第一接合墊120及第二接合墊122。第一接合墊120可藉由第一接線140而耦合至控制器106之對應接合墊130，且第二接合墊122可藉由第二接線142而耦合至記憶體封裝108之各者之對應封裝接點132 (識別一者)。在一實施例中，基板104係將控制器106電耦合至各記憶體封裝108之一單一中介層。基板104可包含(例如)具有電連接器144 (以虛線示意性地展示)(諸如金屬跡線、通孔或其他適合連接器)之一印刷電路板、一多媒體卡基板或其他適合中介層。電連接器144可使控制器106、第一接合墊120及/或第二接合墊122彼此耦合及/或經由基板104之下側處之封裝接點150 (識別一者)及互連件152 (識別一者)而耦合至外部電路(圖中未展示)。互連件152可為凸塊接合件或其他適合連接特徵。 控制器106可藉由一黏著劑160而附著至封裝基板104。黏著劑160可為一黏著材料(例如環氧樹脂、黏膠(adhesive paste)等等)、一黏著疊層(例如膠帶、晶粒附著或切塊晶粒附著膜等等)或其他適合材料。第一記憶體封裝108a可藉由覆蓋控制器106及接線140之一黏著劑162而附著至基板104。接著，額外記憶體封裝108b至108d藉由黏著劑164而彼此附接。在一些實施例中，黏著劑160、162、164可包括相同或類似材料。黏著劑162可具有比黏著劑164厚之一厚度以接納控制器106與記憶體封裝108a之間之接線140之部分。黏著劑164之厚度可足夠大以確保接線142穿過相鄰記憶體封裝108之間之間隙166 (被識別者)。記憶體裝置100可進一步包含一封裝殼115，其包括至少部分囊封記憶體封裝108及接線142之一囊封劑116。 圖2係根據本發明之一實施例而組態之一記憶體封裝108之一橫截面圖。記憶體封裝108可包含複數個記憶體半導體晶粒200 (識別一者)及一記憶體封裝基板202 (「封裝基板202」)。封裝基板202可包含複數個第一接合墊208a及複數個第二接合墊208b。第一接合墊208a可耦合至(例如，線接合至)一第一群組之半導體晶粒200 (例如兩組之四個晶粒)之對應接合墊209a (識別一者)，且第二接合墊208b可耦合至(例如，線接合至)一第二群組之半導體晶粒200 (例如兩組之四個晶粒)之對應接合墊209b (識別一者)。在一些實施例中，一陣列之接合墊208a電耦合至各半導體晶粒200之一陣列之接合墊209a。可基於各自接合墊209a、209b之組態、數目及大小而選擇接合墊208a、208b之組態、數目及大小。在一些實施例中，一列接合墊208b電耦合至各半導體晶粒200之一列接合墊209b。封裝基板202可包含(例如)具有電連接器(諸如金屬跡線、通孔或其他適合連接器)之一中介層、一印刷電路板或其他適合基板，該等電連接器包含用於將記憶體封裝108電耦合至基板104 (圖1)之封裝接點132 (例如接合墊)、互連件(例如凸塊接合件)及/或其他特徵。 圖2展示呈一垂直堆疊配置之半導體晶粒200，其中相鄰半導體晶粒200彼此橫向偏移。在其他實施例中，半導體晶粒200可直接垂直堆疊於彼此上(即，無任何橫向偏移)，或呈任何其他適合堆疊配置，且可由半導體基板(諸如矽基板、絕緣體上矽基板、化合物半導體(例如氮化鎵)基板或其他適合基板)形成。半導體晶粒200可為經切割或單一化晶粒且可具有各種積體電路組件或功能特徵之任何者，諸如非揮發性記憶體、快閃記憶體(例如「反及」快閃記憶體、「反或」快閃記憶體等等)、DRAM、SRAM、其他形式之積體電路裝置(例如處理電路、成像組件及/或其他半導體裝置)。儘管所繪示之記憶體封裝108包含16個記憶體晶粒200，但記憶體封裝108亦可為具有16個以上或16個以下記憶體晶粒(例如一個晶粒、兩個晶粒、四個晶粒、八個晶粒、十個晶粒、二十個晶粒等等)之一多晶片封裝。可基於記憶體封裝108之所要儲存容量而選擇晶粒之數目。由於嵌入式控制器106可管理多個記憶體封裝，所以記憶體封裝之一或多者(例如所有記憶體封裝108)可不具有用於記憶體管理之任何嵌入式控制器晶粒。 記憶體封裝108可進一步包含由至少部分囊封半導體晶粒200之堆疊及接線之一囊封劑116 (例如一熱固性材料、一環氧樹脂或其他適合材料)組成之一封裝殼215。封裝殼215可提供免受周圍環境(例如濕度)影響之遮蔽、電隔離(例如接線之間之電隔離)及/或在處置期間對內部組件之保護。 圖3A至圖3E係繪示根據本發明之一實施例之用於組裝各種製造階段中之記憶體裝置100之一方法的橫截面圖。一般而言，控制器106可耦合至基板104且接著第一記憶體封裝108a可耦合至基板104，使得控制器106定位於第一記憶體封裝108a與封裝基板104之間。額外記憶體封裝可堆疊於記憶體封裝108a上。在將記憶體封裝108電耦合至基板104之後，可由囊封劑116囊封記憶體封裝108。下文將詳細討論製造階段之細節。 參考圖3A，可沿基板104 (例如具有電路之一矽晶圓)之一上表面240定位第一接合墊120及第二接合墊122，且可沿基板104之一下表面242定位封裝接點150。控制器106通常具有比封裝108小之一佔用面積，因此，控制器106可在堆疊封裝總成108之前附著且電耦合至基板104。有利地，控制器106及其電連接件(例如接線140)不會干擾記憶體封裝108之堆疊及附著。如圖3A中所展示，可將攜載黏著劑160之控制器106放置於基板104之上表面240上，使得控制器106與接合墊120、122隔開以提供用於線接合之足夠空隙。黏著劑160可為晶粒附著黏膠或一黏著元件，例如一晶粒附著膜或一切塊晶粒附著膜(分別被熟習技術者稱為「DAF」或「DDF」)。在一實施例中，黏著劑160可包含一壓力凝固黏著元件(例如膠帶或膜)，當該壓力凝固黏著元件被壓縮超過壓力之一臨限位準時，該壓力設定黏著元件將控制器106黏著至基板104。在另一實施例中，黏著劑160可為藉由曝露於UV輻射而凝固之一UV凝固膠帶或膜。 圖3B展示將控制器106附著至基板104且形成第一接線140之後之記憶體裝置100。控制器106之對置橫向側可具有藉由接線140而耦合至對應接合墊120 (例如一列接合墊120)之一陣列之接合墊130 (例如一列接合墊130)。封裝108a可攜載呈適合於與接線一起使用之一「導線上膜(film-over-wire)」材料之形式之黏著劑162。在其他實施例中，可使用焊料或其他適合直接晶粒附著技術來將控制器106直接耦合至基板104。在此等實施例中，黏著劑162可為DAF或DDF。可將具有黏著劑162之記憶體封裝108a放置於基板104之上表面240上，使得記憶體封裝108a橫向向外延伸超過控制器106之周邊。因而，可在組裝期間將整個控制器106直接定位於記憶體封裝108a與基板104之間。黏著劑162之厚度可足夠大以防止記憶體封裝108a之一下表面243與接線140之間之接觸以避免損壞接線140。此外，可將接合墊120直接定位於記憶體封裝108a下以確保控制器106之電連接件不干擾後續線接合程序。 圖3C展示將記憶體封裝108a附著至基板104且形成第二接線142之後之記憶體裝置100。可使用黏著劑164來將第二記憶體封裝108b附著至第一記憶體封裝108a。額外記憶體封裝(用隱線展示記憶體封裝108c)可堆疊於記憶體封裝108上且電耦合至基板104。黏著劑164之厚度可經選擇以維持相鄰記憶體封裝108之間之一所要距離以避免損壞接線142。例如，黏著劑164可足夠厚以防止接線142與相鄰記憶體封裝108之間之接觸恰好位於此等接線142上。 圖3D展示已藉由接線142而將各記憶體封裝108電耦合至基板104之後之記憶體裝置100。各記憶體封裝108之對置橫向側可具有藉由接線142而耦合至對應接合墊122 (例如一列接合墊122)之一陣列之接合墊132 (例如一列接合墊132)。所繪示之記憶體裝置100具有四個記憶體封裝108。在其他實施例中，記憶體裝置100可攜載更多或更少記憶體封裝108，例如一單一記憶體封裝108、兩個記憶體封裝108、五個記憶體封裝108、八個記憶體封裝108、十個記憶體封裝108、十五個記憶體封裝108等等。記憶體裝置100除包含記憶體封裝108之一或多者之外，亦可包含其他封裝或晶粒，及/或可包含其他封裝或晶粒來代替記憶體封裝108之一或多者。可基於記憶體裝置100之所要功能及尺寸而選擇記憶體封裝及/或晶粒之數目、組態及配置。 記憶體封裝108可配置成一垂直堆疊，使得當自上觀察時，記憶體封裝108相對於彼此而居中。此一對準配置可提供具有一相對較小佔用面積之記憶體裝置100。在其他實施例中，垂直堆疊之記憶體封裝108可經彼此橫向偏移以提供用於接入接合墊132之增大空隙。可基於(例如)線接合程序或其他後續程序而選擇橫向偏移之方向及距離。記憶體封裝108可堆疊成其他配置及組態以提供具有所要總大小之封裝。 圖3E展示囊封劑116至少部分囊封記憶體封裝108之堆疊及接線142 (識別一群組之接線)之後之記憶體裝置100。囊封劑116可包含(例如)一熱固性材料、一樹脂(例如環氧樹脂)或其他適合材料(其提供(例如)機械支撐、免受周圍環境(例如濕度)影響之遮蔽、及/或電隔離(例如接線之間之電隔離))。在一些實施例中，可由囊封劑116完全囊封記憶體封裝108及接線142。在囊封記憶體封裝108之後，處理可繼續至後續製造階段，諸如形成球形接合件、單一化、切塊或其他所要程序。 圖3A至圖3E之製程可提高產品良率，此係因為可在組裝之前測試個別組件。記憶體封裝108可經個別測試以確保各記憶體封裝108具有已知良好晶粒(KGD)。例如，各記憶體封裝108可經測試以測試記憶體晶粒108之各者(圖2)。有利地，記憶體封裝108之基板202 (圖2)可具有適合使用標準測試設備來測試之相對較大連接件。具有KGD之記憶體封裝108可經選擇以用於組裝成封裝，同時可捨棄具有已知不佳晶粒之記憶體封裝108。據此，基板104及控制器106僅與良好記憶體封裝108組裝以提供高產率。此外，基板104可具有用於測試組裝之後之基板104、控制器106、記憶體封裝108及/或其他內部組件之一標準球柵陣列或其他適合特徵(例如測試墊)。可識別且捨棄有缺陷之記憶體裝置100。 圖4係根據本發明之另一實施例而組態之一記憶體裝置300之一橫截面圖。記憶體裝置300可包含大體上類似於結合圖1至圖3E而描述之記憶體裝置100之特徵的特徵。記憶體裝置300可包含藉由接線142 (識別一組)而電耦合至封裝基板104之記憶體封裝108，且控制器106可藉由接線140 (識別一者)而電耦合至封裝基板104。記憶體裝置300亦可包含記憶體封裝108a與基板104之間之一或多個間隔物310。間隔物310可為矽或其他適合材料之經切割或單一化部件，其經定尺寸以將第一記憶體封裝108a定位成略微高於控制器106及接線140。一黏著劑(例如黏膠、DAF、膠帶等等)可用於將間隔物310緊固至基板104及/或記憶體封裝108a。其他類型之間隔物310 (諸如一b-階段樹脂)可用於使記憶體封裝108a與基板104隔開達一所要距離且用於緊固記憶體封裝108a。該b-階段樹脂可經固化以將記憶體封裝108a完全黏著至基板104。 囊封劑116可部分或完全囊封經堆疊之記憶體封裝108及接線142，且囊封劑116亦可延伸至第一記憶體封裝108a與基板104之間之一空腔320中。空腔320可由間隔物310之側壁324、記憶體封裝108a之下表面243及基板104之上表面240界定。在製造期間，囊封劑116可流動至空腔320中以至少部分囊封控制器106及接線140，使得囊封劑116使將控制器106耦合至基板104之電連接件電隔離。 圖5係繪示根據本發明之一實施例之記憶體裝置之一實施方案的一方塊電路圖。一記憶體裝置500可為記憶體裝置100、300之一者或可包含大體上類似於記憶體裝置100、300之特徵的特徵。記憶體裝置500可為管理一主機502與記憶體封裝108之各者之間之資料傳送之一封裝。控制器106可經組態以提供記憶體控制且可包含用於提供功能之一或多個模組520。模組520可包含(但不限於)用於錯誤校正之錯誤校正碼(ECC)模組、用於錯誤偵測之錯誤偵測碼(EDC)模組、耗損均衡模組、用於將邏輯映射至實體區塊之位址映射模組、用於區塊管理(例如不佳區塊管理、備用區塊管理等等)之模組、錯誤復原模組、用於分區保護之模組、用於自控制器106啟動之模組或其他所要模組。控制器106可經由一匯流排510而與主機502介接且可包含經由一記憶體匯流排514而可操作地耦合至記憶體封裝108之一介面506。控制器106可為根據多媒體卡規格(例如規格版本4.4、4.41等等)而設計之一MMC控制器。在一些嵌入式多媒體卡(eMMC)實施例中，控制器106可具有一匯流排510，其提供雙向資料信號(例如用於單位元資料傳送、4位元資料傳送、8位元資料傳送等等之資料信號)，自主機502接收命令信號，對主機502作出回應，及/或時控用於使匯流排傳送同步之信號。 主機502可包含具有處理能力之一裝置且能夠與記憶體裝置500介接。主機502可為一行動裝置之一組件(例如主機控制器、硬體、處理器、驅動器等等)、一個人電腦、一遊戲機或能夠將命令輸入提供至記憶體裝置500之其他電子裝置。控制器106可基於來自主機502之命令輸入而管理資料(例如寫入、讀取、擦除資料)。 本文所描述之記憶體裝置之任何者可併入至諸多更大及/或更複雜系統之任何者(諸如圖6中所示意性地展示之系統600)中。系統600可包含一記憶體裝置602、一電源604、一主機606 (例如I/O驅動器)、一處理器608及/或其他子系統或組件610。記憶體裝置602可為記憶體裝置100、300、500之一者或包含大體上類似於上文所描述之記憶體裝置之特徵的特徵。主機606可包含大體上類似於圖5之主機502之特徵。所得系統600可執行各種功能之任何者，諸如記憶體儲存、資料處理及/或其他適合功能。據此，代表性系統600可為(但不限於)手持式裝置(例如行動電話、平板電腦、數位閱讀器及數位音訊播放器)、電腦、數位相機、電器及車輛(例如汽車、輪船、飛機)。系統600之組件可容納於一單一單元中或分佈於多個互連單元中(例如，透過一通信網路)。若記憶體裝置602係可移除的，則其可由另一記憶體裝置(例如具有更先進功能之一新記憶體裝置)替換。記憶體裝置之各者可具有一嵌入式控制器，其經組態以管理記憶體來避免主機606與內建記憶體之間之不相容。 可基於電子裝置之大小而選擇本文所揭示之記憶體裝置之大小。例如，圖1之記憶體裝置100或圖4之記憶體裝置300可具有約4 mm至約7 mm之一範圍內之一高度、約13 mm至約17 mm之一範圍內之一寬度及約17 mm至約25 mm之一範圍內之一長度。記憶體封裝108 (參閱圖1及圖2)可具有約0.75 mm至約1.5 mm之一範圍內之高度(例如1.2 mm)、約12 mm至約16 mm之一範圍內之寬度及約16 mm至約20 mm之一範圍內之長度。 本文所描述之記憶體裝置可併入至各種類型之儲存裝置中。具有「反及」封裝之記憶體裝置(例如圖1中之記憶體裝置100或圖4中之記憶體裝置300)可併入至USB驅動、記憶體卡、固態磁碟機或其他高密度記憶體儲存裝置中。具有「反或」封裝之記憶體裝置(例如圖1中之記憶體裝置100或圖4中之記憶體裝置300)可為嵌入式裝置之部分。本文所揭示之記憶體裝置可使用不同類型之封裝級封裝(PIP)技術、系統級封裝(SIP)技術或其他所要封裝技術且可具有(例如)球柵陣列。例如，圖1中之記憶體裝置100或圖4中之記憶體裝置300可為具有一標準球柵陣列之封裝。 本文所揭示之至少一些實施例係包括一封裝基板、具有半導體晶粒之複數個堆疊記憶體封裝、一控制器及一囊封劑之一記憶體裝置。該控制器附著至該封裝基板且定位於該等記憶體封裝與該封裝基板之間。該控制器經組態以管理該等記憶體封裝之各者。該囊封劑由該封裝基板攜載且囊封該等記憶體封裝之一或多者。 在一些實施例中，一記憶體裝置包括一基板、用於儲存之複數個堆疊構件、用於控制之構件、及一囊封劑。用於控制之該構件附著至用於儲存之該等構件且定位於用於儲存之該複數個堆疊構件與該基板之間。用於控制之該構件經組態以管理用於儲存之該等構件之各者。用於儲存之各構件可為一記憶體封裝。該囊封劑可由該基板攜載且可囊封用於儲存之該複數個堆疊構件。 在一些實施例中，一多媒體裝置包括一中介層、電耦合至該中介層之記憶體構件之一堆疊、及一多媒體控制構件。該多媒體控制構件附著至該中介層且定位於記憶體構件之該堆疊與該中介層之間。該多媒體控制構件可經組態以管理一主機與該等記憶體構件之各者之間之資料傳送。一囊封劑可囊封記憶體構件之該堆疊。各記憶體構件可為一多晶片記憶體封裝。 應自上文瞭解，本文已出於繪示目的而描述本發明之特定實施例，但可在不背離本發明之情況下作出各種修改。若內文容許，則單數或複數術語亦可分別包含複數或單數術語。除非用語「或」與一明示(其指示該用語應僅限於意謂排除與一系列之兩個或兩個以上項目有關之其他項目之一單一項目)相關，否則此一系列中之「或」之使用應被解譯為包含(a)該系列中之任何單一項目、(b)該系列中之所有項目或(c)該系列中之項目之任何組合。此外，術語「垂直」、「橫向」、「上」及「下」可係指記憶體裝置中之特徵鑑於圖中所展示之定向之相對方向或位置。然而，此等術語應被廣義地解釋為包含具有其他定向之記憶體裝置及其組件(諸如，在其等之側上翻轉或經反轉)。 亦可在其他實施例中組合或消除特定實施例之內文中所描述之新技術之某些態樣。此外，儘管已在該等實施例之內文中描述與新技術之某些實施例相關之優點，但其他實施例亦可展現此等優點且未必需要所有實施例展現落於本發明之範疇內之此等優點。據此，本發明及相關技術可涵蓋本文未明確展示或描述之其他實施例。
100‧‧‧記憶體裝置
104‧‧‧封裝基板
106‧‧‧控制器
108‧‧‧記憶體封裝/封裝總成
108a‧‧‧第一記憶體封裝
108b‧‧‧第二記憶體封裝
108c‧‧‧第三記憶體封裝
108d‧‧‧第四記憶體封裝
115‧‧‧封裝殼
116‧‧‧囊封劑
120‧‧‧第一接合墊
122‧‧‧第二接合墊
130‧‧‧接合墊
132‧‧‧封裝接點
140‧‧‧第一接線
142‧‧‧第二接線
144‧‧‧電連接器
150‧‧‧封裝接點
152‧‧‧互連件
160‧‧‧黏著劑
162‧‧‧黏著劑
164‧‧‧黏著劑
166‧‧‧間隙
200‧‧‧記憶體半導體晶粒
202‧‧‧記憶體封裝基板
208a‧‧‧第一接合墊
208b‧‧‧第二接合墊
209a‧‧‧接合墊
209b‧‧‧接合墊
215‧‧‧封裝殼
240‧‧‧上表面
242‧‧‧下表面
243‧‧‧下表面
300‧‧‧記憶體裝置
310‧‧‧間隔物
320‧‧‧空腔
324‧‧‧側壁
500‧‧‧記憶體裝置
502‧‧‧主機
506‧‧‧介面
510‧‧‧匯流排
514‧‧‧記憶體匯流排
520‧‧‧模組
600‧‧‧系統
602‧‧‧記憶體裝置
604‧‧‧電源
606‧‧‧主機
608‧‧‧處理器
610‧‧‧子系統/組件
圖1係根據本發明之一實施例而組態之一記憶體裝置之一橫截面圖。 圖2係根據本發明之一實施例而組態之一多晶粒記憶體封裝之一橫截面圖。 圖3A至圖3E係繪示根據本發明之一實施例之各種製造階段中之一記憶體裝置的橫截面圖。 圖4係根據本發明之另一實施例而組態之一記憶體裝置之一橫截面圖。 圖5係繪示根據本發明之一實施例之適合用於記憶體裝置之一實施方案的一方塊電路圖。 圖6係包含根據本發明之實施例而組態之一記憶體裝置的一系統之一示意圖。

Claims (12)

  1. 一種半導體裝置，其包括：一封裝基板；一控制器，其附著至該封裝基板；至少兩個半導體封裝，其附著至該封裝基板且配置於該控制器上方，每一半導體封裝包含複數個半導體晶粒；及一囊封劑材料，其囊封該控制器及該至少兩個半導體封裝。
  2. 如請求項1之半導體裝置，其中該封裝基板包含複數個第一接合墊及複數個第二接合墊，且其中該半導體裝置進一步包含：複數個第一接線，其將該複數個第一接合墊耦合至該至少兩個半導體封裝；及複數個第二接線，其將該複數個第二接合墊耦合至該控制器。
  3. 如請求項1之半導體裝置，其中該控制器經組態以管理傳送至該至少兩個半導體封裝之各者及傳送來自該至少兩個半導體封裝之各者之資料。
  4. 如請求項1之半導體裝置，其中該至少兩個半導體封裝之各者包含一基板、複數個半導體晶粒、及至少部分囊封該複數個半導體晶粒之一封裝殼。
  5. 如請求項1之半導體裝置，其中該至少兩個半導體封裝包含一第一記憶體封裝及一第二記憶體封裝，其中該第一記憶體封裝附著至該封裝基板，且該第二記憶體封裝藉由一晶粒附著黏著劑而附著至該第一記憶體封裝。
  6. 如請求項1之半導體裝置，其中該至少兩個半導體封裝包括快閃記憶體且包含反及(NAND)記憶體及/或反或(NOR)記憶體。
  7. 如請求項1之半導體裝置，其進一步包括在該至少兩個半導體封裝與該封裝基板之間之一間隔物，且其中該間隔物與該控制器橫向隔開。
  8. 一種多媒體裝置，其經組態以耦合至一主機，該多媒體裝置包括：一中介層；多晶片記憶體封裝之一堆疊，其附著且電耦合至該中介層；一多媒體控制器晶粒，其附著至該中介層且定位於多晶片記憶體封裝之該堆疊與該中介層之間；及一囊封劑，其囊封多晶片記憶體封裝之該堆疊及該多媒體控制器晶粒。
  9. 如請求項8之多媒體裝置，其中該多媒體控制器晶粒經組態以管理在該主機與該等多晶片記憶體封裝之各者之間的資料傳送。
  10. 如請求項8之多媒體裝置，其中該多媒體控制器晶粒經組態以提供錯誤校正、區塊管理、耗損均衡及/或實體至邏輯映射。
  11. 如請求項8之多媒體裝置，其中該多媒體控制器晶粒包含耦合至該等多晶片記憶體封裝之各者之一記憶體介面。
  12. 如請求項8之多媒體裝置，其中各多晶片記憶體封裝係一反及(NAND)封裝。
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Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9627367B2 (en) * 2014-11-21 2017-04-18 Micron Technology, Inc. Memory devices with controllers under memory packages and associated systems and methods
KR102359370B1 (ko) * 2015-10-05 2022-02-09 에스케이하이닉스 주식회사 반도체장치
US10873145B2 (en) * 2016-12-29 2020-12-22 Intel Corporation Ground heat sink for dual inline memory module cooling
US20190067248A1 (en) 2017-08-24 2019-02-28 Micron Technology, Inc. Semiconductor device having laterally offset stacked semiconductor dies
US20190067034A1 (en) * 2017-08-24 2019-02-28 Micron Technology, Inc. Hybrid additive structure stackable memory die using wire bond
JP2019153619A (ja) * 2018-02-28 2019-09-12 東芝メモリ株式会社 半導体装置
JP2019165046A (ja) * 2018-03-19 2019-09-26 東芝メモリ株式会社 半導体装置およびその製造方法
US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method
KR20190121560A (ko) 2018-04-18 2019-10-28 삼성전기주식회사 팬-아웃 반도체 패키지
KR102540050B1 (ko) 2018-07-05 2023-06-05 삼성전자주식회사 반도체 패키지
JP7042713B2 (ja) * 2018-07-12 2022-03-28 キオクシア株式会社 半導体装置
US11157213B2 (en) * 2018-10-12 2021-10-26 Micron Technology, Inc. Parallel memory access and computation in memory devices
US20200117449A1 (en) * 2018-10-12 2020-04-16 Micron Technology, Inc. Accelerated Access to Computations Results Generated from Data Stored in Memory Devices
US10461076B1 (en) 2018-10-24 2019-10-29 Micron Technology, Inc. 3D stacked integrated circuits having functional blocks configured to accelerate artificial neural network (ANN) computation
CN109887850B (zh) * 2019-02-18 2021-10-01 长江存储科技有限责任公司 一种3d封装多点焊接的方法及装置、设备及存储介质
US11005501B2 (en) * 2019-02-19 2021-05-11 Micron Technology, Inc. Error correction on a memory device
US11424212B2 (en) 2019-07-17 2022-08-23 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US11424169B2 (en) * 2019-08-08 2022-08-23 Micron Technology, Inc. Memory device including circuitry under bond pads
US11081468B2 (en) * 2019-08-28 2021-08-03 Micron Technology, Inc. Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding and related methods, devices and apparatuses
JP7293056B2 (ja) * 2019-09-12 2023-06-19 キオクシア株式会社 半導体装置およびその製造方法
CN110970414A (zh) * 2019-12-06 2020-04-07 华天科技（西安）有限公司 一种多芯片封装结构及制造方法
KR20220055112A (ko) 2020-10-26 2022-05-03 삼성전자주식회사 반도체 칩들을 갖는 반도체 패키지
US20230015323A1 (en) * 2021-07-19 2023-01-19 Texas Instruments Incorporated Semiconductor package with topside cooling

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130119542A1 (en) * 2011-11-14 2013-05-16 Mosaid Technologies Incorporated Package having stacked memory dies with serially connected buffer dies
US20130161788A1 (en) * 2011-12-22 2013-06-27 Sung-Hoon Chun Semiconductor Package Including Stacked Semiconductor Chips and a Redistribution Layer
US20140097513A1 (en) * 2012-10-08 2014-04-10 Jong-Joo Lee Package-on-Package Type Package Including Integrated Circuit Devices and Associated Passive Components on Different Levels

Family Cites Families (97)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6266753B1 (en) * 1997-07-10 2001-07-24 Cirrus Logic, Inc. Memory manager for multi-media apparatus and method therefor
TW495943B (en) * 2001-04-18 2002-07-21 Siliconware Precision Industries Co Ltd Semiconductor package article with heat sink structure and its manufacture method
US20030127719A1 (en) 2002-01-07 2003-07-10 Picta Technology, Inc. Structure and process for packaging multi-chip
US7049691B2 (en) * 2002-10-08 2006-05-23 Chippac, Inc. Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package
US6930378B1 (en) * 2003-11-10 2005-08-16 Amkor Technology, Inc. Stacked semiconductor die assembly having at least one support
US8970049B2 (en) * 2003-12-17 2015-03-03 Chippac, Inc. Multiple chip package module having inverted package stacked over die
JP2005209882A (ja) 2004-01-22 2005-08-04 Renesas Technology Corp 半導体パッケージ及び半導体装置
US20050269692A1 (en) * 2004-05-24 2005-12-08 Chippac, Inc Stacked semiconductor package having adhesive/spacer structure and insulation
US7253511B2 (en) * 2004-07-13 2007-08-07 Chippac, Inc. Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package
US20070090517A1 (en) 2005-10-05 2007-04-26 Moon Sung-Won Stacked die package with thermally conductive block embedded in substrate
SG135074A1 (en) * 2006-02-28 2007-09-28 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
US8710675B2 (en) * 2006-02-21 2014-04-29 Stats Chippac Ltd. Integrated circuit package system with bonding lands
US7420269B2 (en) * 2006-04-18 2008-09-02 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
JP2007311395A (ja) * 2006-05-16 2007-11-29 Toppan Printing Co Ltd 半導体装置及び半導体装置の製造方法
TW200828561A (en) 2006-12-20 2008-07-01 Powertech Technology Inc Stacked-chip package structure
JP2008166527A (ja) * 2006-12-28 2008-07-17 Spansion Llc 半導体装置およびその製造方法
US8609463B2 (en) * 2007-03-16 2013-12-17 Stats Chippac Ltd. Integrated circuit package system employing multi-package module techniques
US8198716B2 (en) 2007-03-26 2012-06-12 Intel Corporation Die backside wire bond technology for single or stacked die package
JP2008299997A (ja) * 2007-06-01 2008-12-11 Toshiba Corp 半導体記憶装置
US20110024890A1 (en) * 2007-06-29 2011-02-03 Stats Chippac, Ltd. Stackable Package By Using Internal Stacking Modules
TW200915970A (en) * 2007-09-27 2009-04-01 Sanyo Electric Co Circuit device, circuit module and outdoor equipment
TWI402952B (zh) * 2007-09-27 2013-07-21 Sanyo Electric Co 電路裝置及其製造方法
JP2009081325A (ja) * 2007-09-27 2009-04-16 Sanyo Electric Co Ltd 回路装置
US10074553B2 (en) * 2007-12-03 2018-09-11 STATS ChipPAC Pte. Ltd. Wafer level package integration and method
US8399973B2 (en) * 2007-12-20 2013-03-19 Mosaid Technologies Incorporated Data storage and stackable configurations
US7867819B2 (en) * 2007-12-27 2011-01-11 Sandisk Corporation Semiconductor package including flip chip controller at bottom of die stack
JP2009206429A (ja) * 2008-02-29 2009-09-10 Toshiba Corp 記憶媒体
CN102027429B (zh) 2008-04-01 2013-05-08 惠普发展公司，有限责任合伙企业 三维封装件及管理三维封装件中的冷却供应的方法
JP2010010407A (ja) * 2008-06-27 2010-01-14 Toshiba Corp 半導体記憶装置
JP2010021306A (ja) * 2008-07-10 2010-01-28 Hitachi Ltd 半導体装置
US8004093B2 (en) * 2008-08-01 2011-08-23 Stats Chippac Ltd. Integrated circuit package stacking system
JP2010238898A (ja) * 2009-03-31 2010-10-21 Toshiba Corp 半導体装置
KR20100134354A (ko) * 2009-06-15 2010-12-23 삼성전자주식회사 반도체 패키지, 스택 모듈, 카드 및 전자 시스템
US7944029B2 (en) * 2009-09-16 2011-05-17 Sandisk Corporation Non-volatile memory with reduced mobile ion diffusion
JP5593053B2 (ja) * 2009-10-09 2014-09-17 ピーエスフォー ルクスコ エスエイアールエル 半導体装置
KR101624975B1 (ko) 2009-11-17 2016-05-30 삼성전자주식회사 3차원 반도체 기억 소자
KR101665556B1 (ko) * 2009-11-19 2016-10-13 삼성전자 주식회사 멀티 피치 볼 랜드를 갖는 반도체 패키지
TWI502723B (zh) * 2010-06-18 2015-10-01 Chipmos Technologies Inc 多晶粒堆疊封裝結構
KR101686553B1 (ko) * 2010-07-12 2016-12-14 삼성전자 주식회사 반도체 패키지 및 패키지 온 패키지
JP2012129464A (ja) * 2010-12-17 2012-07-05 Toshiba Corp 半導体装置およびその製造方法
US8531021B2 (en) * 2011-01-27 2013-09-10 Unimicron Technology Corporation Package stack device and fabrication method thereof
JP2012238725A (ja) * 2011-05-12 2012-12-06 Toshiba Corp 半導体装置とその製造方法、およびそれを用いた半導体モジュール
US8530350B2 (en) 2011-06-02 2013-09-10 Micron Technology, Inc. Apparatuses including stair-step structures and methods of forming the same
JP2012255704A (ja) * 2011-06-08 2012-12-27 Elpida Memory Inc 半導体装置
KR20120137051A (ko) * 2011-06-10 2012-12-20 삼성전자주식회사 솔리드 스테이트 드라이브 패키지 및 그의 제조 방법
JP2013021216A (ja) * 2011-07-13 2013-01-31 Toshiba Corp 積層型半導体パッケージ
KR101800440B1 (ko) * 2011-08-31 2017-11-23 삼성전자주식회사 다수의 반도체 칩들을 가진 반도체 패키지 및 그 형성 방법
KR101774938B1 (ko) 2011-08-31 2017-09-06 삼성전자 주식회사 지지대를 갖는 반도체 패키지 및 그 형성 방법
US8956968B2 (en) 2011-11-21 2015-02-17 Sandisk Technologies Inc. Method for fabricating a metal silicide interconnect in 3D non-volatile memory
US8780600B2 (en) * 2011-12-07 2014-07-15 Apple Inc. Systems and methods for stacked semiconductor memory devices
JP5840479B2 (ja) 2011-12-20 2016-01-06 株式会社東芝 半導体装置およびその製造方法
KR101798571B1 (ko) 2012-02-16 2017-11-16 삼성전자주식회사 반도체 패키지
JP2013201218A (ja) * 2012-03-23 2013-10-03 Toshiba Corp 半導体装置とそれを用いた半導体モジュール
KR101906269B1 (ko) * 2012-04-17 2018-10-10 삼성전자 주식회사 반도체 패키지 및 그 제조 방법
KR101947722B1 (ko) * 2012-06-07 2019-04-25 삼성전자주식회사 적층 반도체 패키지 및 이의 제조방법
WO2014107848A1 (en) * 2013-01-09 2014-07-17 Sandisk Semiconductor (Shanghai) Co., Ltd. Semiconductor device including independent film layer for embedding and/or spacing semiconductor die
CN108807348A (zh) * 2013-01-28 2018-11-13 晟碟信息科技（上海）有限公司 包括嵌入式控制器裸芯的半导体器件和其制造方法
US20140246781A1 (en) * 2013-03-04 2014-09-04 Kabushiki Kaisha Toshiba Semiconductor device, method of forming a packaged chip device and chip package
US9087846B2 (en) * 2013-03-13 2015-07-21 Apple Inc. Systems and methods for high-speed, low-profile memory packages and pinout designs
JP2014179484A (ja) * 2013-03-15 2014-09-25 Toshiba Corp 半導体記憶装置
KR101999114B1 (ko) * 2013-06-03 2019-07-11 에스케이하이닉스 주식회사 반도체 패키지
US9373527B2 (en) * 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
JP6067541B2 (ja) * 2013-11-08 2017-01-25 株式会社東芝 メモリシステムおよびメモリシステムのアセンブリ方法
US9600413B2 (en) * 2013-12-24 2017-03-21 Intel Corporation Common platform for one-level memory architecture and two-level memory architecture
CN104752491A (zh) * 2013-12-30 2015-07-01 晟碟半导体（上海）有限公司 用于半导体装置的间隔体层和半导体装置
CN104752380B (zh) * 2013-12-31 2018-10-09 晟碟信息科技（上海）有限公司 半导体装置
KR102317263B1 (ko) * 2014-03-11 2021-10-25 삼성전자주식회사 반도체 패키지 및 이를 포함하는 데이터 저장 장치
US9362161B2 (en) * 2014-03-20 2016-06-07 Stats Chippac, Ltd. Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package
US9384128B2 (en) * 2014-04-18 2016-07-05 SanDisk Technologies, Inc. Multi-level redundancy code for non-volatile memory controller
US9406660B2 (en) * 2014-04-29 2016-08-02 Micron Technology, Inc. Stacked semiconductor die assemblies with die support members and associated systems and methods
US9418974B2 (en) * 2014-04-29 2016-08-16 Micron Technology, Inc. Stacked semiconductor die assemblies with support members and associated systems and methods
KR102284652B1 (ko) * 2014-08-28 2021-08-02 삼성전자 주식회사 반도체 패키지
KR102210332B1 (ko) * 2014-09-05 2021-02-01 삼성전자주식회사 반도체 패키지
US9627367B2 (en) * 2014-11-21 2017-04-18 Micron Technology, Inc. Memory devices with controllers under memory packages and associated systems and methods
JP2016178196A (ja) * 2015-03-19 2016-10-06 株式会社東芝 半導体装置及びその製造方法
US10177128B2 (en) * 2015-04-01 2019-01-08 Sandisk Technologies Llc Semiconductor device including support pillars on solder mask
KR102324628B1 (ko) * 2015-07-24 2021-11-10 삼성전자주식회사 솔리드 스테이트 드라이브 패키지 및 이를 포함하는 데이터 저장 시스템
US9947642B2 (en) * 2015-10-02 2018-04-17 Qualcomm Incorporated Package-on-Package (PoP) device comprising a gap controller between integrated circuit (IC) packages
US10163871B2 (en) * 2015-10-02 2018-12-25 Qualcomm Incorporated Integrated device comprising embedded package on package (PoP) device
US10872832B2 (en) * 2015-12-16 2020-12-22 Intel Corporation Pre-molded active IC of passive components to miniaturize system in package
US9978722B2 (en) * 2016-09-29 2018-05-22 Intel Corporation Integrated circuit package assembly with wire end above a topmost component
WO2018058416A1 (en) * 2016-09-29 2018-04-05 Intel Corporation Prepackaged stair-stacked memory module in a chip scale system in package, and methods of making same
US10797039B2 (en) * 2016-12-07 2020-10-06 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a 3D interposer system-in-package module
TWI613772B (zh) * 2017-01-25 2018-02-01 力成科技股份有限公司 薄型扇出式多晶片堆疊封裝構造
US10147705B2 (en) * 2017-02-21 2018-12-04 Micron Technology, Inc. Stacked semiconductor die assemblies with die substrate extensions
US10485125B2 (en) * 2017-12-22 2019-11-19 Western Digital Technologies, Inc. Integrated USB connector and memory device
US11004803B2 (en) * 2018-07-02 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy dies for reducing warpage in packages
US10825696B2 (en) * 2018-07-02 2020-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Cross-wafer RDLs in constructed wafers
JP7042713B2 (ja) * 2018-07-12 2022-03-28 キオクシア株式会社 半導体装置
JP2020053655A (ja) * 2018-09-28 2020-04-02 キオクシア株式会社 半導体装置及び半導体装置の製造方法
US20200211760A1 (en) * 2018-12-28 2020-07-02 Texas Instruments Incorporated Molded inductor with magnetic core having mold flow enhancing channels
US11948917B2 (en) * 2019-04-23 2024-04-02 Intel Corporation Die over mold stacked semiconductor package
US11282791B2 (en) * 2019-06-27 2022-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a heat dissipation structure connected chip package
CN112151528A (zh) * 2019-06-28 2020-12-29 西部数据技术公司 包括相对表面上的接触指的半导体装置
US11282766B2 (en) * 2019-09-27 2022-03-22 Taiwan Semiconductor Manufacturing Company Package structure
US11587918B2 (en) * 2019-12-17 2023-02-21 Micron Technology, Inc. Semiconductor devices, semiconductor device packages, electronic systems including same, and related methods
JP2021125643A (ja) * 2020-02-07 2021-08-30 キオクシア株式会社 半導体装置およびその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130119542A1 (en) * 2011-11-14 2013-05-16 Mosaid Technologies Incorporated Package having stacked memory dies with serially connected buffer dies
US20130161788A1 (en) * 2011-12-22 2013-06-27 Sung-Hoon Chun Semiconductor Package Including Stacked Semiconductor Chips and a Redistribution Layer
US20140097513A1 (en) * 2012-10-08 2014-04-10 Jong-Joo Lee Package-on-Package Type Package Including Integrated Circuit Devices and Associated Passive Components on Different Levels

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