CN106415829B - 用于改良互连性能的保护通孔盖 - Google Patents

用于改良互连性能的保护通孔盖 Download PDF

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CN106415829B
CN106415829B CN201580029003.0A CN201580029003A CN106415829B CN 106415829 B CN106415829 B CN 106415829B CN 201580029003 A CN201580029003 A CN 201580029003A CN 106415829 B CN106415829 B CN 106415829B
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CN106415829A (zh
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M·奈克
P·F·马
S·D·耐马尼
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Applied Materials Inc
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Abstract

形成半导体结构的示例性方法可包括蚀刻通孔以贯穿半导体结构而暴露出第一电路层互连金属。该方法可包括形成覆盖暴露的第一电路层互连金属的材料层。该方法还包括在通孔内形成阻障层且沿着该通孔的底部具有最少覆盖物。该方法附加地包括形成覆盖该材料层的第二电路层互连金属。

Description

用于改良互连性能的保护通孔盖
相关申请的交叉引用
本申请要求2014年5月30日提交的题为“PROTECTIVE VIA CAP FOR IMPROVEDINTERCONNECT PERFORMANCE”的美国非临时专利申请No.14/291,466的优先权。该申请的全部内容出于所有目的通过引用合并于此。
技术领域
本技术涉及半导体系统、工艺及设备。更具体的，本技术涉及用来改良互连结构以降低电迁移的系统、方法及结构。
背景技术
集成电路可包含超过一百万个的微电子场效晶体管，该等晶体管形成在基板上并协同运作以在该电路内执行各种功能。可靠地生产次半微米特征及更小特征是半导体器件的下一代超大规模集成(“VLSI”)及极大规模集成(“ULSI”)的关键技术的一。然而，随着集成电路技术的极限竖直地推动及扩展，VLSI及ULSI技术中的持续缩小的互连件尺寸在处理能力方面有着诸多附加要求。通孔及互连件的可靠形成对于集成电路成功及持续努力提高电路密度及单独基板和管芯的质量而言很重要。
随着特征尺寸缩小，电性连接各式各样的结构的互连件及通孔也缩小。然而，包括互连件及通孔在内的安全特征可能造成整个电路结构中的线路电阻及电阻-电容延迟剧增。此外，电迁移可能随着特征尺寸缩小而变得越来越具破坏性。
因此，需要能够用来生产高质量器件及结构的改良的系统及方法。本技术解决这些需求及其他需求。
发明内容
提出用于改进互连件及通孔性能的系统、结构及工艺。该等系统可为部件提供配置以允许在不改变环境或使结构暴露在周遭环境条件的情况下进行多种工艺。该等结构可包括可降低电迁移的集成电路结构。该等方法可提供对互连件中或跨互连件的原子移动的限制。
形成半导体结构的示例性方法可包括蚀刻通孔以贯穿半导体结构，其中该蚀刻步骤暴露出第一金属。该方法可包括在该暴露的第一金属上形成材料层，及该方法可进一步包括在该材料层上形成第二金属。在一些实施例中，该材料层可包括过渡金属或过渡金属氧化物，且在一些实施例中，该材料层可形成为达到介于约0.5纳米与10纳米之间的厚度。该方法可进一步包括在形成覆盖该材料层的该第二金属之前，先在该蚀刻的通孔内形成阻障层。沿该通孔的侧壁沉积可将该阻障层沉积达第一厚度，及在该材料层上将该阻障层沉积达第二厚度且该第二厚度小于该第一厚度。在所揭示的实施例中，除了该第二金属及阻障层外，该通孔可不包括其他材料。在实施例中，该阻障层可包括过渡金属(诸如锰)，及该第一金属与该第二金属中的至少一者可包含铜。
在所揭示的实施例中，该第一金属可以是用于半导体结构的第一层面的互连件，及该第二金属可以是用于半导体结构的第二层面的互连件。该蚀刻操作可包括使该半导体结构的一部分接触来自电容耦合的等离子体的非反应性离子，且随后使该半导体结构的接触部分暴露于等离子体生成的反应性物种下。该蚀刻操作可作为单镶嵌或双镶嵌工艺的其中一部分来进行，及该半导体结构可在该蚀刻操作与材料层形成操作之间保持处于真空。
还揭示了在集成电路结构中形成保护盖的方法，该等方法包括蚀刻通孔以贯穿半导体结构。该半导体结构可包括至少第一电路层及第二电路层，且可进行该蚀刻步骤以贯穿该第二电路层而暴露该第一电路层内的互连金属。该等方法包括清洗该互连金属，且该等方法也可包括形成覆盖该暴露的第一金属的含钴保护盖。该等方法可又进一步包括沿该通孔的侧壁形成含锰的阻障层。在形成期间，阻障层可形成为覆盖该含钴保护盖达一厚度，该厚度小于沿着该通孔的侧壁所沉积的阻障层厚度的50％。在所揭示的实施例中，该阻障层在侧壁处可具有小于或约为10纳米的厚度。该等方法也可包括使用铜来填充该通孔从而直接覆盖该阻障层。
还揭示了半导体结构，且该等半导体结构可包括第一介电材料层及第一导电层，且该第一导电层至少部分设置在该第一介电材料层中。该等结构可包括第二介电材料层及第二导电层，且该第二导电层至少部分设置在该第二介电材料层中。该等结构也可包括第三导电层，该第三导电层设置在该第一导电层与该第二导电层之间。该第三导电层可包括导电材料，且该导电材料与该第一导电层或该第二导电层所含的材料不同。示例性的结构可包括具有第一部分及第二部分的第二导电层，该第一部分具有第一宽度及该第二部分具有第二宽度，且该第二宽度小于该第一宽度。该第二部分可设置成比该第一部分更接近该第一导电层。该结构还可包括第三介电材料层，该第三介电材料层设置在该第一介电材料层与该第二介电材料层之间。在所揭示的实施例中，该第三导电层可设置在该第一介电材料层与该第三介电材料层之间。该第三导电层可在该第一介电材料层与该第三介电材料层之间的一位置处包括第一厚度，且在该第一导电层与该第二导电层之间的一位置处包括第二厚度，且该第二厚度与该第一厚度不同。
此技术可提供胜过常规系统与技术的诸多好处。例如，随着电迁移效应降低，器件的寿命可能增加。附加优点是改善后的系统可缩短队列时间及减少器件氧化或腐蚀。现配合下述内容及附图更详细地说明这些实施例与其他实施例及该等实施例的特征及所带来的诸多优点。
附图说明
参阅说明书的其余部分及附图，可实现对所揭示的技术的本质与优点的进一步理解。
图1示出根据本技术的示例性处理系统的俯视平面图。
图2示出根据本技术的示例性处理腔室的示意性剖面图。
图3示出根据所揭示技术的实施例的在互连金属上形成选择性金属盖的方法。
图4示出使用减小的阻障层厚度所推算出的临界电流密度效应的图形模型。
图5示出多种阻障层材料的电迁移失效时间的双模型分布图。
图6示出根据所揭示技术的实施例的含有选择性金属盖的集成电路的一部分的示例性剖面结构。
图7示出根据所公开技术的实施例的在互连金属上形成选择性金属盖的方法。
某些附图被包括作为示意图。应明白该等附图仅为了说明的目的，且除非文中特别声明该图依规格比例所做，否则该等附图未按比例绘制。
在该等附图中，相似的部件及/或特征可具有相同的参考标记。此外，可借着在该参考标记后方所附一个用来区分该等相似部件的字母来区别同类型的各个不同部件。若在本说明书中仅使用首位参考标号，则不论该字母为何，该段描述内容皆适用于该等具有相同首位参考标号的相似部件中的任一者。
具体实施方式
本技术包括用于改进互连件与通孔性能及集成电路(“IC”)器件的总体电性能的系统、结构及方法。随着半导体特征尺寸的缩减，可能产生包括电性问题在内等诸多问题。许多IC器件使用铜或钨作为用于器件层内及器件层之间的通孔金属及互连金属。例如使用铜作为通孔金属及互连金属通常包括在沟槽及通孔内使用阻障层，以限制铜扩散进入周围层中，若铜扩散进入周围膜层中会造成短路或器件失效。此外，当器件特征及互连沟槽和通孔的尺寸缩小时，互连金属可能会因沟槽内的高深宽比而遭受不完整的填充。
常规技术经常利用内衬以改进缝隙填充来解决此劣化。然而，沟槽及通孔内含有越多的阻障层及内衬材料，能填入该体积中的铜越少。由于铜的导电性远胜于阻障层及内衬材料，所以通孔或沟槽内的铜越少，有效电阻越大，当组件诸多膜层各处的有效电阻加总在一起时，有效电阻会实质影响总体电阻-电容(“RC”)延迟。可通过薄化阻障层且甚至移除内衬来处理这些问题，然而这么做会让器件可能具有差的电迁移特性，此点将于以下配合图3及图4进行讨论。在另一方面，本技术使用盖层并可使用无阻障层通孔底部效应(barrier-less via bottom effect)来提供背向应力以抵销电迁移，并在通孔内提供最少量的非铜材料以使通孔及线路的电阻减至最小。因此相较于诸多常规设计而言，本发明中所描述的方法及结构提供更佳的性能及成本效益。以下将详细说明这些益处及其他益处。
尽管其余的揭示内容将照惯例举出使用所揭示技术的具体蚀刻工艺，但可轻易明白的是，该等系统及方法可等效地应用于可在所述腔室中进行的沉积工艺及清洁工艺上。因此，不应认为本技术仅可与蚀刻工艺并用。
图1示出根据实施例的由沉积腔室、蚀刻腔室、烘烤腔室及固化腔室所组成的处理系统100的一个实施例的俯视平面图。图1中所示的处理工具100可包含多个工艺腔室114A-114D、移送腔室110、检修腔室116、整合式度量腔室117及一对装载锁定腔室106A-106B。该等工艺腔室可包括与图2中所述者相似的结构或部件以及附加的处理腔室，附加的处理腔室可包括沉积腔室。
为了在该等腔室之间传送基板，移送腔室110可包含机器人传送机构113。传送机构113可具有一对基板传送叶片113A，这对基板传送叶片113A分别附连到可伸缩臂113B的远端。叶片113A可用于运载各个基板进入或离开工艺腔室。操作时，该传送机构113的基板传送叶片(诸如，叶片113A)中的一个可从装载锁定腔室(诸如腔室106A-B)中的一个腔室取出基板W并运载基板W至第一阶段的处理，例如在腔室114A-D中进行如以下所述的蚀刻工艺。若腔室已被占用，机器人可等候至处理完成，且随后使用一个叶片113A从腔室中移出已处理基板并使用第二叶片(未示出)插入新的基板。一旦基板被处理后，随后可移动该基板至第二阶段的处理，第二阶段的处理可包括沉积操作、处理操作，等等。对于每次移动，该传送机构113通常可用一个叶片运载基板并使一个叶片保持空的以执行基板交换。传送机构113可在每个腔室处等候直到完成交换。
一旦在工艺腔室内完成处理后，传送机构113可从最后的工艺腔室中移出基板W并将基板W移送至装载锁定腔室106A-B内的匣盒中。可将该基板从装载锁定腔室106A-B移动至工厂接口104。工厂接口104通常可运作以在装载锁定腔室106A-B与处于大气压洁净环境中的容器装载器105A-C之间移送基板。通常透过空气过滤工艺(诸如，HEPA过滤)来提供工厂接口104中的洁净环境。工厂接口104也可包括基板定向器/对准器(未示出)，在进行处理前可使用基板定向器/对准器适当地对准基板。至少一个基板机器人(诸如机器人108A-B)可定位在工厂接口104中以用于在工厂接口104内的各种位置/场所之间移送基板以及将基板送往与工产接口104连通的其他位置。机器人108A-B可配置成可在外壳104内沿着轨道系统从工厂接口104的第一端行进至工厂接口104的第二端。
处理系统100可进一步包括整合式度量腔室117以提供控制信号，从而可提供对处理腔室内正在进行的任何工艺的适应性控制。整合式度量腔室117可包括各式各样的度量装置以测量各种膜性质(诸如厚度、粗糙度、成分)，且度量装置可进一步能够以自动化方式在真空下表征光栅参数(诸如，临界尺寸、侧壁角度及特征高度)。
现参阅图2，图2示出根据本技术的示例性工艺腔室系统200的剖面图。腔室200可例如用于前述系统100的处理腔室部分114的其中一者或多者。通常，蚀刻腔室200可包括第一电容耦合的等离子体源以实现离子铣削(ion-milling)操作，且蚀刻腔室200可包括第二电容耦合的等离子体源以实现蚀刻操作并且实现任选的沉积操作。腔室200可包括接地的腔室壁240，腔室壁240围绕着卡盘250。在实施例中，卡盘250可以是静电卡盘以在处理期间将基板202夹紧在卡盘250的顶表面，但也可使用已知的其他夹紧机构。卡盘250可包括嵌入式热交换器盘管(coil)217。在示例性实施例中，热交换器盘管217包含一个或更多个热传递流体通道，热传递流体(诸如，乙二醇/水的混合物)可流经热传递流体通道以控制卡盘250的温度且最终控制基板202的温度。
卡盘250可包括网格249，网格249耦接至高压直流(DC)电源248，使得网格249可携带DC偏压电位以实现基板202的静电夹紧。卡盘250可与第一射频(RF)电源耦接，且在一此种实施例中，网格249可与第一RF电源耦接，以使DC电压偏移和RF电压电位跨卡盘250的顶表面上的薄介电层耦合。在示例性实施例中，该第一RF电源可包括第一RF产生器252及第二RF产生器253。RF产生器252及RF产生器253可以以任何工业用频率运作，然而在示例性实施例中，RF产生器252可以以60MHz运作以提供有利的方向性。在还提供第二RF产生器253的情况下，示例性频率可以是2MHz。
在对卡盘250RF供电的情况下，可通过第一喷淋头225提供RF返回路径。第一喷淋头225可设置在卡盘上方以将第一馈入气体分配至由第一喷淋头225与腔室壁240所界定的第一腔室区域284中。如此，卡盘250与第一喷淋头225形成第一RF耦合的电极对以电容式地激发第一腔室区域284中的第一馈入气体的第一等离子体270。经RF供电的卡盘的电容耦合所产生的DC等离子体偏压或RF偏压可产生从第一等离子体270至基板202的离子流(若第一馈入气体为Ar，则产生Ar离子)以提供离子铣削等离子体。第一喷淋头225可接地或可与RF电源228耦接，该RF电源228具有一个或更多个产生器，该一个或更多个产生器可使用与卡盘250不同的频率进行运作，例如以13.56MHz或60MHz的频率运作。在所示实施例中，第一喷淋头225可通过继电器227可选择地耦接至地或耦接至RF电源228，且在蚀刻工艺期间可例如使用控制器(未示出)自动控制该继电器227。在所揭示的实施例中，腔室200可能不包括喷淋头225或介电间隔物220，且腔室200可能改为仅包括挡板215及喷淋头210。
如图中进一步所示，蚀刻腔室200可包括泵堆叠(pump stack)，该泵堆叠能在低工艺压力下提供高通量。在实施例中，至少一个涡轮分子泵265/涡轮分子泵266可经由一个或更多个闸阀260而与第一腔室区域284耦接，且涡轮分子泵265/涡轮分子泵266可设置在卡盘250下方且与第一喷淋头225相对。涡轮分子泵265及涡轮分子泵266可以是任何市售具有适当通量的泵，尤其涡轮分子泵265及涡轮分子泵266可适当地尺寸设定成在第一馈入气体的期望的流动速率(例如，若第一馈入气体为氩气，则以50sccm至500sccm的Ar)下使工艺压力维持低于或约为10毫托耳(mTorr)或更低或是维持约5毫托耳。在所示实施例中，卡盘250可形成基座的一部分，该基座置中地放置在两涡轮泵265与涡轮泵266之间，然而在替代的配置方案中，卡盘250可位在从腔室壁240悬伸而出的基座上并具有单个涡轮分子泵，且该涡轮分子泵的中心对准该卡盘250的中心。
可在第一喷淋头225的上方设置第二喷淋头210。在一实施例中，于处理期间，第一馈入气体源(例如，从气体分配系统290输送出的氩气)可耦接至气体入口276，且该第一馈入气体流经延伸通过第二喷淋头210的多个孔280而进入第二腔室区域281并通过延伸通过第一喷淋头225的多个孔282而进入第一腔室区域284。具有孔278的附加的气流分配器或挡板215可进一步跨蚀刻腔室200的贯穿分配区域218的直径分布第一馈入气流216。在替代实施例中，第一馈入气体可如虚线223所指示般经由孔283直接流入第一腔室区域284中，孔283与第二腔室区域281隔离。
腔室200可由图中所示的状态额外重新配置成进行蚀刻操作。辅助电极205可设置在第一喷淋头225上方，且在辅助电极205与第一喷淋头225之间具有第二腔室区域281。辅助电极205可进一步形成蚀刻腔室200的盖或顶板。可利用介电环220使辅助电极205与第一喷淋头225电性隔离，且辅助电极205与第一喷淋头225形成第二RF耦合的电极对以电容式地释放第二腔室区域281的第二馈入气体的第二等离子体292。有利地，第二等离子体292可能不在卡盘250上提供明显的RF偏压电位。该第二RF耦合的电极对中的至少一个电极可耦接至RF电源以激发蚀刻等离子体。辅助电极205可与第二喷淋头210电性耦接。在示例性实施例中，第一喷淋头225可与接地板耦接或为浮动状态(floating)，且第一喷淋头225可经由继电器227接地，从而允许在离子铣削模式的操作期间也可利用RF电源228对第一喷淋头225供电。若第一喷淋头225接地，RF电源208(具有一个或更多个可以以13.56MHz或60MHz运作的RF产生器)可例如经由继电器207与辅助电极205连接，继电器207允许辅助电极205在其他操作模式期间(例如在离子铣削操作期间)也可接地，但若供电给第一喷淋头225时，也可使辅助电极205处于浮动状态。
可由气体分配系统290供应第二馈入气体源(诸如，三氟化氮)及氢源(诸如，氨)，且第二馈入气体源及氢源可例如经由虚线224而与气体入口276耦接。在此模式中，第二馈入气体可流经第二喷淋头210，并可在第二腔室区域281中激发该第二馈入气体。反应性物种随后可进入第一腔室区域284以与基板202反应。如进一步所示，对于第一喷淋头225是多通道喷淋头的实施例而言，可提供一或更多种馈入气体以与第二等离子体292所生成的反应性物种反应。在一个这种实施例中，水源可与多个孔283耦接。
在实施例中，卡盘250可在与第一喷淋头225垂直的方向上沿着距离H2移动。卡盘250可位于被波纹管255包围的驱动机构等上而允许移动卡盘250以接近或远离第一喷淋头225，藉以作为控制卡盘250与第一喷淋头225间的热传递作用的手段，第一喷淋头225可处于80℃-150℃或更高的高温。如此，可通过相对于第一喷淋头225在第一预定位置与第二预定位置之间移动卡盘250来实现蚀刻工艺。或者，卡盘250可包括升降器251以用于将基板202从卡盘250的顶表面上举起一段距离H1，藉以在蚀刻工艺期间控制第一喷淋头225的加热作用。在其他实施例中，若于固定温度(诸如，约90℃-110℃)进行蚀刻工艺，则可避免卡盘位移机构。在蚀刻工艺期间，系统控制器(未示出)可通过自动交替对第一RF耦合的电极对和第二RF耦合的电极对的供电而交替地激发第一等离子体270及第二等离子体292。
腔室200也可重新配置以进行沉积操作。可利用上述用于产生第二等离子体292的方法中的任一种方法进行RF放电以在第二腔室区域281中产生等离子体292。若在沉积期间对第一喷淋头225供电以产生等离子体292，则可利用介电间隔物230来隔离该第一喷淋头225与接地的腔室壁240，使得第一喷淋头225相对于腔室壁240而言为电性浮动的。在示例性实施例中，可从气体分配系统290输送氧化剂馈入气体源(诸如，氧分子)，且该氧化剂馈入气体源耦接至气体入口276。在第一喷淋头225是多通道喷淋头的实施例中，可从气体分配系统290输送任何含金属的前驱物(例如，含硅前驱物或其他含金属前驱物)，并引导该含金属前驱物进入第一腔室区域284中以与来自等离子体292的通过第一喷淋头225的反应性物种进行反应。或者，该前驱物也可连同该氧化剂一起流过气体入口276。
图3示出根据本技术的形成具有改善电特性的半导体结构的方法300。方法300至少部分可例如在腔室200中进行，或可在配置用来进行蚀刻操作及/或沉积操作的一或更多种其他工艺腔室中进行方法300。在所揭示的实施例中，单一工艺工具(诸如，前述的工艺工具100)可包含一个或更多个腔室。通过维持单一工具内的一个或更多个腔室，可使半导体器件保持处在受调节的环境中。例如，该工艺工具可保持真空环境，且通过使该器件在处理期间始终保持处在该工具环境内，可使该器件不暴露在周遭空气中。由于铜及其他金属在周遭环境条件(包括潮湿环境)中可能会氧化或腐蚀，因此通过在单一工具环境内进行所有操作可改进器件质量。因此，在所揭示的实施例中，可在蚀刻操作与材料层的形成之间使该半导体器件保持处于真空下。
方法300可始于在半导体结构上进行蚀刻操作310。在所揭示的实施例中，该半导体结构可包括一个或更多个IC层(例如至少两个IC层)，且该半导体结构(例如在底部电路结构中)可包括至少一金属层。蚀刻操作310可形成贯穿一个或更多个材料层的通孔以暴露出位于下层中的第一金属(诸如，金属化层)。方法300也可包括于操作320中在暴露的第一金属上形成材料层。在所示实施例中，该材料层可包含与第一金属不相同的材料，且该材料层可包含导电材料和/或含金属材料。方法300可进一步包括于操作330中在该材料层上形成第二金属，且在所示实施例中，该第二金属可与第一金属相同或不同。例如，在实施例中，第一金属及第二金属可皆为铜或钨，且在所揭示的实施例中，第一金属及第二金属可以是任何可用于电性连接(例如通孔或互连件)的其他填充材料。在一实施例中，第一金属及第二金属两者皆为铜，且该第一金属形成用于半导体结构的第一层面或IC层的互连结构，及该第二金属形成用于半导体结构的第二层面或IC层的互连结构。
在所揭示的实施例中，操作320中所形成的材料层可包括导电材料或金属。例如，该导电材料可包括过渡金属或过度金属氧化物，例如可包括钴、锰、钨，等等。此外，可依据所使用的互连金属或填充金属来选择该导电材料。例如，若使用钴作为填充金属，则可使用不同的金属作为导电材料，例如使用钨或铜或某些其他金属，从而避免该互连金属与该导电材料或盖材料皆使用相同金属。在所揭示的实施例中，该导电材料可包括钴、钌、钽，等等，及各种其他金属及过渡金属。在一实施例中，该导电材料包括钴，可在暴露的第一金属(例如在下IC层中的含铜的互连金属)上形成一层钴。可利用各种沉积技术中的任何技术，包括利用数种已知方法(包括气相沉积法、热沉积法和/或等离子体沉积法)中的任何方法进行循环沉积或直接沉积，来沉积该导电材料。在所揭示的实施例中，可选择该材料的特定前驱物以在暴露的互连金属上沉积或形成该材料层，且沿着沟槽或通孔侧壁不会形成任何该导电材料或形成最少的该导电材料。
在某些实施例中，可通过在原位点燃氢气、氨或某些其他还原性前驱物或组合物所形成的等离子体或使用来自远程处理腔室的等离子体来形成层或可在形成层之后使层暴露于等离子体中。可通过使惰性气体所携带的金属来源气体(例如钴)受热分解来沉积导电材料。还原性气体可连同金属来源气体一同流入处理腔室中，或还原性气体可与金属来源气体以交替脉冲方式流入该处理腔室。可加热基板达到介于约50℃至约600℃范围间的温度，例如达到介于约100℃至约500℃或例如约200℃至约400℃间的温度。或者，可在原子层沉积(ALD)工艺或化学气相沉积(CVD)工艺(包括各种等离子体增强CVD和/或ALD工艺)中使基板暴露于金属来源气体(例如钴来源气体)来沉积材料层或一些材料层。
在所揭示的实施例中，金属化合物可包括一或更多种钴物质，且可利用CVD或ALD工艺使用合适的钴前驱物来形成材料层内所含的钴物质(例如，金属钴或钴合金)，合适的钴前驱物包括羰基钴错合物、脒基钴化合物、二茂钴化合物、二烯基钴错合物、亚硝基钴错合物、上述前驱物的衍生物、上述前驱物的错合物、上述前驱物的等离子体或上述前驱物的组合物。
在某些实施例中，在气相沉积工艺期间可使用羰基钴化合物或羰基钴错合物作为钴前驱物以用于形成钴材料。羰基钴化合物或羰基钴错合物具有化学通式(CO)xCoyLz，其中X可以是1、2、3、4、5、6、7、8、9、10、11或12，Y可以是1、2、3、4或5，及Z可以是1、2、3、4、5、6、7或8。基团L可以是缺乏的、一个配位基或多个配位基，且该多个配位基可以是相同配位基或不同配位基，且基团L可包括环戊二烯基、烷基环戊二烯基(例如，甲基环戊二烯基或五甲基环戊二烯基)、戊二烯基、烷基戊二烯基、环丁二烯基、丁二烯基、乙烯基(ethylene)、烯丙基(或丙烯基)、烯烃、二烯烃、炔烃、乙炔、丁基乙炔、亚硝基、氨、上述化合物的衍生物、上述化合物的错合物、上述化合物的等离子体或上述化合物的组合物。
在另一实施例中，在气相沉积工艺期间可使用脒基钴或酰胺基钴错合物作为钴前驱物以用于形成钴材料。酰胺基钴错合物具有化学通式(RR'N)xCo，其中X可以是1、2或3，且R及R'独立地为氢、甲基、乙基、丙基、丁基、烷基、硅烷基、烷基硅烷基、上述基团的衍生物或组合物。一些示例性的酰胺基钴错合物包括双(二(丁基二甲基硅烷基)酰胺基)钴(bis(di(butyldimethylsilyl)amido)cobalt)、双(二(乙基二甲基硅烷基)酰胺基)钴(bis(di(ethyldimethylsilyl)amido)cobalt)、双(二(丙基二甲基硅烷基)酰胺基)钴(bis(di(propyldimethylsilyl)amido)cobalt)、双(二(三甲基硅烷基)酰胺基)钴(bis(di(trimethylsilyl)amido)cobalt)、三(二(三甲基硅烷基)酰胺基)钴(tris(di(trimethylsilyl)amido)cobalt)、上述化合物的衍生物、上述化合物的错合物、上述化合物的等离子体或上述化合物的组合物。
示例性的钴前驱物包括双(羰基)甲基环戊二烯钴(methylcyclopentadienylcobalt bis(carbonyl))、双(羰基)乙基环戊二烯钴(ethylcyclopentadienyl cobalt bis(carbonyl))、双(羰基)五甲基环戊二烯钴(pentamethylcyclopentadienyl cobalt bis(carbonyl))、八(羰基)二钴(dicobalt octa(carbonyl))、三(羰基)亚硝基钴(nitrosylcobalt tris(carbonyl))、双(环戊二烯)钴(bis(cyclopentadienyl)cobalt)、(环己二烯基)(环戊二烯基)钴((cyclopentadienyl)cobalt(cyclohexadienyl))、(1,3-己二烯基)环戊二烯钴(cyclopentadienyl cobalt(1,3-hexadienyl))、(环丁二烯基)(环戊二烯基)钴((cyclobutadienyl)cobalt(cyclopentadienyl))、双(甲基环戊二烯)钴(bis(methylcyclopentadienyl)cobalt)、(5-甲基环戊二烯基)(环戊二烯基)钴((cyclopentadienyl)cobalt(5-methylcyclopentadienyl))、双(乙烯)(五甲基环戊二烯)钴(bis(ethylene)cobalt(pentamethylcyclopentadienyl))、碘化四羰基钴(cobalttetracarbonyl iodide)、四羰基三氯硅烷钴(cobalt tetracarbonyl trichlorosilane)、氯化羰基三(三甲基膦)钴(carbonyl chloride tris(trimethylphosphine)cobalt)、三羰基-氢三丁基膦钴(cobalt tricarbonyl-hydrotributylphosphine)、乙炔六羰基二钴(acetylene dicobalt hexacarbonyl)、乙炔五羰基三乙基膦二钴(acetylene dicobaltpentacarbonyl triethylphosphine)、上述化合物的衍生物、上述化合物的错合物、上述化合物的等离子体或上述化合物的组合物。
于某些示例中，在如本文中所述的气相沉积工艺期间可使用替代的试剂(包括还原剂)与钴前驱物并用以用于形成钴材料。这些替代的试剂可包括氢(例如，H2或原子氢)、氮(N2或原子氮)、氨(NH3)、联氨(N2H4)、氢与氨的混合物、硼烷(BH3)、二硼烷(B2H6)、三乙基硼烷(Et3B)、硅烷(SiH4)、二硅烷(Si2H6)、三硅烷(Si3H8)、四硅烷(Si4H10)、甲基硅烷(SiCH6)、二甲基硅烷(SiC2H8)、磷化氢(PH3)、上述试剂的衍生物、上述试剂的等离子体或上述试剂的组合物。
可将含钴材料沉积至具有范围介于约至约(诸如约至约)内的厚度。在其他实施例中，可在表面氧化工艺期间使至少一部分的含钴材料氧化以形成氧化钴层。在一实施例中，由含钴层的上部形成氧化钴。在所揭示的实施例中，可通过使含钴层完全氧化或基本上氧化且因此被消耗以形成氧化钴层。
在所揭示的实施例中，蚀刻操作310可包括形成沟槽及通孔两者。例如，蚀刻操作310可包括形成较宽的沟槽及较窄的通孔且该通孔延伸至下方金属层。也可进行该蚀刻操作以贯穿介电材料层或蚀刻终止层中的一层或更多层，例如在所揭示的实施例中，可连续或以不连续的时间间隔来进行该蚀刻操作。例如，可在能够进行离子铣削操作且接着进行蚀刻操作的腔室(诸如，上述腔室200)中进行蚀刻操作310。此外，可使用多个蚀刻腔室。例如，可利用掩模层针对沟槽和通孔开口进行蚀刻操作，蚀刻操作可停止在介于上IC层与下IC层之间的蚀刻终止层处。随后可进行上述的离子铣削及蚀刻操作以打通该蚀刻终止层而暴露出下方金属。操作310可包括使半导体结构的一部分与来自于如上述电容耦合的等离子体的非反应性离子接触，且随后使该半导体结构的接触部分暴露于等离子体生成的反应性物种下。依此方式，可针对欲进行蚀刻的各层来选择性地进行该蚀刻工艺310，并可在损坏下方膜层之前停止蚀刻，如此可允许以不同的顺序来沉积材料层。
在所揭示的实施例中，方法300的工艺可作为镶嵌工艺(包括单镶嵌或双镶嵌工艺)的一部分。在形成该下方IC层之后可形成选择性金属盖。在形成后续或上方的层后，可使沟槽及通孔的蚀刻延伸至该下方层中的互连金属。由于工艺不完美，这种蚀刻可能蚀穿形成在第一层面互连金属上方的选择性金属盖部分。后面将会解释，此种情况可能造成电迁移问题。然而，使用所述的离子铣削及蚀刻工艺，可通过使用特殊化学剂来调整蚀刻，以在触及钴层后便终止蚀刻而不会造成钴层损伤。在所揭示的实施例中，该钴材料可能发生反应而形成表层副产物，在蚀刻工艺期间将不会蚀刻该表层副产物。当蚀刻操作完成时，可移动晶片而例如使该晶片靠近加热元件，从而造成副产物升华以暴露出下方的钴。可在所形成的选择性薄金属盖上沉积附加的含钴材料，或者，若该层在蚀刻工艺310期间受到损伤，则可对该层进行修复。
沉积该材料层后，方法300还可包括在形成覆盖该材料层的第二金属之前，先在所蚀刻的通孔和/或沟槽内形成阻障层。该阻障层可包括多种材料，该等材料包括金属、非金属、过渡金属或主族金属(poor metal)材料，包括锰、钽、镍等的非排他性列表。阻障层材料可包括过渡金属及含过渡金属的材料，例如其氮化物、氧化物、碳化物、硼化物等等，例如，诸如氮化锰。该材料可包括各种合金或其他材料(例如陶瓷或类陶瓷材料)或任何适用于降低或防止铜、钨或其他互连材料扩散进入周遭材料中的其他材料。虽然所揭示的实施例可包括在沟槽中形成内衬，但所揭示的实施例在沟槽和/或通孔中也可能除了该第二金属(例如，铜)以外不含其他材料。如上所述，互连金属占据的体积越少，则通过该等层的电阻越大，且该器件的延迟及整个结构的功率损耗越大。因此，本技术可使沟槽内被通孔导体所占据的体积最大化。
可以多种方式，包括物理沉积工艺和/或CVD或ALD工艺以及无电镀式(E-less)形成工艺或其他形成工艺，来形成该阻障层材料。在所揭示的实施例中，该阻障层材料可包括锰，例如，诸如用CVD所沉积的氮化锰或硅酸锰。通过使用此种工艺，可进行无底式通孔填充，无底式通孔填充具有完全或基本上完全的侧壁覆盖，但在通孔底部处具有最少或减少的覆盖物。例如，可沿着通孔的侧壁沉积阻障层达到第一厚度，并在所形成的该材料层上沉积阻障层达到第二厚度，且该第二厚度小于该第一厚度。这么做可有助于通过最小化该空间内的附加材料而进一步最大化填充金属(诸如填充于通孔内的铜)。然而，本案发明人也确定一些可能是由无底式通孔现象所造成的作用可能对电迁移产生影响。
由于较少的覆盖物提供的较低电阻，无底式通孔方案可能有好处。然而，下层面互连金属与上层面互连金属之间的覆盖物减少可能导致浮现出电迁移的问题。换而言之，电迁移问题集中在电子通量(electron flux)及填充金属原子(诸如，铜原子)的移动这两者上。在上层面的铜与下层面的铜之间(或任何用来形成上方与下方互连金属及通孔金属的两个相似金属之间)没有接触或几乎不接触的情况下，电迁移通量可能使引发金属原子移动的情况增加。这可能造成在互连结构中形成空穴而可能加速器件失效。常规技术建议使用短的互连件(诸如长度小于50微米的互连件)，短互连件可由背向应力停止(back stressstop)来提供足够的背向应力来抵销任何能实际移动铜原子的电子通量。然而，如图4所示，此做法是不够的。
图4图示使用减小的阻障层厚度所推算出的临界电流密度效应的模型。然而，测试显示模型随着阻障层宽度按比例变化(scaled)而失效。如图中在阻障层为10纳米厚的位置410处所示，模型随着临界电流密度实质降低而失效代表当宽度缩小时，短的互连件长度仍旧无法克服电迁移及缩短组件寿命的问题。反观长的互连件(诸如，超过200微米)的谱，则可能发生不同现象。图5示出针对控制阻障层510以及针对氮化锰520的无底式通孔形成的电迁移失效测试测量值。控制阻障层510显示出较低的失效时间，然而无底式通孔阻障层520所测出的失效时间改进超过7倍，显示无底式通孔阻障层是一项大幅改善的设计。
然而，进一步测试显示这是由于电迁移造成的移动所发展出的错误信号。提供看似较长的电迁移失效时间的结构实际上劣化其下方结构。通常，电迁移会受电子通量的方向影响而造成在上表面中形成空穴。然而，在使用无底式通孔阻障层且该上层互连金属与下层互连金属接触的情况下，该通量确实会造成将铜从下层的IC层中拉出，从而在该下层中形成空穴并造成结构断裂。虽然该器件在失效测试过程中呈现持续运作状态，但这持续运作的状态事实上是由于铜原子从下层移动到上层所造成，代表着器件失效实际上可能更早发生。
令人惊讶的是，虽然本案发明人已确定通过在下层互连金属上结合盖层且同时还使用无底部的通孔阻障层时，该盖层可提供用来与电子通量达成平衡的背向应力以防止铜原子移动，同时通过减少阻障层的厚度及用于阻障层的材料量来额外减少通孔及线路的电阻。随后将铜填入该通孔及沟槽的较大体积中而有助于减少通孔电阻及整个器件的总体RC延迟。应了解，常规上是以铜作为填充金属，但也可使用任何已知的填充金属或导电金属，包括钨、钴，等等。
图6示出根据本技术的实施例的包含选择性金属盖的集成电路600的部分的示例剖面结构。可通过本申请文件中的其他处所述方法中的任何方法来形成结构600，并可在本文中所述的任何腔室或工艺工具中形成该结构600，例如可使用诸多用来进行微影、沉积及蚀刻的其他已知工艺及腔室来形成结构600。该图示出部分地根据所揭示技术制造的双镶嵌互连结构。然而容易理解的是，本技术可运用在包含其他双镶嵌工艺或单镶嵌工艺的更简单或更复杂的结构上。也明白，IC器件经常包含多个双镶嵌结构，而本技术可用于此种结构上，因此本技术不应局限于此图。
IC600的结构包含两层结构及数个可能包含的示例性层。也可包含更多或更少个层，包括更多或更少的介电层、特征、器件、蚀刻终止层，等等。图中所示的结构600包含下层，在所示实施例中，该下层包含底部电介质605、第一介电材料层或第一层间电介质610及上电介质615，该上电介质615可以是蚀刻终止层。该等介电层可包括各种低介电常数(k)电介质中的任何电介质，包括硅基电介质(包括硅的氮化物、氧化物、碳化物，等等)。下层也包括金属层635，金属层635可以是第一导电层且该第一导电层至少部分设置在第一介电层内，且该第一导电层可例如是铜互连金属。在所揭示的实施例中，该下层也可包括选择性盖或第三导电层，可在对金属635及介电层610进行研磨之后，在介电层610与介电层615之间形成该选择性盖或第三导电层。
针对上半部结构，器件可例如包括第二介电层620以及上介电层或蚀刻终止层625以及任选的硬掩模层630。第二介电层620可覆盖于介电层615上，该介电层615可视为是设置在第一介电层与第二介电层之间的第三介电层。第二导电层640可包括上方的互连件及通孔材料，且第二导电层640可至少部分设置在该第二介电层620中。导电层640可包括第一部分或上部分643及第二部分或下部分646，该第一部分或上部分643具有第一宽度，该第二部分或下部分646具有第二宽度且该第二宽度小于该第一宽度。如图所示，第二部分646可设置成比该第一部分643更接近该第一导电层。在所揭示的实施例中，沟槽643与通孔646可分开蚀刻，且可在多个蚀刻操作中形成该结构。
第三导电层645可设置在第一导电层635与第二导电层640之间。第三导电层645可包含导电材料且该导电材料与第一导电层或第二导电层中所含的材料不同。结构600中可使用先前所讨论的材料中的任何材料或方法，例如，在一实施例中，第一导电层及第二导电层可包含铜，及第三导电层645可包含钴。结构600也可包括阻障层且该阻障层至少部分设置在沟槽及通孔的侧壁650上。该阻障层也可包括或不包括在第三导电材料645上的覆盖物(coverage)653。在实施例中，阻障层可具有小于或约为20纳米的侧壁厚度，且该阻障层可小于或约为15纳米、10纳米、9纳米、8纳米、7纳米、6纳米、5纳米、4纳米、3纳米、2纳米、1纳米，等等。该阻障层可包括一或更多种材料，诸如该阻障层可包含一材料及该材料的氮化物或包含两种不同材料。在所揭示的实施例中，该阻障层在区域653中可包含较少的覆盖物，且可包含一阻障层厚度，该阻障层厚度可小于、等于或约为该侧壁650的覆盖物的90％，且可小于、等于或约为80％、70％、60％、50％、40％、30％、20％、10％、5％、1％或包含在该等范围内的任何其他数值或较小范围。在选择性盖定位在第一电介质610与第三电介质615之间的情况下，该盖的材料可与第三导电材料相同。此外，该盖在第一电介质610与第三电介质615之间可具有第一厚度。第三导电材料可具有第二厚度，且该第二厚度与该盖的第一厚度不同。在所揭示的实施例中，该第二厚度可大于或小于该第一厚度。
回到图7，图7示出根据所揭示技术的在互连金属上形成盖的方法700。方法700可包括前述方法操作中的部分操作或所有操作，且可例如在腔室200中或在多种其他腔室中进行方法700。可使用部分的方法700或使用经某些修改形式的方法700来制造结构600或其他结构。方法700包括蚀刻通孔710而使通孔710贯穿半导体结构。在所揭示的实施例中，该结构可至少包括第一电路层及在该第一电路层上的第二电路层。可进行该蚀刻操作710以贯穿该第二电路层而暴露出在第一电路中的互连金属。在操作720，可清洗下方的互连金属。可进行诸多清洗工艺中的任何清洗工艺，包括溅射工艺、可包含原位氢等离子体的反应性预清洗工艺、利用异地氢等离子体进行的活性预清洗工艺、UV或任何可能包含由各种前驱物所形成的一或多种等离子体物种以用于清洗下方互连金属表面的其他清洗方法。
方法700还可包括在操作730中，于暴露的第一金属上形成含钴保护盖。可使用前述方式中的任一种方式来形成该含钴盖。方法700还可包括在操作740中沿着该通孔的侧壁形成含锰阻障层。该阻障层可沉积以覆盖含钴保护盖达一厚度，该厚度比沿着该通孔侧壁所沉积的阻障层厚度的50％要小。在实施例中，该阻障层在侧壁处可具有小于10纳米或约10纳米的厚度，且该阻障层在该保护盖上可具有不连续或最少的覆盖。方法700也可包括在操作750中使用铜来填充该通孔从而直接覆盖阻障层。
在前述说明内容中举出诸多细节以供解说的用，以帮助了解本发明的各种实施例。然而所属技术领域中熟悉该项技艺者明白可在不使用这些细节内容中的部分细节或是使用附加细节的情况下实施某些实施例。
虽已揭示数个实施例，但所属技术领域中熟悉该项技艺者将明白在不偏离实施例的精神下，可做出各种修饰变化、替代配置方案及使用等效物。此外，未对诸多众所皆知的工艺及器件进行描述，以避免不必要地模糊本技术。因此，以上所述内容不应用来限制本技术的范围。
当提供一数值范围时，应了解到这也具体揭示了介于该范围上下限值之间的每个居间数值(至该下限值的单位的最小分数，除非文中另有明确指示)。本发明涵盖介于所述范围中任一陈述值(或未陈述的居间值)与该所述范围中任一其他陈述值(或其他未陈述的居间值)之间的任何较窄范围。该范围中可各自包括或排除该等较小范围的上限值及下限值，且本发明也涵盖每一个包含其中一限值、不含限值或两限值皆具的较小范围，端取决于所述范围中是否有任何明确排出的限值而定。若所述范围包含该等限值的其中一者或两者时，本发明也包括排除了其中一个或两个所含限值的范围。
当用于本文中及后附权利要求中时，除非为中另有明确指示，否则单数用语“一”、“一个”及“该”包括复数的引用。因此，例如当提到“电介质”时可包括多个此种电介质，及当提到“该层”时包括提及一或更多层及所属技术领域中熟悉该项技艺者知悉的等效物，并依此类推。
同样，当本说明书及后附权利要求中使用“包括”、“包含”、“含有”、“含”、“具有”及“有”等术语时，该等术语意欲指出所述特征、整数、部件或操作的存在，但该等术语并不排除可能存在有或附加的一个或更多个其他特征、整数、部件、操作、动作或群组。

Claims (17)

1.一种形成半导体结构的方法，所述方法包括以下步骤：
蚀刻通孔以贯穿半导体结构，其中所述蚀刻步骤暴露出第一金属；
形成覆盖暴露的第一金属的材料层；
在蚀刻的通孔内形成阻障层，其中沿所述通孔的侧壁将所述阻障层沉积达第一厚度，且在所述材料层上将所述阻障层沉积达第二厚度，所述第二厚度小于所述第一厚度；以及
形成覆盖所述材料层的第二金属。
2.如权利要求1所述的方法，其中所述材料层包括过渡金属或过渡金属氧化物。
3.如权利要求1所述的方法，其中将所述材料层形成为达到介于0.5纳米与10纳米之间的厚度。
4.如权利要求1所述的方法，其中除了所述材料层、所述第二金属及所述阻障层材料外，所述通孔不包括其他材料。
5.如权利要求4所述的方法，其中所述阻障层包含过渡金属。
6.如权利要求5所述的方法，其中所述阻障层包含锰。
7.如权利要求1所述的方法，其中所述第一金属及所述第二金属中的至少一者包含铜。
8.如权利要求1所述的方法，其中所述第一金属包括互连件，用于半导体结构的第一层面，以及所述第二金属包括互连件，用于半导体结构的第二层面。
9.如权利要求1所述的方法，其中所述蚀刻步骤的至少一部分包括以下步骤：
使所述半导体结构的一部分接触来自电容耦合的等离子体的非反应性离子；以及
使所述半导体结构的接触部分暴露于等离子体生成的反应性物种下。
10.如权利要求1所述的方法，其中进行所述蚀刻步骤作为单镶嵌或双镶嵌工艺的操作。
11.如权利要求1所述的方法，其中在所述蚀刻操作与材料层形成操作之间，所述半导体结构保持处于真空。
12.一种在集成电路结构中形成保护盖的方法，所述方法包括以下步骤：
蚀刻通孔以贯穿半导体结构，其中所述半导体结构包括至少第一电路层及第二电路层，且其中进行所述蚀刻步骤以贯穿所述第二电路层而暴露所述第一电路层内的互连金属；
清洗所述互连金属；
形成覆盖暴露的第一金属的含钴保护盖；
沿所述通孔的侧壁形成含锰的阻障层，其中所述阻障层形成为覆盖所述含钴保护盖达一厚度，所述厚度小于沿着所述通孔的侧壁所沉积的阻障层的厚度的50％，且其中所述阻障层在侧壁处具有10纳米或更小的厚度；以及
使用铜填充所述通孔从而直接覆盖所述阻障层。
13.一种半导体结构，所述半导体结构包括：
第一介电材料层；
第一导电层，所述第一导电层至少部分地设置在所述第一介电材料层中；
第二介电材料层；
第二导电层，所述第二导电层至少部分地设置在所述第二介电材料层中；
第三导电层，所述第三导电层设置在所述第一导电层与所述第二导电层之间，其中所述第三导电层包括导电材料，所述导电材料与所述第一导电层或所述第二导电层所含的材料不同；以及
阻障层，所述阻障层在所述第二介电材料层与所述第二导电层之间沉积达第一厚度，且在所述第二导电层和所述第三导电层之间沉积达第二厚度，所述第二厚度小于所述第一厚度。
14.如权利要求13所述的半导体结构，其中所述第二导电层包括具有第一宽度的第一部分及具有第二宽度的第二部分，所述第二宽度小于所述第一宽度，其中所述第二部分设置成比所述第一部分更接近所述第一导电层。
15.如权利要求13所述的半导体结构，进一步包括第三介电材料层，所述第三介电材料层定位在所述第一介电材料层与所述第二介电材料层之间。
16.如权利要求15所述的半导体结构，其中所述第三导电层定位在所述第一介电材料层与所述第三介电材料层之间。
17.如权利要求16所述的半导体结构，其中所述第三导电层在所述第一介电材料层与所述第三介电材料层之间的一位置处包括第一厚度，且在所述第一导电层与所述第二导电层之间的一位置处包括第二厚度，所述第二厚度与所述第一厚度不同。
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