TW201546963A - 用於改良互連性能之保護通孔蓋 - Google Patents

用於改良互連性能之保護通孔蓋 Download PDF

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TW201546963A
TW201546963A TW104117463A TW104117463A TW201546963A TW 201546963 A TW201546963 A TW 201546963A TW 104117463 A TW104117463 A TW 104117463A TW 104117463 A TW104117463 A TW 104117463A TW 201546963 A TW201546963 A TW 201546963A
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metal
semiconductor structure
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Mehul Naik
Paul F Ma
Srinivas D Nemani
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Applied Materials Inc
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Abstract

形成半導體結構的示例性方法可包括蝕刻通孔以貫穿半導體結構而暴露出第一電路層互連金屬。該方法可包括在該暴露的第一電路層互連金屬上形成材料層。該方法亦包括在該通孔內形成阻障層且在沿著該通孔的底部具有最少覆蓋物。該方法附加包括在該材料層上形成第二電路層互連金屬。

Description

用於改良互連性能之保護通孔蓋
本發明技術是關於半導體系統、製程及設備。更明確言之，本發明技術有關用來改良互連結構以降低電遷移效應的系統、方法及結構。
積體電路可包含超過一百萬個的微電子場效電晶體，該等電晶體形成在基板上並協同運作以在該電路內執行各種功能。可靠地生產次半微米特徵及更小特徵是半導體元件下一代超大型積體電路(「VLSI」)及極大型積體電路(「ULSI」)的關鍵技術之一。然而，由於積體電路技術的極限是朝垂直方向推動及擴展，因此VLSI及ULSI中持續縮小的互連線尺寸在處理能力方面有著諸多附加要求。可靠地形成通孔及互連線對於成功形成積體電路及持續努力提高電路密度及個別基板和晶粒的品質而言很重要。
由於特徵尺寸縮小，所以該等互連線及通孔可電性連接各式各樣的結構。然而，包括互連線及通孔在內的安全特徵可能造成整個電路結構中的線路電阻及電阻-電容延遲劇增。此外，當特徵尺寸縮小時，電遷移可能變得越來越具破壞性。
因此，需要能夠用來生產高品質元件及結構的改良系統及方法。本發明技術將可解決此等需求及其他需求。
本發明提出用於增進互連線及通孔性能的系統、結構及製程。該等系統可提供構件結構配置以允許進行多種製程而無需改變環境或使結構暴露 在周遭環境條件下。該等結構可包括可降低電遷移的積體電路結構。該等方法可限制互連線中或整個互連線上的原子移動。
形成半導體結構的示例性方法可包括蝕刻蝕刻通孔以貫穿半導 體結構，其中該蝕刻步驟暴露出第一金屬。該方法可包括在該暴露的第一金屬上形成材料層，及該方法可進一步包括在該材料層上形成第二金屬。在一實施例中，該材料層可包括過渡金屬或過渡金屬氧化物，且在一實施例中，所形成的該材料層可達到介於約0.5奈米至10奈米間的厚度。該方法可進一步包括在該材料層上形成該第二金屬之前，先在該蝕刻的通孔內形成阻障層。沿該通孔的該等側壁沈積該阻障層達第一厚度，及在該材料層上沈積該阻障層達第二厚度且該第二厚度小於該第一厚度。在所揭示的實施例中，除了該第二金屬及阻障層之外，該通孔可不包括其他材料。在實施例中，該阻障層可包括過渡金屬(例如錳)，及該第一金屬與該第二金屬其中至少一者可包含銅。
在所揭示的實施例中，該第一金屬可為用於半導體結構之第一層 次的互連線，及該第二金屬可為用於半導體結構之第二層次的互連線。該蝕刻步驟可包括使該半導體結構的一部分接觸來自一電容耦合電漿的不反應性離子，及隨後使該半導體結構的該已接觸部分暴露於一電漿生成的反應性物種下。 該蝕刻步驟可作為單鑲嵌或雙鑲嵌製程的其中一部分來進行，及該半導體結構在該蝕刻步驟與形成材料層的步驟之間可保持處於真空。
本發明還揭示在積體電路結構中形成保護蓋的方法，該等方法包 括蝕刻通孔以貫穿半導體結構。該半導體結構可包括至少一第一電路層及一第二電路層，且可進行該蝕刻步驟以貫穿該第二電路層而暴露該第一電路層內的互連金屬。該等方法包括清洗該互連金屬，且該等方法亦可包括在該暴露的第一金屬上形成含鈷保護蓋。該等方法可又進一步包括沿該通孔的側壁形成含錳阻障層。在形成期間，形成在該含鈷保護蓋上的阻障層厚度比沿著該通孔之側 壁所沈積之阻障層厚度的50%要小。在所揭示的實施例中，該阻障層在該等側壁處可具有小於或約為10奈米的厚度。該等方法亦可包括直接在該阻障層上使用銅來填充該通孔。
本發明亦揭示半導體結構，且該等半導體結構可包括第一介電材 料層及第一導電層，且該第一導電層至少部分配置在該第一介電材料層中。該等結構可包括第二介電材料層及第二導電層，且該第二導電層至少部分配置在該第二介電材料層中。該等結構可亦包括第三導電層，該第三導電層配置在該第一導電層與該第二導電層之間。該第三導電層可包括導電材料，且該導電材料與該第一導電層或該第二導電層所含的材料不同。示例性的結構可包括該第二導電層具有第一部分及第二部分，該第一部分具有第一寬度及該第二部分具有第二寬度，且該第二寬度小於該第一寬度。該第二部分配置成比該第一部分更接近該第一導電層。該結構可亦包括第三介電材料層，該第三介電材料層配置在該第一介電材料層與該第二介電材料層之間。在所揭示的實施例中，該第三導電層可配置在該第一介電材料層與該第三介電材料層之間。該第三導電層可包括位在介於該第一介電材料層與該第三介電材料層間之一位置處的第一厚度，及位在介於該第一導電層與該第二導電層間之一位置處的第二厚度，且該第二厚度與該第一厚度不同。
此技術可帶來勝過習知系統與技術的諸多好處。例如，若電遷移 效應降低，元件的壽命可能增加。附加優點是改善後的系統可縮短佇列時間及減少元件氧化或腐蝕。現配合下述內容及附圖更詳細地說明此等實施例與其他實施例及該等實施例的特徵及所帶來的諸多優點。
W‧‧‧基板
100‧‧‧處理系統/處理工具
104‧‧‧工廠介面
105A‧‧‧晶圓盒裝載器
105B‧‧‧晶圓盒裝載器
105C‧‧‧晶圓盒裝載器
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110‧‧‧移送室
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113A‧‧‧基板傳送刀刃
113B‧‧‧伸縮臂
114A‧‧‧處理腔室
114B‧‧‧處理腔室
114C‧‧‧處理腔室
114D‧‧‧處理腔室
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117‧‧‧整合式度量腔室
200‧‧‧示例性處理腔室系統
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217‧‧‧嵌入式熱交換器蛇管
218‧‧‧分佈區域
220‧‧‧介電間隔物/介電環
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225‧‧‧第一噴淋頭
227‧‧‧繼電器
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248‧‧‧高壓直流供應器
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265‧‧‧渦輪分子泵
266‧‧‧渦輪分子泵
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276‧‧‧氣體入口
278‧‧‧孔
280‧‧‧孔
281‧‧‧第二腔室區域
282‧‧‧孔
283‧‧‧孔
284‧‧‧第一腔室區域
290‧‧‧氣體分配系統
292‧‧‧第二電漿
300‧‧‧方法
310‧‧‧蝕刻步驟
320‧‧‧步驟
330‧‧‧步驟
410‧‧‧位置
510‧‧‧控制組阻障層
520‧‧‧氮化錳
600‧‧‧積體電路/結構
605‧‧‧底部介電質
610‧‧‧第一介電材料層/第一層間介電層
615‧‧‧上介電質
620‧‧‧第二介電層
625‧‧‧上介電層/蝕刻終止層
630‧‧‧選用性硬遮罩層
635‧‧‧金屬層
640‧‧‧第二導電層
643‧‧‧第一部分/上部分/溝槽
645‧‧‧第三導電層/第三導電材料
646‧‧‧第二部分/下部分
650‧‧‧側壁
653‧‧‧覆蓋物/覆蓋
700‧‧‧方法
710‧‧‧步驟
720‧‧‧步驟
730‧‧‧步驟
740‧‧‧步驟
750‧‧‧步驟
參閱本案說明書其餘部分及附圖，可進一步瞭解本案揭示技術的本質與優點。
第1圖為根據本發明技術圖示示例性處理系統的俯視平面圖。
第2圖為根據本發明技術圖示示例性處理腔室的概要剖面圖。
第3圖為根據本發明技術之實施例圖示在互連金屬上形成選擇性金屬蓋的方法。
第4圖圖示使用減小的阻障層厚度所推算出之臨界電流密度效應的圖形模型。
第5圖圖示多種阻障層材料的電遷移失效時間雙模型分佈圖。
第6圖為根據本發明技術之實施例圖示出含有選擇性金屬蓋之積體電路的局部示例性剖面結構。
第7圖為根據本發明技術之實施例圖示在互連金屬上形成選擇性金屬蓋的方法。
某些圖式為概要圖。應明白該等圖式僅做示範說明之用，且除非文中特別聲明該圖依規格比例所做，否則該等圖式未按比例繪製。
在該等附圖中，相似的構件及/或特徵可具有相同的元件符號。此外，可藉著在該元件符號後方隨附一個用來區分該等相似構件的字母來區別同類型的各個不同構件。若在本案說明書中僅使用首位元件符號，則不論該字母為何，該段描述內容皆適用於該等具有相同首位元件符號之相似構件中的任一者。
本發明技術包括用於改良互連線與通孔性能及積體電路(「IC」)元件之總電性能的系統、結構及方法。隨著半導體特徵尺寸的縮減，可能產生包括電性問題在內等諸多問題。許多IC元件使用銅或鎢作為用於元件膜層內及元件膜層之間的通孔金屬及互連線金屬。例如使用銅作為通孔金屬及互連線金屬通常包括在溝槽及通孔內使用阻障層，藉以限制銅擴散進入周圍膜層中，若 銅擴散進入周圍膜層中則可能造成短路或元件失效。此外，當元件特徵及互連線溝槽和通孔的尺寸縮小時，互連線金屬可能會因溝槽內的高深寬比而遇到未能完全填通的情形。
習知技術經常利用內襯來解決此劣化問題以改善縫隙填充情 形。然而，溝槽及通孔內含有越多的阻障層及內襯材料，能填入該體積中的銅越少。由於銅的導電性遠勝於阻障層及內襯材料，通孔或溝槽內的銅越少，則有效電阻越大，當元件諸多膜層各處的有效電阻加總在一起時，有效電阻會實質影響到總電阻-電容(「RC」)延遲。可藉著薄化阻障層及甚至是拿掉內襯來控制此等問題，然而這麼做會讓元件可能具有很差的電遷移特性，此點將於以下配合第3圖及第4圖進行討論。在另一方面，本發明技術使用蓋層並可使用無阻障層通孔底部作用(barrier-less via bottom effects)來提供背向應力以抵銷電遷移，並在通孔內提供最少量的非銅材料以使通孔及線路的電阻減至最小。因此相較於諸多習知設計而言，本發明中所描述的方法及結構提供更佳的性能及成本效益。以下將詳細說明此等益處及其他益處。
儘管其餘的揭示內容將照慣例舉出可使用本案揭示技術的具體 蝕刻製程，但可輕易明白的是，該等系統及方法可等效地應用於可在所述腔室中進行的沉積製程及清潔製程上。因此，不應認為本發明技術僅可與蝕刻製程併用。
第1圖為根據實施例圖示由沉積腔室、蝕刻腔室、烘烤腔室及固 化腔室所組成之處理系統100實施例的俯視平面圖。第1圖中所示之處理工具100可包含複數個處理腔室114A~114D、移送室110、檢修腔室116、整合式度量腔室117及一對裝載鎖定腔室106A~106B。該等處理腔室可包括與第2圖中所述者相似的結構或構件及附加處理腔室，附加的處理腔室可包括沉積腔室。
移送室110可包含機器人傳送機構113以用於在該等腔室之間傳 送基板。機器人傳送機構113可具有一對基板傳送刀刃113A，該等基板傳送刀刃113A分別連接於伸縮臂113B的遠端。該等刀刃113A可用於搬運個別基板進入或離開該等處理腔室。操作時，該傳送機構113的其中一個基板傳送刀刃(例如，刀刃113A)可從該等裝載鎖定腔室(例如腔室106A~B)的其中一個腔室取出基板W並搬運基板W以進行第一階段處理，例如在腔室114A~D中進行如以下所述般的蝕刻製程。若該等腔室已被佔用，機器人可等候至處理完成，且隨後使用刀刃113A取出該等腔室中的已處理基板並使用第二刀刃(圖中未示出)插入新的基板。一旦基板處理完成後，隨後可移送該基板前往進行第二階段處理，第二階段處理可包括沈積步驟、處理步驟，等等。對於每次移送，該機器人傳送機構113通常可用一個刀刃承載基板並使一個刀刃保持空閑以供進行基板交換。傳送機構113可在各個腔室處等候直到完成交換動作。
一旦在處理腔室內完成處理，傳送機構113可從最後的處理腔室 中移出基板W並將基板W移送至裝載鎖定腔室106A~B內的匣盒中。可將該基板從該等裝載鎖定腔室106A~B移送至工廠介面104。工廠介面104通常可運作以在該等裝載鎖定腔室106A~B與處於大氣壓潔淨環境中的晶圓盒裝載器105A~D之間移送基板。通常透過空氣過濾處理(例如，HEPA過濾)來提供工廠介面104中的潔淨環境。工廠介面104亦可包括基板定向器/對準器(圖中未示出)，在進行處理之前可使用基板定向器/對準器適當地對準基板。工廠介面104中可配置至少一個基板機器人(例如機器人108A~B)以用於在工廠介面104內的各種不同位置/場所之間移送基板及將基板送往與工產介面104連通的其他位置。機器人108A~B可配置成可在外殼104內沿著軌道系統從工廠介面104的第一端行進至工廠介面104的第二端。
處理系統100可進一步包括整合式度量腔室117以提供控制訊號 而可為該等處理腔室內正在進行任何製程提供適應性控制。整合式度量腔室117可包括各式各樣的度量裝置以測量各種膜性質(例如厚度、粗糙度、組成)，且該等度量裝置可進一步能夠以自動化方式描述處於真空下的光柵參數特性(例如，臨界尺寸、側壁角度及特徵高度)。
現參閱第2圖，第2圖根據本發明技術示出示例性處理腔室系統 200的剖面圖。腔室200可例如用於前述系統100之該等處理腔室部分114的其中一者或多者。通常，蝕刻腔室200可包括第一電容耦合電漿源以進行離子銑削(ion-milling)步驟，且蝕刻腔室200可包括第二電容耦合電漿源以進行蝕刻步驟及進行選用性的沈積步驟。腔室200可包括接地的腔室壁240，該等腔室壁240圍繞著卡盤250。在實施例中，卡盤250可為靜電卡盤以在處理期間將基板202固定於卡盤250的頂表面，但也可使用已知的其他固定機構。卡盤250可包括嵌入式熱交換器蛇管217。在示例性實施例中，熱交換器蛇管217包含一或更多個熱交換流體通道，熱交換流體(例如，乙二醇/水的混合物)可流經該等熱交換流體通道以控制卡盤250的溫度且最終控制基板202的溫度。
卡盤250可包括網格249，網格249連接至高壓直流(DC)供應器 248，使得網格249可攜帶DC偏壓電位以進行靜電固定該基板202。卡盤250可與第一射頻(RF)電源連接，且在一此種實施例中，網格249可與第一RF電源連接，以使DC電壓偏移及RF電壓電位耦合於卡盤250之頂表面上的整個薄介電層。在示例性實施例中，該第一RF電源可包括第一RF產生器252及第二RF產生器253。 RF產生器252及RF產生器253可以任何工業用頻率運作，然而在示例性實施例中，RF產生器252可以60MHz運作以提供有利的方向性。實施例中亦提供第二RF產生器253，且示例性的頻率可為2MHz。
由於會提供RF電力給卡盤250，可藉由第一噴淋頭225提供RF返 回路徑。第一噴淋頭225可配置在該卡盤上方以將第一饋入氣體分配至由第一噴淋頭225與腔室壁240所界定而成第一腔室區域284中。如此，卡盤250與第一噴淋頭225形成第一對RF耦合電極而以電容耦合方式供給能量給第一腔室區域284中由第一饋入氣體所形成的第一電漿270。經RF供電的卡盤進行電容耦合所產生DC電漿偏壓或RF偏壓可使第一電漿270的離子流(若第一饋入氣體為Ar時，則產生Ar離子)流向基板202以提供離子銑削電漿。第一噴淋頭225可接地或可與RF電源228連接，該RF電源228具有一或更多個產生器且該一或更多個產生器可使用與卡盤250不同的頻率進行運作，例如以13.56MHz或60MHz的頻率運作。在所示實施例中，第一噴淋頭225可透過繼電器227來選擇接地或連接至RF電源228，且在蝕刻製程期間可例如使用控制器(圖中未示出)自動控制該繼電器227。在所揭示的實施例中，腔室200可能不包括噴淋頭225或介電間隔物220，且腔室200可能改為僅包括擋板215及噴淋頭210。
如圖中進一步所示，蝕刻腔室200可包括堆疊泵組(pump stack)， 該堆疊泵組能在低製程壓力下提供高通量。在實施例中，至少一個渦輪分子泵265/渦輪分子泵266可經由一或更多個閘閥260而與第一腔室區域284連接，且渦輪分子泵265/渦輪分子泵266可配置在卡盤250下方且位在與第一噴流頭225相反之處。渦輪分子泵265及渦輪分子泵266可為任何市售具有適當通量的泵，尤其是該等渦輪分子泵265及渦輪分子泵266可適當調整尺寸而可在期望的第一饋入氣體流動速率(例如，若第一饋入氣體為氬氣，則以50sccm至500sccm的Ar)下使製程壓力維持低於或約為10毫托耳(mTorr)或更低或是維持約5毫托耳。在所示實施例中，卡盤250可形成基座的一部分，該基座置中地放置在兩渦輪幫浦265與渦輪幫浦266之間，然而在替代的配置方案中，卡盤250可位在從腔室壁240懸伸 而出的基座上並具有單個渦輪分子泵，且該渦輪分子泵的中心對準該卡盤250的中心。
可在第一噴淋頭225的上方配置第二噴淋頭210。在一實施例中， 於處理期間，第一饋入氣體源(例如，從氣體分配系統290輸送出的氬氣)可連接氣體入口276，且該第一饋入氣體流經延伸貫穿第二噴淋頭210的複數個孔280而進入第二腔室區域281並通過延伸貫穿第一噴淋頭225的複數個孔282而進入第一腔室區域284。附加的氣流分配器或擋板215具有孔278而可進一步使第一饋入氣流216通過分配區域218而分佈於蝕刻腔室200的整個直徑。在替代實施例中，第一饋入氣體可如虛線223所指示般經由孔283直接流入第一腔室區域284中，該等孔283是與第二腔室區域281隔離的。
腔室200可由圖中所示的狀態額外重新配置成可用來進行蝕刻步 驟。輔助電極205可配置在第一噴淋頭225上方，且在輔助電極205與第一噴淋頭225之間具有第二腔室區域281。輔助電極205可進一步形成蝕刻腔室200的蓋或頂板。可利用介電環220使輔助電極205與第一噴淋頭225電性隔離，且輔助電極205與第一噴淋頭225形成第二對RF耦合電極以用於在第二腔室區域281內進行電容性放電以使第二饋入氣體形成第二電漿292。較佳者，第二電漿292可能不在卡盤250上提供明顯的RF偏壓電位。該第二對RF耦合電極之中的至少一個電極可連接RF電源以為蝕刻電漿提供能量。輔助電極205可與第二噴淋頭210電性連接。在示例性實施例中，第一噴淋頭225可與接地板連接或為浮接狀態(floating)，且第一噴淋頭225可經由繼電器227接地，以允許在離子銑削模式操作期間亦可利用RF電源228供電至第一噴淋頭225。若第一噴淋頭225接地，RF電源208(具有一或更多個可以13.56MHz或60MHz運作的RF產生器)可例如經由繼電器207與輔助電極205連接，繼電器207允許輔助電極205在其他操作模式期間 (例如在離子銑削步驟期間)也可接地，但若供電給第一噴淋頭225時，亦可使輔助電極205處於浮接狀態。
可由氣體分配系統290供應第二饋入氣體源(例如，三氟化氮)及 氫源(例如，氨)，且第二饋入氣體源及氫源可例如經由虛線224而與氣體入口276連接。在此模式中，第二饋入氣體可流經第二噴淋頭210，並可在第二腔室區域281中活化該第二饋入氣體。反應性物種隨後可進入第一腔室區域284以與基板202反應。如進一步所示，對於第一噴淋頭225是多通道噴淋頭的實施例而言，可提供一或更多種饋入氣體以與第二電漿292所生成的反應性物種反應。在一此實施例中，水源可與該複數個孔283連接。
在實施例中，卡盤250可在與第一噴淋頭225成垂直的方向上沿著 距離H2移動。卡盤250可位在被波紋管255包圍的可驅動機構(或諸如此類構件)上而允許移動卡盤250以接近或遠離第一噴淋頭225，藉以作為控制卡盤250與第一噴淋頭225間之熱傳作用的手段，第一噴淋頭225可能處於80℃~150℃或更高的高溫。如此，可藉著相對於第一噴淋頭225在第一預定位置與第二預定位置之間移動卡盤250來進行蝕刻製程。或者，卡盤250可包括升降器251以用於將基板202從卡盤250的頂表面上舉起一段距離H1，藉以在蝕刻製程期間控制第一噴淋頭225的加熱作用。在其他實施例中，若於固定溫度(例如，約90℃~110℃)進行該蝕刻製程，則可免用卡盤移動機構。在蝕刻製程期間，系統控制器(圖中未示出)可藉著自動交替供電給第一對RF耦合電極及第二對RF耦合電極而交替地提供能量給第一電漿270及第二電漿292。
腔室200亦可重新配置以進行沈積步驟。可利用上述用於產生第 二電漿292之方法中的任一種方法進行射頻放電以在第二腔室區域281中產生電漿292。若在沈積期間供電給第一噴淋頭225以產生電漿292，則可利用介電間隔物230來隔離該第一噴淋頭225與接地的腔室壁240，使得第一噴淋頭225相對於 腔室壁240而言為電性浮動。在示例性實施例中，可從氣體分配系統290輸送氧化劑饋入氣體源(例如，氧分子)，且該氧化劑饋入氣體源連接至氣體入口276。 在第一噴淋頭225是多通道噴淋頭的實施例中，可從氣體分配系統290輸送任何含金屬前驅物(例如，含矽前驅物或其他含金屬前驅物)，並引導該含金屬前驅物進入第一腔室區域284中以與來自電漿292並通過第一噴淋頭225的反應性物種進行反應。或者，該前驅物亦可隨著該氧化劑一起流過氣體入口276。
第3圖根據本發明技術示出形成具有改善電特性之半導體結構的 方法300。方法300至少部分可例如在腔室200中進行，或可在一或更多種配置用來進行蝕刻步驟及/或沈積步驟的其他製程腔室中進行方法300。在所揭示的實施例中，單一個製程工具(例如，前述的製程工具100)可包含一或更多個腔室。藉由維持單一工具內的該一或更多個腔室，可使半導體元件保持處在受調節的環境中。例如，該製程工具可保持真空環境，且藉著使該元件在處理期間始終保持處在該工具環境內，可使該元件不暴露在周遭空氣中。由於銅及其他金屬在周遭環境(包括潮濕環境)中可能會氧化或腐蝕，因此藉著在單一工具環境內進行所有步驟可增進元件品質。因此，在所揭示的實施例中，可在蝕刻步驟與形成材料層的步驟之間使該半導體結構保持處於真空下。
方法300可始於在半導體結構上進行蝕刻步驟310。在所揭示的實 施例中，該半導體結構可包括一或更多個IC層(例如至少兩個IC層)，且該半導體結構(例如在底部電路結構中)可包括至少一金屬層。蝕刻步驟310可形成貫穿一或更多個材料層的通孔以暴露出位於下層(lower layer)中的第一金屬(例如，金屬層)。方法300亦可包括於步驟320中在暴露的第一金屬上形成材料層。在所示實施例中，該材料層可包含與第一金屬不相同的材料，且該材料層可包含導電材料及/或含金屬材料。方法300可進一步包括於步驟330中在該材料層上形成第二金屬，且在所示實施例中，該第二金屬可與第一金屬相同或不同。例如，在實 施例中，第一金屬及第二金屬可皆為銅或鎢，且在所揭示的實施例中，第一金屬及第二金屬可為任何可用於電性連接(例如通孔或互連線)的其他填充材料。在一實施例中，第一金屬及第二金屬兩者皆為銅，且該第一金屬形成用於半導體結構之第一層次或IC層的互連結構，及該第二金屬形成用於半導體結構之第二層次或IC層的互連結構。
在所揭示的實施例中，步驟320中所形成的材料層可包括導電材 料或金屬。例如，該導電材料可包括過渡金屬或過度金屬氧化物，例如可包括鈷、錳、鎢，等等。此外，可依據所使用的互連金屬或填充金屬來選擇該導電材料。例如，若使用鈷作為填充金屬，則可使用不同的金屬作為導電材料，例如使用鎢或銅或某些其他金屬，藉以避免該互連金屬與該導電材料或蓋材料皆使用相同金屬。在所揭示的實施例中，該導電材料可包括鈷、釕、鉭，等等，及各種其他金屬及過渡金屬。在一實施例中，該導電材料包括鈷，可在暴露的第一金屬(例如在下IC層中的含銅互連金屬)上形成一層鈷。可利用各種沈積技術中的任何技術，包括利用數種已知方法(包括氣相沈積法、熱沈積法及/或電漿沈積法)中的任何方法進行循環沈積或直接沈積，來沈積該導電材料。在所揭示的實施例中，可選擇該材料的特定前驅物以在暴露的互連金屬上沈積或形成該材料層，且沿著溝槽或通孔的側壁不會形成任何該導電材料或形成最少的該導電材料。
在某些實施例中，可藉著在原位點燃氫氣、氨或某些其他還原性 前驅物或其組合物所形成的電漿或使用來自遠端處理腔室的電漿來形成該等層或可在形成該等層之後使該等層暴露於電漿中。可藉著使惰性氣體所攜帶的金屬來源氣體(例如鈷)受熱分解來沈積該導電材料。還原性氣體可隨著該金屬來源氣體一同流入該處理腔室中，或該還原性氣體可與金屬來源氣體以交替脈衝方式流入該處理腔室。可加熱該基板達到介於約50℃至約600℃範圍間的溫度，例 如達到介於約100℃至約500℃或例如約200℃至約400℃間的溫度。或者，可在原子層沈積(ALD)製程或化學氣相沈積(CVD)製程(包括各種電漿增強CVD及/或ALD製程)中使該基板暴露於金屬來源氣體(例如鈷來源氣體)來沈積該材料層或該等材料層。
在所揭示的實施例中，該金屬化合物可包括一或更多種鈷物質， 且可利用CVD或ALD製程使用合適的鈷前驅物來形成該材料層內所含的該等鈷物質(例如，金屬鈷或鈷合金)，合適的鈷前驅物包括羰基鈷錯合物、脒基鈷化合物、二茂鈷化合物、二烯基鈷錯合物、亞硝基鈷錯合物、上述前驅物之衍生物、上述前驅物之錯合物、上述前驅物之電漿或上述前驅物之組合物。
在某些實施例中，在氣相沈積製程期間可使用羰基鈷化合物或羰 基鈷錯合物作為鈷前驅物以用於形成鈷材料。羰基鈷化合物或羰基鈷錯合物具有化學通式(CO)xCoyLz，其中X可為1、2、3、4、5、6、7、8、9、10、11或12，Y可為1、2、3、4或5，及Z可為1、2、3、4、5、6、7或8。L基團可為缺乏、一個配位基或多個配位基，且該多個配位基可為相同配位基或不同配位基，且L基團可包括環戊二烯基、烷基環戊二烯基(例如，甲基環戊二烯基或五甲基環戊二烯基)、戊二烯基、烷基戊二烯基、環丁二烯基、丁二烯基、乙烯基(ethylene)、烯丙基(或丙烯基)、烯烴、二烯烴、炔烴、乙炔、丁基乙炔、亞硝基、氨、上述化合物之衍生物、上述化合物之錯合物、上述化合物之電漿或上述化合物之組合物。
在另一實施例中，在氣相沈積製程期間可使用脒基鈷或醯胺基鈷 錯合物作為鈷前驅物以用於形成鈷材料。醯胺基鈷錯合物具有化學通式(RR'N)xCo，其中X可為1、2或3，且R及R'各自為氫、甲基、乙基、丙基、丁基、烷基、矽烷基、烷基矽烷基、上述基團之衍生物或組合物。一些示例性的醯胺基鈷錯合物包括雙(二(丁基二甲基矽烷基)醯胺基)鈷 (bis(di(butyldimethylsilyl)amido)cobalt)、雙(二(乙基二甲基矽烷基)醯胺基)鈷(bis(di(ethyldimethylsilyl)amido)cobalt)、雙(二(丙基二甲基矽烷基)醯胺基)鈷(bis(di(propyldimethylsilyl)amido)cobalt)、雙(二(三甲基矽烷基)醯胺基)鈷(bis(di(trimethylsilyl)amido)cobalt)、三(二(三甲基矽烷基)醯胺基)鈷(tris(di(trimethylsilyl)amido)cobalt)、上述化合物之衍生物、上述化合物之錯合物、上述化合物之電漿或上述化合物之組合物。
示例性的鈷前驅物包括雙(羰基)甲基環戊二烯鈷 (methylcyclopentadienyl cobalt bis(carbonyl))、雙(羰基)乙基環戊二烯鈷(ethylcyclopentadienyl cobalt bis(carbonyl))、雙(羰基)五甲基環戊二烯鈷(pentamethylcyclopentadienyl cobalt bis(carbonyl))、八(羰基)二鈷(dicobalt octa(carbonyl))、三(羰基)亞硝基鈷(nitrosyl cobalt tris(carbonyl))、雙(環戊二烯)鈷(bis(cyclopentadienyl)cobalt)、(環己二烯基)(環戊二烯基)鈷((cyclopentadienyl)cobalt(cyclohexadienyl))、(1,3-己二烯基)環戊二烯鈷(cyclopentadienyl cobalt(1,3-hexadienyl))、(環丁二烯基)(環戊二烯基)鈷((cyclobutadienyl)cobalt(cyclopentadienyl))、雙(甲基環戊二烯)鈷(bis(methylcyclopentadienyl)cobalt)、(5-甲基環戊二烯基)(環戊二烯基)鈷((cyclopentadienyl)cobalt(5-methylcyclopentadienyl))、雙(乙烯)(五甲基環戊二烯)鈷(bis(ethylene)cobalt(pentamethylcyclopentadienyl))、碘化四羰基鈷(cobalt tetracarbonyl iodide)、四羰基三氯矽烷鈷(cobalt tetracarbonyl trichlorosilane)、氯化羰基三(三甲基膦)鈷(carbonyl chloride tris(trimethylphosphine)cobalt)、三羰基-氫三丁基膦鈷(cobalt tricarbonyl-hydrotributylphosphine)、乙炔六羰基二鈷(acetylene dicobalt hexacarbonyl)、乙炔五羰基三乙基膦二鈷(acetylene dicobalt pentacarbonyl triethylphosphine)、上述化合物之衍生物、上述化合物之錯合物、上述化合物之電漿或上述化合物之組合物。
於某些實例中，在如本文中所述的氣相沈積製程期間可使用另類 的試劑(包括還原劑)與鈷前驅物並用以用於形成鈷材料。此等另類試劑可包括氫(例如，H2或原子氫)、氮(N2或原子氮)、氨(NH3)、聯氨(N2H4)、氫與氨的混合物、硼烷(BH3)、二硼烷(B2H6)、三乙基硼烷(Et3B)、矽烷(SiH4)、二矽烷(Si2H6)、三矽烷(Si3H8)、四矽烷(Si4H10)、甲基矽烷(SiCH6)、二甲基矽烷(SiC2H8)、磷化氫(PH3)、上述試劑之衍生物、上述試劑之電漿或上述試劑之組合物。
可沈積該含鈷材料至具有範圍介於約2Å至約100Å(例如約10Å至約40Å)間的厚度。在其他實施例中，可在表面氧化製程中使至少一部分的含鈷材料氧化以形成氧化鈷層。在一實施例中，由該含鈷層的上部分形成氧化鈷。在所揭示的實施例中，可使該含鈷材料完全氧化或實質氧化且從而消耗該含鈷材料以形成氧化鈷層。
在所揭示的實施例中，蝕刻步驟310可包括形成溝槽及通孔兩者。例如，蝕刻步驟310可包括形成較寬的溝槽及較窄的通孔且該通孔延伸至下方金屬層。亦可進行該蝕刻步驟以貫穿一或更多個介電材料層或蝕刻終止層，例如在所揭示的實施例中，可連續或以不連續的時間間隔來進行該蝕刻步驟。例如，可在能夠進行離子銑削步驟且接著進行蝕刻步驟的腔室(例如，上述腔室200)中進行蝕刻步驟310。此外，可使用多個蝕刻腔室。例如，利用遮罩層進行蝕刻步驟以打通溝槽和通孔，打通溝槽和通孔的動作可停止在介於上IC層與下IC層之間的蝕刻終止層處。隨後可進行上述的離子銑削及蝕刻步驟以打通該蝕刻終止層而暴露出下方金屬。步驟310可包括使該半導體結構的一部分與來自於如上述電容耦合電漿的非反應性離子接觸，且隨後使該半導體結構的已接觸部分暴露於電漿生成的反應性物種下。依此方式，可針對欲進行蝕刻的各層來選擇性地進行該蝕刻製程310，並可在損及下方膜層之前停止蝕刻，如此可允許以不同的順序來沈積該材料層。
在所揭示的實施例中，方法300的製程可作為鑲嵌製程(包括單鑲 嵌或雙鑲嵌製程)的一部分。在形成該下方IC層之後可形成選擇性金屬蓋。在形成後續或上方的層之後，可使溝槽及通孔的蝕刻延伸至該下方層的互連金屬。 由於製程不完美，此蝕刻作用可能蝕穿該形成在第一層次之互連金屬上方的選擇性金屬蓋部分。後面將會解釋，此種情況可能造成電遷移問題。然而，使用所述的離子銑削及蝕刻製程，可能要使用特殊化學劑來調整該蝕刻作用，以求一旦觸及該鈷層時便終止蝕刻而不會造成鈷層損傷。在所揭示的實施例中，該鈷材料可能發生反應而形成表層副產物，在蝕刻製程中將不會蝕刻該表層副產物。當蝕刻步驟完成時，可移動晶圓而例如使該晶圓靠近加熱元件，造成該等副產物昇華而暴露出下方的鈷。可在所形成的選擇性薄金屬蓋上沈積附加的含鈷材料，或者，若該層在蝕刻製程310期間受到損傷，可對該層進行修復。
沈積該材料層之後，方法300亦可包括在該材料層上形成第二金 屬之前，先在所蝕刻的通孔及/或溝槽內形成阻障層。該阻障層可包括多種材料，該等材料包括金屬、非金屬、過渡金屬或主族金屬(poor metal)材料，非排他性的列舉實例包括錳、鉭、鎳，等等。該阻障層材料可包括過渡金屬及含過渡金屬的材料，例如其氮化物、氧化物、碳化物、硼化物等等，舉例而言，例如氮化錳。該材料可包括各種合金或其他材料(例如陶瓷或類陶瓷材料)或任何適用於降低或防止銅、鎢或其他互連材料擴散進入周遭材料中的其他材料。雖然所揭示的實施例可包括在溝槽中形成內襯，但所揭示的實施例在溝槽及/或通孔中也可能除了該第二金屬(例如，銅)以外不含其他材料。如上述般，互連金屬佔據的體積越少，則通過該等層的電阻越大，且該元件的延遲及整個結構的功率損耗越大。因此，本發明技術可使溝槽內被通孔導體所佔據的體積最大化。
可以多種方式，包括物理沈積製程及/或CVD或ALD製程以及無 電式(E-less)形成製程或其他形成製程，來形成該阻障層材料。在所揭示的實施 例中，該阻障層材料可包括錳，舉例而言，例如用CVD所沈積的氮化錳或矽酸錳。使用此種製程可進行無底式通孔填充，無底式通孔填充具有完全或實質完全的側壁覆蓋，但在通孔底部處具有最少或減少的覆蓋物。例如，可沿著通孔的側壁沈積阻障層達到第一厚度，並在所形成的該材料層上沈積阻障層達到第二厚度，且該第二厚度小於該第一厚度。這麼做有助於減少該空間內附加材料而可進一步增大填充金屬(例如填充於通孔內的銅)。然而，本案發明人亦觀察到一些可能是由無底式通孔現象所造成的作用，這些作用可能對電遷移產生影響。
由於較少的覆蓋物可提供較低電阻，因此無底式通孔方案可能有 好處。然而，下層次之互連金屬與上層次之互連金屬之間的覆蓋物減少可能導致浮現出電遷移的問題。換言之，電遷移問題集中在電子流(electron flux)及填充金屬原子(例如，銅原子)的移動這兩者上。當上層次的銅與下層次的銅之間(或任何用來形成上方與下方互連金屬及通孔金屬的兩個相似金屬之間)沒有接觸或少許接觸，電遷移通量可能使引發金屬原子移動的情況增加。這可能造成在互連結構中形成孔洞而可能加速元件失效。習知技術建議使用短的互連線(例如長度小於50微米的互連線)，短互連線可由背向應力停止(back stress stop)來提供足夠的背向應力來抵銷任何能實際移動銅原子的電子流。然而，如第4圖所示，此做法是不夠的。
第4圖圖示使用減小的阻障層厚度所推算出臨界電流密度效應的 模型。然而，測試顯示當阻障層寬度縮小(scaled)時，該模型失效。如圖中在阻障層為10奈米厚的位置410處所示般，臨界電流密度實質降低代表當寬度縮小時，短的互連線長度仍舊無法克服電遷移及縮短元件壽命的問題，因此該模型失效。反觀長的互連線(例如，超過200微米)則可能發生不同現象。第5圖示出控制組阻障層510及無底式通孔形成法所形成之氮化錳520的電遷移失效試驗測量 值。控制組阻障層510顯示出較低的失效時間，然而無底式通孔阻障層520所測出的失效時間增進超過7倍，顯示無底式通孔阻障層是一項大幅改善的設計。
然而，進一步測試顯示這是由於電遷移造成移動所衍生出的錯誤 訊號。該等提供看似較長之電遷移失效時間的結構實際上其下方結構正在劣化。通常，電遷移作用會受電子流的方向影響而造成在該上表面中形成孔洞。 然而，當使用無底式通孔阻障層且該上層互連金屬與下層互連金屬接觸時，該電子流確實會造成將銅從下層的IC層中拉出，而在該下層中形成孔洞並造成結構斷裂。雖然該元件在失效測試過程中呈現持續運作狀態，但這持續運作的狀態事實上是由於銅原子從下層移動到上層所造成，代表著元件失效的情況實際上可能更早發生。
令人驚訝的是，雖然本案發明人已確定藉由在下層互連金屬上使 用蓋層且同時亦合併使用無底部的通孔阻障層時，該蓋層可提供用來與電子流達成平衡的背向應力以防止銅原子移動，然而藉著減少阻障層的厚度及用於阻障層的材料量可額外減少通孔及線路的電阻。隨後將銅填入該通孔及溝槽的較大體積中而有助於減少通孔電阻及整個元件的總RC延遲。應瞭解，常規上是以銅作為填充金屬，但也可使用任何已知的填充金屬或導電金屬，包括鎢、鈷，等等。
第6圖為根據本發明技術之實施例圖示包含選擇性金屬蓋之積體 電路600的局部示例剖面結構。可使用本案文中其他處所述方法中之任何方法來形成結構600，並可在本文中所述的任何腔室或製程工具中形成該結構600，例如可使用諸多用來進行微影、沈積及蝕刻的其他已知製程及腔室來形成結構600。該圖圖示根據本案揭示技術部分製造而成雙鑲嵌互連結構。然而容易理解的是，本發明技術可運用在包含其他雙鑲嵌製程或單鑲嵌製程的更簡單或更複 雜結構上。亦明白，IC元件經常包含多個雙鑲嵌結構，而本發明技術可用於此種結構上，因此本發明技術不應侷限於此圖。
積體電路(IC)600的結構包含兩層結構及數個可能包含的示例性 膜層。亦可包含更多或更少個膜層，包括更多或更少的介電層、特徵、元件、蝕刻終止層，等等。圖中所示的結構600包含下層，在所示實施例中，該下層包含底部介電質605、第一介電材料層或第一層間介電層610及上介電質615，該上介電質615可為蝕刻終止層。該等介電層可包括各種低介電常數(low-k)介電質中的任何介電質，包括矽型介電質(包括矽的氮化物、氧化物、碳化物，等等)。下層亦包括金屬層635，金屬層635可為第一導電層且該第一導電層至少部分配置在第一介電層內，且該第一導電層可例如是銅互連金屬。在所揭示的實施例中，該下層亦可包括選擇性蓋或第三導電層，可在對金屬635及介電層610進行研磨之後，在介電層610與介電層615之間形成該選擇性蓋或第三導電層。
針對上半部結構，該元件可例如包括第二介電層620和上介電層或蝕刻終止層625及選用性的硬遮罩層630。第二介電層620可覆蓋於介電層615上，該介電層615可視為是配置在第一介電層與第二介電層之間的第三介電層。第二導電層640可包括上方的互連線及通孔材料，且第二導電層640可至少部分配置在該第二介電層620中。導電層640可包括第一部分或上部分643及第二部分或下部分646，該第一部分或上部分643具有第一寬度，該第二部分或下部分646具有第二寬度且該第二寬度小於該第一寬度。如圖所示，第二部分646可配置成比該第一部分643更接近該第一導電層。在所揭示的實施例中，溝槽643與通孔646可分開蝕刻，且可在複數個蝕刻步驟中形成該結構。
第三導電層645可配置在第一導電層635與第二導電層640之間。第三導電層645可包含導電材料且該導電材料與第一導電層或第二導電層中所含的材料不同。結構600中可使用先前所討論之材料中的任何材料，例如，在一 實施例中，第一導電層及第二導電層可包含銅，及第三導電層645可包含鈷。結構600亦可包括阻障層且該阻障層至少部分配置在溝槽及通孔的側壁650上。該阻障層亦可包括或不包括位在第三導電材料645上的覆蓋物(coverage)653。在實施例中，該阻障層可具有小於或約為20奈米的側壁厚度，且該阻障層可小於或約為15奈米、10奈米、9奈米、8奈米、7奈米、6奈米、5奈米、4奈米、3奈米、2奈米、1奈米，等等。該阻障層可包括一或更多種材料，例如該阻障層可包含一材料及該材料的氮化物或包含兩種不同材料。在所揭示的實施例中，該阻障層在區域653中可包含較少的覆蓋物，且可包含一阻障層厚度，該阻障層厚度可小於、等於或約為該側壁650之覆蓋物的90%，且可小於、等於或約為80%、70%、60%、50%、40%、30%、20%、10%、5%、1%或包含在該等範圍內的任何其他數值或較小範圍。若在第一介電質610與第三介電質615之間配置了選擇性蓋，該蓋的材料可與第三導電材料相同。此外，該蓋在第一介電質610與第三介電質615之間可具有第一厚度。第三導電材料可具有第二厚度，且該第二厚度與該蓋的第一厚度不同。在所揭示的實施例中，該第二厚度可大於或小於該第一厚度。
回到第7圖，第7圖是根據本案揭示技術圖示在互連金屬上形成蓋 的方法700。方法700可包括前述方法步驟中的部分步驟或所有步驟，且可例如在腔室200中或在多種其他腔室中進行方法700。可使用部分的方法700或使用經某些修改形式的方法700來製造結構600或其他結構。方法700包括蝕刻通孔710而使通孔710貫穿半導體結構。在所揭示的實施例中，該結構可至少包括第一電路層及在該第一電路層上的第二電路層。可進行該蝕刻步驟710以貫穿該第二電路層而暴露出位在第一電路中的互連金屬。在步驟720，可清洗下方的互連金屬。可進行諸多清洗製程中的任何清洗製程，包括濺射製程、可包含原位氫電漿的反應性預清洗製程、利用異地氫電漿進行的活性預清洗製程、UV或任何可 能包含由各種前驅物所形成之一或多種電漿物種以用於清洗下方互連金屬表面的其他清洗方法。
方法700亦可包括在步驟730中，於暴露的第一金屬上形成含鈷保 護蓋。可使用前述方式中的任一種方式來形成該含鈷蓋。方法700亦可包括在步驟740中沿著該通孔的側壁形成含錳阻障層。該阻障層可沈積在該含鈷保護蓋上，以使沈積在該含鈷保護蓋上的阻障層厚度比沿著該通孔側壁所沈積之阻障層厚度的50%要小。在實施例中，該阻障層在該等側壁處可具有小於10奈米或約10奈米的厚度，且該阻障層在該保護蓋上可具有不連續或最少的覆蓋。方法700亦可包括在步驟750中直接在該阻障層上使用銅來填充該通孔。
在前述說明內容中舉出諸多細節以供解說之用，以幫助瞭解本發 明的各種實施例。然而所屬技術領域中熟悉該項技藝者明白可在不使用此等細節內容中的部分細節或是使用附加細節的情況下實施某些實施例。
雖已揭示數個實施例，但所屬技術領域中熟悉該項技藝者將明白 在不偏離該等實施例的精神下，可做出各種修飾變化、替代配置方案及使用等效物。此外，未對諸多眾所皆知的製程及元件進行描述，以避免不必要地模糊本發明技術。因此，以上所述內容不應用來限制本發明技術的範圍。
當提供一數值範圍時，應瞭解到這也具體揭示了介於該範圍上下 限值之間的每個居間數值(至該下限值之單位的最小分數，除非文中另有明確指示)。本發明涵蓋介於所述範圍中任一陳述值(或未陳述之居間值)與該所述範圍中任一其他陳述值(或其他未陳述之居間值)之間的任何較窄範圍。該範圍中可各自包括或排除該等較小範圍的上限值及下限值，且本發明亦涵蓋每一個包含其中一限值、不含限值或兩限值皆具的較小範圍，端取決於所述範圍中是否有任何明確排出的限值而定。若所述範圍包含該等限值之其中一者或兩者時，本發明也包括排除了其中一個或兩個所含限值的範圍。
當用於本文中及後附請求項中時，除非為中另有明確指示，否則 單數用語「一」、「一個」及「該」包括複數之意。因此，例如當提到「一介電質」時可包括複數個此種介電質，及當提到「該層」時包括提及一或更多層及所屬技術領域中熟悉該項技藝者知悉的等效物，並依此類推。
又，當本案說明書及後附請求項中使用「包括」、「包含」、「含 有」、「含」、「具有」及「有」等用字時，該等用字是意欲指出所述特徵、整數、構件或步驟的存在，但該等用字並不排除可能存在有或附加一或更多個其他特徵、整數、構件、步驟、動作或群組。
W‧‧‧基板
100‧‧‧處理系統
104‧‧‧工廠介面
105A‧‧‧晶圓盒裝載器
105B‧‧‧晶圓盒裝載器
105C‧‧‧晶圓盒裝載器
106A‧‧‧裝載鎖定腔室
106B‧‧‧裝載鎖定腔室
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113B‧‧‧延伸臂
114A‧‧‧處理腔室
114B‧‧‧處理腔室
114C‧‧‧處理腔室
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Claims (18)

  1. 一種形成一半導體結構的方法，該方法包括以下步驟：蝕刻一通孔以貫穿一半導體結構，其中該蝕刻步驟暴露出一第一金屬；在該暴露的第一金屬上形成一材料層；及在該材料層上形成一第二金屬。
  2. 如請求項1所述之方法，其中該材料層包括一過渡金屬或一過渡金屬氧化物。
  3. 如請求項1所述之方法，其中所形成的該材料層達到介於約0.5奈米至10奈米間的一厚度。
  4. 如請求項1所述之方法，進一步包括以下步驟：在該材料層上形成該第二金屬之前，先在該蝕刻的通孔內形成一阻障層。
  5. 如請求項4所述之方法，其中沿該通孔的該等側壁沈積該阻障層達一第一厚度，及在該材料層上沈積該阻障層達一第二厚度且該第二厚度小於該第一厚度，及其中除了該第二金屬及該等阻障層材料之外，該通孔不包括其他材料。
  6. 如請求項5所述之方法，其中該阻障層包含一過渡金屬。
  7. 如請求項6所述之方法，其中該阻障層包含錳。
  8. 如請求項1所述之方法，其中該第一金屬及該第二金屬之其中至少一者包含銅。
  9. 如請求項1所述之方法，其中該第一金屬包括一互連線以用於一半導體結構的一第一層次，及該第二金屬包括一互連線以用於一半導體結構的一第二層次。
  10. 如請求項1所述之方法，其中該蝕刻步驟的至少一部分包括以下步驟：使該半導體結構的一部分接觸來自一電容耦合電漿的不反應性離子；及使該半導體結構的該已接觸部分暴露於一電漿生成的反應性物種下。
  11. 如請求項1所述之方法，其中所進行的該蝕刻步驟是作為一單鑲嵌或雙鑲嵌製程的一步驟。
  12. 如請求項1所述之方法，其中在該蝕刻步驟與該形成材料層的步驟之間，該半導體結構保持處於真空。
  13. 一種在一積體電路結構中形成一保護蓋的方法，該方法包括以下步驟：蝕刻一通孔以貫穿一半導體結構，其中該半導體結構包括至少一第一電路層及一第二電路層，及其中執行該蝕刻步驟以貫穿該第二電路層而暴露該第一電路層內的一互連金屬；清洗該互連金屬；於該暴露的第一金屬上形成一含鈷保護蓋；沿該通孔的該等側壁形成一含錳阻障層，其中形成在該含鈷保護蓋上之該阻障層的厚度比沿著該通孔之該等側壁所沈積之該阻障層厚度的50%要小，及其中該阻障層在該等側壁處具有一小於或約為10奈米的厚度；及直接在該阻障層上使用銅填充該通孔。
  14. 一種半導體結構，該半導體結構包括：一第一介電材料層；一第一導電層，且該第一導電層至少部分配置在該第一介電材料層中； 一第二介電材料層；一第二導電層，且該第二導電層至少部分配置在該第二介電材料層中；及一第三導電層，該第三導電層配置在該第一導電層與該第二導電層之間，其中該第三導電層包括一導電材料，且該導電材料與該第一導電層或該第二導電層所含的材料不同。
  15. 如請求項14所述之半導體結構，其中該第二導電層包括一具有一第一寬度的第一部分及一具有一第二寬度的第二部分，且該第二寬度小於該第一寬度，其中該第二部分配置成比該第一部分更接近該第一導電層。
  16. 如請求項14所述之半導體結構，進一步包括一第三介電材料層，該第三介電材料層配置在該第一介電材料層與該第二介電材料層之間。
  17. 如請求項16所述之半導體結構，其中該第三導電層配置在該第一介電材料層與該第三介電材料層之間。
  18. 如請求項17所述之半導體結構，其中該第三導電層包括位在該第一介電材料層與該第三介電材料層間之一位置處的一第一厚度，及位在該第一導電層與該第二導電層間之一位置處的一第二厚度，且該第二厚度與該第一厚度不同。
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