CN103262237A - 具有中部触点并改善热性能的增强堆叠微电子组件 - Google Patents
具有中部触点并改善热性能的增强堆叠微电子组件 Download PDFInfo
- Publication number
- CN103262237A CN103262237A CN2011800604260A CN201180060426A CN103262237A CN 103262237 A CN103262237 A CN 103262237A CN 2011800604260 A CN2011800604260 A CN 2011800604260A CN 201180060426 A CN201180060426 A CN 201180060426A CN 103262237 A CN103262237 A CN 103262237A
- Authority
- CN
- China
- Prior art keywords
- microelectronic element
- micromodule
- radiator
- microelectronic
- back side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3731—Ceramic materials or glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
- H01L2224/13014—Shape in top view being circular or elliptic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1451—Function
- H01L2224/14515—Bump connectors having different functions
- H01L2224/14519—Bump connectors having different functions including bump connectors providing primarily thermal dissipation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
- H01L2224/32188—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48105—Connecting bonding areas at different heights
- H01L2224/48106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06589—Thermal management, e.g. cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1094—Thermal management, e.g. cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01049—Indium [In]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Ceramic Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
微电子组件包括:介电元件(930B),具有朝向相反的第一表面和第二表面、及在两表面之间延伸的一个或多个孔隙(972),介电元件上进一步具有导电元件;第一微电子元件(900A),具有背面和面向介电元件(930B)第一表面的正面,第一微电子元件(900A)具有第一边缘和暴露在正面的复数个触点;第二微电子元件(900B),包括有背面和面对第一微电子元件的背面的正面,第二微电子元件(900B)正面的突出部分越过第一微电子元件(900A)的第一边缘而延伸,突出部分与介电元件(930B)的第一表面间隔开,第二微电子元件(900B)具有暴露在正面突出部分上的复数个触点,引线从微电子元件的触点穿过至少一个孔隙延伸到至少一些导电元件;散热器(970),与第一微电元件(900A)或第二微电子元件(900B)中的至少一个热耦合。
Description
相关申请的交叉引用
本申请为申请号为12/907522、申请日为2010年10月19日的美国专利申请的继续申请,其公开的内容以引用的方式并入本文。
背景技术
本发明涉及堆叠微电子组件及制造这种组件的方法,并涉及用于这种组件的元器件。
半导体芯片通常设置为单独的、封装的单元。标准芯片具有扁平的、长方形的主体,正面大且具有与芯片内部电路连接的触点。每个单独的芯片通常都安装在封装内,封装又安装在如印刷电路板的电路板上,并使芯片的触点与电路板的导电体连接。在许多常规设计中,芯片封装占据电路板的面积远大于上芯片本身的面积。参照具有正面的扁平芯片在本文中应用的,“芯片面积”应当理解为指的是正面的面积。在“倒装芯片”的设计中,芯片的正面面对封装基板、即芯片载体的表面,芯片上的触点通过焊料球或其他连接元件与芯片载体的触点直接结合。然后,芯片载体可通过覆盖芯片正面的端子而与电路板结合。“倒装芯片”设计提供了相对紧凑的布置,每个芯片占据电路板的面积等于或稍大于芯片正面的面积,例如在共同转让的专利号为5148265、5148266、5679977的美国专利中某些实施例中公开的,其公开的内容以引用的方式并入本文。
某些创新安装技术提供的紧凑性接近或等于常规倒装芯片结合技术。可容纳单个芯片的封装占用电路板的面积等于或稍大于芯片本身的面积,通常称为“芯片级封装”。
除了使微电子组件所占据电路板的平面面积最小化以外,制造垂直于电路板平面的总体高度或尺寸小的芯片封装,也是可取的。这种薄的微电子封装允许,其内安装有此封装的电路板放置为与邻近结构相当接近,因此制成的并入此电路板的产品的总体尺寸小。为在单个封装或模块内生产多个芯片,已推出了各种方案。在常规的“多芯片模块”中,芯片并排安装在单个封装基板上,然后基板安装在电路板上。这种方案仅提供了芯片所占据电路板的总面积的有限缩减。该总面积仍大于模块中单独芯片的面积总和。
还提出了把多个芯片封装至“堆叠”中的布置,即,布置为多个芯片以一个在另一个之上的方式放置。在堆叠布置中,数个芯片可安装在电路板的小于各芯片面积总和的区域内。例如上述的专利号为5679977、5148265的美国专利及专利号为5347159的美国专利的某些实施例中已公开了一些堆叠芯片布置,其公开的内容以引用的方式并入本文。同样以引用方式并入本文的专利号为4941033的美国专利中,公开了一种布置,其中芯片以一个在另一个之上堆叠,并通过与芯片相连称为“布线膜(wiring films)”上的导电体而彼此互连。
尽管在本领域中已具有这些努力,在多芯片封装中芯片具有大致位于芯片中部区域的触点的情况下,进一步的改进将是可取的。某些半导体芯片,如一些存储芯片,通常制有大致沿芯片中心轴设置为一排或两排的触点。
发明内容
微电子组件包括具有朝向相反的第一表面和第二表面、及在两表面间延伸的一个或多个孔隙的介电元件,介电元件上还具有导电元件;第一微电子元件具有背面和面向介电元件第一表面的正面,第一微电子元件具有第一边缘和复数个暴露在其正面的触点;第二微电子元件包括有背面和面对第一微电子元件背面的正面,第二微电子元件正面的突出部分越过第一微电子元件的第一边缘而延伸,突出部分与介电元件的第一表面间隔开,第二微电子元件具有复数个暴露在正面的突出部分上的触点,引线从微电子元件的触点穿过至少一个孔隙延伸到至少一些导电元件;散热器与第一微电元件或第二微电子元件中的至少一个热耦合。
附图说明
图1是根据本发明实施例堆叠微电子组件的剖视示意图。
图2是图1中堆叠组件的仰视图。
图3是根据本发明另一实施例堆叠微电子布置的剖视示意图。
图4是根据本发明另一实施例堆叠微电子组件的剖视示意图。
以及图5是根据本发明又一实施例堆叠微电子组件的剖视示意图。
图6是根据本发明实施例堆叠微电子组件的剖视示意图。
图7是根据本发明一个实施例系统的示意图。
具体实施方式
参照图1,根据本发明实施例的堆叠微电子组件10,包括第一微电子元件12和第二微电子元件14。在一些实施例中,第一微电子元件12和第二微电子元件14可为半导体芯片、晶圆或类似物。
第一微电子元件12具有正面16、远离正面的背面18、及在正面与背面之间延伸的第一边缘27和第二边缘29。第一微电子元件12的正面16包括第一端部区域15和第二端部区域17,及位于第一端部区域15与第二端部区域17之间的中部区域13。第一端部区域15在中部区域13与第一边缘27之间延伸,而第二端部区域17在中部区域13与第二边缘29之间延伸。电触点20暴露在第一微电子元件12的正面16上。如在本文应用的,声明导电元件“暴露在”结构的表面,指的是导电元件可与一理论点接触,该理论点以垂直于该结构表面的方向从结构外部朝该结构表面移动。因此,暴露在结构表面上的端子或其他导电元件可从该表面突出;可与该表面平齐;或可相对该表面凹陷,并通过该结构上的孔或凹坑暴露。第一微电子元件12的触点20暴露在正面16上且位于中部区域13内。例如,触点20可邻近第一表面16中心布置为一排或平行的两排。
第二微电子元件14具有正面22、远离正面的背面24、及在正面与背面之间延伸的第一边缘35和第二边缘37。第二微电子元件14的正面22包括第一端部区域21和第二端部区域23,及位于第一端部区域21与第二端部区域23之间的中部区域19。第一端部区域21在中部区域19与第一边缘35之间延伸,而第二端部区域23在中部区域19与第二边缘37之间延伸。电触点26在第二微电子元件14的正面22暴露。第二微电子元件14的触点26暴露在正面22的中部区域19内。例如,触点26可邻近第一表面22的中心布置为一排或平行的两排。
从图1可以看出,第一微电子元件12和第二微电子元件14相互堆叠。在一些实施例中,第二微电子元件14的正面22和第一微电子元件12的背面18彼此面对。第二微电子元件14的第二端部区域23的至少一部分覆盖第一微电子元件12的第二端部区域17的至少一部分。第二微电子元件14的中部区域19的至少一部分越过第一微电子元件12的第二边缘29而突出。相应地,第二微电子元件14的触点26设置在越过第一微电子元件12的第二边缘29的部位内。
微电子组件10进一步包括具有朝向相反的第一表面32和第二表面34的介电元件30。尽管图1只示出了一个介电元件30,微电子组件10可包括超过一个的介电元件。一个或多个导电元件或端子36暴露在介电元件30的第一表面32上。至少一些端子36可相对于第一微电子元件12和/或第二微电子元件14可移动。
介电元件30可进一步包括一个或多个孔隙。在图1所描述的实施例中,介电元件30包括与第一微电子元件12的中部区域13大致对齐的第一孔隙33、及与第二微电子元件14的中部区域19大致对齐的第二孔隙39,从而提供了到达触点20和26的通道。
从图1中可以看出,介电元件30可越过第一微电子元件12的第一边缘27及第二微电子元件14的第二边缘35而延伸。介电元件30的第二表面34可与第一微电子元件12的正面16并置。介电元件30可部分地或全部由任意适当的介电材料制成。例如,介电元件30可包括柔性材料层,如聚合物、BT (Bismaleimide-triazine,双马来酰亚胺-三嗪)树脂或常用于制造带式自动结合(“TAB”)带的其他介电材料的层。替代地,介电元件30可包含相对刚性的板状材料,如纤维强化的环氧树脂厚层,如Fr-4或Fr-5板。无论采用何种材料,介电元件30都可包括单层或多层介电材料。
介电元件30还可包括暴露在第一表面32的导电元件40以及导电迹线42。导电迹线40使导电元件40与端子36电连接。
如粘接层等的间隔或支撑元件31,可设置在第二微电子元件14的第一端部区域21与介电元件30的一部分之间。如果间隔层31包括粘接剂,则粘接剂可使第二微电子元件14与介电元件30连接。另一间隔层60可设置在第二微电子元件14的第二端部区域23与第一微电子元件12的第二端部区域17之间。此间隔层60可包括,使第一微电子元件12与第二微电子元件14结合在一起的粘接剂。在这种情况下,间隔层60可部分地或全部由裸片粘附粘接剂制成,且可包含低弹性模量的材料,如硅酮弹性体。但是,如果两个微电子元件12、14为由相同材料制成的常规半导体芯片,则间隔层60可全部或部分地由高弹性模量的粘接剂或焊料的薄层制成,因为对应于温度的变化,各微电子元件将倾向于一致地膨胀和收缩。无论采用何种材料,间隔层31、60中每个都可包括单层或多层。
从图1和图2中可以看出,电连接件或引线70使第一微电子元件12的触点20与介电元件30上的一些导电元件40电连接。电连接件70可包括,使微电子元件12的触点与导电元件40电连接的并列的结合引线72、74。结合引线72、74穿过第一孔隙33而延伸,并定位为大致相互平行。每条结合引线72、74都使触点20与介电元件的相应导电元件40电连接。根据本实施例的并列结合引线结构,可通过在相连接的触点之间设置用于电流通过的附加通路,而大大降低结合引线连接的感应系数。
其他电连接件或引线50使第二微电子元件14的触点26与一些导电元件40电连接。电连接件50可包括,使微电子元件14的触点与导电元件40电连接的并列的结合引线52、54。结合引线52、54穿过第二孔隙39延伸,且定位为大致相互平行。结合引线52、54都使触点26与介电元件30的相应元件40电连接。根据本实施例的并列结合引线结构,可通过在相连接的触点之间设置用于电流通过的附加通路,而大大降低结合引线连接的感应系数。
微电子组件10进一步包括至少覆盖第一微电子元件12和第二微电子元件14的上模11。从图1可以看出,上模11还可覆盖介电元件30超出第一微电子元件12的第一边缘27及第二微电子元件14的第一边缘35而延伸的部分。
图3描述了包括至少两个堆叠且电互连的微电子组件900的布置1000。微电子组件900A、900B可为上述的任意组件。至少一个微电子组件可具有附接至端子的导电接合件,如焊料球981或其他,如锡、铟或其组合等金属结合块。两个微电子组件900通过任意适当的导电连接件而相互电连接。例如,各组件可通过焊料柱990而电互连,焊料柱与相应微电子元件的介电元件930A、930B上的垫(未示出)连接。也在图3中示出的特定实施例中,导电柱992和焊料994可用于使两个微电子组件900A和900B电互连。柱992可从第一组件或从第二组件朝着另一组件延伸,或者设置在两个组件上的柱可彼此朝着对方而延伸。
继续参照图3,散热器970可设置在第一微电子组件900A与第二微电子组件900B之间,以帮助均匀散发堆叠微电子组件的布置内的热量。散热器970还可改善热量向周围环境的散发。散热器可部分地或全部由任意适当的导热材料制成。适当导热材料的示例,包括但不限于,金属、石墨、如导热环氧树脂等的导热粘接剂、焊料或类似物,或这些材料的组合物。在一个示例中,散热器可为基本连续的金属板。在特定实施例中,例如采用如导热粘接剂或导热油脂等的导热材料,由金属或其他导热材料制成的预成形的散热器970,可附接或设置在第二微电子组件900B的介电元件930B的正面932B上。如果有粘接剂存在,其可为柔性材料,允许散热器与微电子元件或其附接的介电元件之间相对移动,从而调节柔性附接的各元件之间不同的热膨胀。散热器970可为单体结构,且可包括大致与介电元件930B的孔隙933B、939B分别对齐的一个或多个孔隙972、974。在一个实施例中,散热器970的每个孔隙972、974的尺寸都可容纳覆盖介电元件930B的孔隙933B或939B的密封剂980B或982B。替代地,散热器970可包括彼此间隔开的多个散热部分。尽管没有示出,替代地,散热器970可附接在微电子组件900A的第二微电子元件914A的背面924A上,或附接在第一微电子组件900A的第一微电子元件912A的背面918A上,或散热器970可与两个微电子元件912A、914A的背面都附接。在特定实施例中,散热器可为焊料层或包括焊接层,焊料层与第一微电子元件912A和第二微电子元件914A中一个或多个的背面的至少一部分直接接合。
在本文所描述的任意实施例中,微电子组件都可包括位于微电子组件其他位置的附加散热器。
图4示出了微电子组件1200,如上所述,微电子组件1200包括至少附接至第二微电子元件1214的背面1224的散热器1280。散热器1280可与第二微电子组件1214的整个背面1224热导通,且可越过第二微电子元件的第一边缘1235和第二边缘1237而延伸。支撑元件1290可由硅或其他任意适当的材料制成,且可位于散热器1280与第一微电子元件1212的第一端部区域1215之间。支撑元件可由导热材料制成,如金属、如导电环氧树脂等的填充金属的聚合物材料、石墨、粘接剂、焊料或任意适当的材料制成,以提高组件内及组件与环境之间的热传递和散逸。
另一支撑元件1292可设置在第二微电子元件1214的第一端部区域1221与介电元件1230之间。支撑元件1292可部分地或全部由硅制成。散热器1280可越过第一微电子元件的第一边缘1227和第二边缘1229而延伸。如上所述,散热器1280可全部或部分地由金属、石墨或任意适当的其他导热材料制成,且可通过导热粘接剂或导热油脂附接至组件的其他部分、或与组件的其他部分热连通,导热粘接剂可为柔性的。在一个实施例中,特别是当微电子元件实质上由一种类型如硅等的半导体材料组成时,支撑元件1290、1292可基本上由相同的半导体材料组成。
除了散热器1280以外,微电子组件1200可包括一个或多个导热球1282、1284。导热球1282、1284通常由焊料制成,但其内可包括导热金属的芯,如示为1283的铜球或铜柱。导热球1282可以与第一微电子元件1212的第一边缘1227大致对齐的方式,附接至介电元件1230的正面1232。导热的连接器1286可附接至一个或多个导热球1282,并可穿过介电元件1230而延伸。导热球1284可以与第二微电子元件1214的第一边缘1235大致对齐的方式,附接至介电元件1230的正面1232。导热的连接器1288可附接至一个或多个导热球1284,并可穿过介电元件1230而延伸。
图5示出了图4所描述实施例的变例。在此变例中,微电子组件1300无需包括第一微电子元件1314的第一端部区域1315与散热器1380之间的支撑元件。散热器1380可包括邻近第二微电子元件1314的第二边缘1337的台阶1398。台阶1398使散热器1380能接触、或至少相当接近第一微电子元件1312的背面1318。
图6示出了图3所说明实施例的变例。在图6所描述的变例中,散热器971与微电子组件900B的第一微电子元件912B及第二微电子元件914B热连通。散热器971可具有背向第一微电元件912B的背面918B及第二微电子元件914B的背面924B的大致平坦的第一表面987。另外,散热器971可具有分别朝向第一微电子元件912B的背面918B及第二微电子元件914B的背面924B的大致平坦的第二表面989A和第三表面989B。散热器971可包括与第二微电子元件914B的背面924B热连通并覆盖该背面的第一部分973、及与第一微电子元件912B的背面918B热连通并覆盖该背面的第二部分975。在一个特定实施例中,散热器971的第一部分973可与第二微电子元件914B的部分或整个背面924B热接触,例如通过焊料、导热油脂或导热粘接剂而接触。类似地,散热器971的第二部分975可与第一微电子元件912B的部分或整个背面918B热接触。散热器971的第二部分975可比第一部分973更厚。
继续参照图6,另一散热器977可与微电子组件900A的第一微电子元件912A及第二微电子元件914A热连通。散热器977可包括背向第一微电子元件912A和第二微电子元件914B的基本平坦的第一表面991。此外,散热器977可包括分别朝着第一微电子元件912A的背面918A和第二微电子元件914A的背面924A的基本平坦的第二表面993A、993B。另外,散热器977可包括与第二微电子元件914A的背面924A热连通且覆盖该表面的第一部分979、及与第一微电子元件912A的背面918A热连通且覆盖该表面的第二部分983。在一个特定实施例中,散热器977的第一部分979可与第二微电子元件914A的部分或整个背面924A热接触,与散热器971的布置类似。类似地,散热器977的第二部分983可与第一微电子元件918A的部分或整个背面918A热接触。散热器977的第二部分983可比第一部分973更厚。
导热材料985可设置在散热器977与介电元件930B之间。导电材料985可包括一层或多层的任意适当材料,且可为25微米至100微米厚。适当的导热材料包括但不限于,导热油脂、焊料、铟或任意适当的导热粘接剂。导热材料985可以液态或非完全固化的状态涂敷在介电元件930B和散热器977中一个或二者的表面上。以这种方式,材料可流至其间的空间内。相应地,导热材料可适应其接触的表面的高度变化。在一些实施例中,导热材料985可为单体或整体结构,包括与第一微电子元件912B的触点920和第二微电子元件914B的触点926大致对齐的一个或多个孔隙999。替代地,导热材料985可包括多个间隔开且相分离的部分。在特定实施例中,导热材料985可导电。在这种实施例中,该导电材料可作为导电板而应用,且可与地面电连接。微电子组件900A可包括在第二微电子元件914A与介电元件930之间的支撑元件931。
从图6可以看出,本文描述的任意微电子组件都可与电路面板或电路板电连接。例如,微电子组件500可包括复数个接合单元,如焊接球581或铜柱。焊料球981使微电子组件900A与电路板1300电连接。尽管图6只示出了连接微电子组件500与电路板1300的焊料球981,可以理解的是,任意导电元件都可使电路板1300与微电子组件900A互连。一个或多个导电元件或端子1302暴露在电路板1300的第一表面1304上。电路板1300的第一表面1304面向焊料球981。焊料球981附接至端子1302,从而与电路板1300内的至少一些电路电互连。
上述的微电子组件可在不同的电子系统的构造中利用,如图7所示。例如,根据本发明另一实施例的系统1100包括如上文所述的微电子组件1106与其他电子元器件1108和1110联合。在描述的示例中,元器件1108为半导体芯片,而元器件1110为显示屏,但任意其他元器件都可使用。当然,尽管为清楚图示起见,在图24中只描述了两个附加元器件,该系统可包括任意数量的这种元器件。在另一变例中,可采用任意数量的这种微电子组件。微电子组件1106和元器件1108、1110都安装在以虚线示意性地描述的共同外壳901内,且必要时彼此电互连以形成所需的电路。在所示的示例性系统中,该系统包括如柔性印刷电路板等的电路板1102,且电路板包括使元器件之间彼此互连的大量导电体1104,其中在图13中只示出了一个导电体。但是,这只是示例,任意适当的用于形成电连接的结构都可应用。外壳1101作为便携式外壳而描述,具有用于如移动电话或个人数字助理等的类型,显示屏1110暴露在外壳的表面。其中结构1106包括如成像芯片等的光敏元件,还可配置镜头1111或其他光学器件,以提供光到达结构的路线。同样,图7内所示的简化系统只是示例,其他系统,包括一般被视为固定结构的系统,如台式计算机、路由器及类似的结构,都可应用上述的结构而制成。
可是理解的是,各从属权利要求及其阐述的特征可以与存在于最初权利要求书中的不同的方式组合。也可理解的是,与单个实施例结合进行描述的特征可与其他已描述的实施例共用。
尽管本发明参照特定实施例进行描述,可以理解的是,这些实施例只是说明本发明的原理和应用。因此,应理解为,在不偏离由附加的权利要求书所限定的本发明实质和范围的情况下,说明的实施例可做出许多修改及可设计出其他布置。
Claims (24)
1. 微电子组件,包括:
介电元件,具有朝向相反的第一表面和第二表面、及在两表面间延伸的一个或多个孔隙,所述介电元件上进一步具有导电元件;
第一微电子元件,具有背面和面对所述介电元件的所述第一表面的正面,所述第一微电子元件具有第一边缘及复数个暴露在其所述正面的触点;
第二微电子元件,包括有背面和面对所述第一微电子元件的所述背面的正面,所述第二微电子元件的所述正面的突出部分越过所述第一微电子元件的所述第一边缘而延伸,所述突出部分与所述介电元件的所述第一表面间隔开,所述第二微电子元件具有复数个暴露在所述正面的所述突出部分上的触点;
引线,从所述微电子元件的触点穿过至少一个所述孔隙延伸至所述导电元件中的至少一些导电元件;及
散热器,与所述第一微电子元件及所述第二微电子元件中的至少一个热耦合。
2. 根据权利要求1所述的微电子组件,其中所述引线为结合引线。
3. 根据权利要求1所述的微电子组件,其中所述散热器部分地或全部由石墨制成。
4. 根据权利要求1所述的微电子组件,其中所述散热器包括金属板。
5. 根据权利要求1所述的微电子组件,其中所述散热器至少覆盖所述第一微电子元件的所述背面。
6. 根据权利要求1所述的微电子组件,其中所述散热器至少覆盖所述第二微电子组件的所述背面。
7. 根据权利要求1所述的微电子组件,其中所述散热器覆盖所述第一微电子元件及所述第二微电子元件的背面。
8. 根据权利要求7所述的微电子组件,其中所述散热器包括设置在所述第一微电子元件上方的第一部分、设置在所述第二微电子元件上方的第二部分、及在所述第一部分与所述第二部分之间的台阶。
9. 根据权利要求1所述的微电子组件,进一步包括与所述介电元件热耦合的导热球。
10. 根据权利要求9所述的微电子组件,其中所述导热球附接至所述介电元件的第二表面。
11. 根据权利要求9所述的微电子组件,其中每个导热球都包括嵌入其中的金属芯。
12. 根据权利要求9所述的微电子组件,进一步包括穿过所述介电元件延伸、并使所述导热球中的一个与所述介电元件耦合的导热连接体。
13. 根据权利要求1所述的微电子组件,其中整个所述散热器沿平面延伸。
14. 根据权利要求13所述的微电子组件,进一步包括在所述散热器与所述第一微电子元件之间的支撑元件。
15. 微电子组件,包括:
第一单元和第二单元,每个单元都包括:
(1)介电元件,具有朝向相反的第一表面和第二表面,及在两表面之间延伸的至少一个孔隙,所述介电元件上具有导电元件;
(2)第一微电子元件,具有背面、面向所述介电元件的所述第一表面的正面、边缘、及所述正面上的触点;
(3)第二微电子元件,具有背面、面向所述第一微电子元件的正面、及在所述正面越过所述第一微电子元件的所述边缘突出的部分上的触点;及
(4)信号引线,从所述第一微电子元件和所述第二微电子元件的触点穿过所述至少一个孔隙延伸至所述介电元件上的所述导电元件中的至少一些导电元件,
所述第二单元覆盖所述第一单元的微电子元件,所述组件进一步包括堆叠互连,使所述第一单元的所述介电元件上的所述导电元件中至少一些导电元件与所述第二单元的所述介电元件上的所述导电元件中至少一些导电元件电互连;及
至少一个散热器,设置在所述第一单元与所述第二单元之间。
16. 根据权利要求15所述的微电子组件,其中所述散热器为单体结构,具有与所述第一单元的所述第一微电子元件及所述第二微电子元件的触点大致对齐的孔隙。
17. 根据权利要求15所述的微电子组件,其中所述散热器包括彼此间隔开的散热器部分。
18. 根据权利要求15所述微电子组件,其中所述散热器附接至所述第一单元的所述介电元件的所述第二表面。
19. 根据权利要求15所述的微电子组件,其中所述引线为结合引线。
20. 根据权利要求15所述的微电子组件,其中所述散热器包括朝着所述第一单元的所述第一微电子元件及所述第二微电子元件的各背面的大致平坦的表面。
21. 系统,包括根据权利要求1所述的组件、及与所述组件电连接的一个或多个其他电子元器件。
22. 根据权利要求21所述的系统,进一步包括外壳,所述组件及所述其他电子元器件安装至所述外壳。
23. 系统,包括根据权利要求15所述的组件、及与所述组件电连接的一个或多个其他电子元器件。
24. 根据权利要求23所述的系统,进一步包括外壳,所述组件及所述其他电子元器件安装至所述外壳。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/907,522 | 2010-10-19 | ||
US12/907,522 US8553420B2 (en) | 2010-10-19 | 2010-10-19 | Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics |
PCT/US2011/056352 WO2012054335A1 (en) | 2010-10-19 | 2011-10-14 | Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristic |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103262237A true CN103262237A (zh) | 2013-08-21 |
CN103262237B CN103262237B (zh) | 2016-06-15 |
Family
ID=44903389
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201180060426.0A Expired - Fee Related CN103262237B (zh) | 2010-10-19 | 2011-10-14 | 具有中部触点并改善热性能的增强堆叠微电子组件 |
Country Status (8)
Country | Link |
---|---|
US (3) | US8553420B2 (zh) |
EP (1) | EP2630657A1 (zh) |
JP (1) | JP5883456B2 (zh) |
KR (1) | KR101941615B1 (zh) |
CN (1) | CN103262237B (zh) |
DE (1) | DE202011110802U1 (zh) |
TW (1) | TWI480960B (zh) |
WO (1) | WO2012054335A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20200273768A1 (en) * | 2019-02-27 | 2020-08-27 | Intel Corporation | Crystalline carbon heat spreading materials for ic die hot spot reduction |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8553420B2 (en) | 2010-10-19 | 2013-10-08 | Tessera, Inc. | Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics |
KR101061531B1 (ko) | 2010-12-17 | 2011-09-01 | 테세라 리써치 엘엘씨 | 중앙 콘택을 구비하며 접지 또는 배전을 개선한 적층형 마이크로전자 조립체 |
US8304881B1 (en) | 2011-04-21 | 2012-11-06 | Tessera, Inc. | Flip-chip, face-up and face-down wirebond combination package |
US8952516B2 (en) | 2011-04-21 | 2015-02-10 | Tessera, Inc. | Multiple die stacking for two or more die |
US9013033B2 (en) | 2011-04-21 | 2015-04-21 | Tessera, Inc. | Multiple die face-down stacking for two or more die |
US8970028B2 (en) | 2011-12-29 | 2015-03-03 | Invensas Corporation | Embedded heat spreader for package with multiple microelectronic elements and face-down connection |
US8633576B2 (en) * | 2011-04-21 | 2014-01-21 | Tessera, Inc. | Stacked chip-on-board module with edge connector |
US8928153B2 (en) | 2011-04-21 | 2015-01-06 | Tessera, Inc. | Flip-chip, face-up and face-down centerbond memory wirebond assemblies |
CN104718619A (zh) * | 2012-08-02 | 2015-06-17 | 泰塞拉公司 | 用于两个或更多个裸片的多裸片倒装堆叠 |
JP2015216263A (ja) * | 2014-05-12 | 2015-12-03 | マイクロン テクノロジー, インク. | 半導体装置 |
KR101640126B1 (ko) * | 2014-06-12 | 2016-07-15 | 주식회사 에스에프에이반도체 | 반도체 패키지 제조방법 |
US9953957B2 (en) | 2015-03-05 | 2018-04-24 | Invensas Corporation | Embedded graphite heat spreader for 3DIC |
KR102534732B1 (ko) | 2016-06-14 | 2023-05-19 | 삼성전자 주식회사 | 반도체 패키지 |
CN113491007A (zh) * | 2019-03-11 | 2021-10-08 | Hrl实验室有限责任公司 | 在金属嵌入式芯片组件(meca)处理期间保护晶粒的方法 |
US11049791B1 (en) * | 2019-12-26 | 2021-06-29 | Intel Corporation | Heat spreading layer integrated within a composite IC die structure and methods of forming the same |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020030267A1 (en) * | 2000-09-08 | 2002-03-14 | Fujitsu Quantum Devices Limited | Compound semiconductor device |
US20020053727A1 (en) * | 2000-08-31 | 2002-05-09 | Naoto Kimura | Semiconductor device |
US20050116358A1 (en) * | 2003-11-12 | 2005-06-02 | Tessera,Inc. | Stacked microelectronic assemblies with central contacts |
US20060097379A1 (en) * | 2004-11-10 | 2006-05-11 | Chung-Cheng Wang | Substrate for electrical device and methods for making the same |
CN101034689A (zh) * | 2006-01-16 | 2007-09-12 | 三星电子株式会社 | 双密封半导体封装及其制造方法 |
US20080116557A1 (en) * | 2006-11-16 | 2008-05-22 | Samsung Electronics Co., Ltd. | Semiconductor package having improved heat spreading performance |
TWI301314B (en) * | 2002-03-22 | 2008-09-21 | Broadcom Corp | Low voltage drop and high thermal performance ball grid array package |
CN101315922A (zh) * | 2007-05-30 | 2008-12-03 | 力成科技股份有限公司 | 避免半导体堆叠发生微接触焊点断裂的半导体封装堆叠装置 |
US20090045524A1 (en) * | 2007-08-16 | 2009-02-19 | Tessera, Inc. | Microelectronic package |
KR20100050981A (ko) * | 2008-11-06 | 2010-05-14 | 주식회사 하이닉스반도체 | 반도체 패키지 및 이를 이용한 스택 패키지 |
Family Cites Families (182)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62107391A (ja) | 1985-11-06 | 1987-05-18 | Nippon Texas Instr Kk | 情報記憶媒体 |
US5138438A (en) | 1987-06-24 | 1992-08-11 | Akita Electronics Co. Ltd. | Lead connections means for stacked tab packaged IC chips |
JPH02174255A (ja) | 1988-12-27 | 1990-07-05 | Mitsubishi Electric Corp | 半導体集積回路装置 |
US5148266A (en) | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies having interposer and flexible lead |
US5679977A (en) | 1990-09-24 | 1997-10-21 | Tessera, Inc. | Semiconductor chip assemblies, methods of making same and components for same |
US5148265A (en) | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies with fan-in leads |
US5222014A (en) | 1992-03-02 | 1993-06-22 | Motorola, Inc. | Three-dimensional multi-chip pad array carrier |
US5369552A (en) | 1992-07-14 | 1994-11-29 | Ncr Corporation | Multi-chip module with multiple compartments |
US5998864A (en) | 1995-05-26 | 1999-12-07 | Formfactor, Inc. | Stacking semiconductor devices, particularly memory chips |
US5861666A (en) | 1995-08-30 | 1999-01-19 | Tessera, Inc. | Stacked chip assembly |
KR100204753B1 (ko) | 1996-03-08 | 1999-06-15 | 윤종용 | 엘오씨 유형의 적층 칩 패키지 |
JP2806357B2 (ja) | 1996-04-18 | 1998-09-30 | 日本電気株式会社 | スタックモジュール |
US5892660A (en) | 1996-08-29 | 1999-04-06 | Micron Technology, Inc. | Single in line memory module adapter |
WO1998012568A1 (en) | 1996-09-18 | 1998-03-26 | Hitachi, Ltd. | Process for producing semiconductor device and semiconductor device |
WO1998025304A1 (fr) | 1996-12-04 | 1998-06-11 | Hitachi, Ltd. | Dispositif a semi-conducteur |
JP2978861B2 (ja) | 1997-10-28 | 1999-11-15 | 九州日本電気株式会社 | モールドbga型半導体装置及びその製造方法 |
JP3718039B2 (ja) | 1997-12-17 | 2005-11-16 | 株式会社日立製作所 | 半導体装置およびそれを用いた電子装置 |
US6742098B1 (en) | 2000-10-03 | 2004-05-25 | Intel Corporation | Dual-port buffer-to-memory interface |
US6021048A (en) | 1998-02-17 | 2000-02-01 | Smith; Gary W. | High speed memory module |
US6150724A (en) | 1998-03-02 | 2000-11-21 | Motorola, Inc. | Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces |
US6072233A (en) | 1998-05-04 | 2000-06-06 | Micron Technology, Inc. | Stackable ball grid array package |
US6180881B1 (en) | 1998-05-05 | 2001-01-30 | Harlan Ruben Isaak | Chip stack and method of making same |
US6369444B1 (en) | 1998-05-19 | 2002-04-09 | Agere Systems Guardian Corp. | Packaging silicon on silicon multichip modules |
US5977640A (en) | 1998-06-26 | 1999-11-02 | International Business Machines Corporation | Highly integrated chip-on-chip packaging |
US7525813B2 (en) | 1998-07-06 | 2009-04-28 | Renesas Technology Corp. | Semiconductor device |
US6353539B1 (en) | 1998-07-21 | 2002-03-05 | Intel Corporation | Method and apparatus for matched length routing of back-to-back package placement |
US6121576A (en) | 1998-09-02 | 2000-09-19 | Micron Technology, Inc. | Method and process of contact to a heat softened solder ball array |
US6093029A (en) | 1998-09-08 | 2000-07-25 | S3 Incorporated | Vertically stackable integrated circuit |
US6201695B1 (en) | 1998-10-26 | 2001-03-13 | Micron Technology, Inc. | Heat sink for chip stacking applications |
US6815251B1 (en) | 1999-02-01 | 2004-11-09 | Micron Technology, Inc. | High density modularity for IC's |
SE519108C2 (sv) | 1999-05-06 | 2003-01-14 | Sandvik Ab | Belagt skärverktyg för bearbetning av grått gjutjärn |
TW409377B (en) | 1999-05-21 | 2000-10-21 | Siliconware Precision Industries Co Ltd | Small scale ball grid array package |
KR100393095B1 (ko) | 1999-06-12 | 2003-07-31 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지와 그 제조방법 |
JP3360655B2 (ja) | 1999-07-08 | 2002-12-24 | 日本電気株式会社 | 半導体装置 |
JP2001053243A (ja) | 1999-08-06 | 2001-02-23 | Hitachi Ltd | 半導体記憶装置とメモリモジュール |
US6199743B1 (en) | 1999-08-19 | 2001-03-13 | Micron Technology, Inc. | Apparatuses for forming wire bonds from circuitry on a substrate to a semiconductor chip, and methods of forming semiconductor chip assemblies |
JP2001196407A (ja) | 2000-01-14 | 2001-07-19 | Seiko Instruments Inc | 半導体装置および半導体装置の形成方法 |
US6369448B1 (en) | 2000-01-21 | 2002-04-09 | Lsi Logic Corporation | Vertically integrated flip chip semiconductor package |
US6414396B1 (en) | 2000-01-24 | 2002-07-02 | Amkor Technology, Inc. | Package for stacked integrated circuits |
JP3768761B2 (ja) | 2000-01-31 | 2006-04-19 | 株式会社日立製作所 | 半導体装置およびその製造方法 |
JP2001223324A (ja) * | 2000-02-10 | 2001-08-17 | Mitsubishi Electric Corp | 半導体装置 |
TW579555B (en) * | 2000-03-13 | 2004-03-11 | Ibm | Semiconductor chip package and packaging of integrated circuit chip in electronic apparatus |
US6731009B1 (en) | 2000-03-20 | 2004-05-04 | Cypress Semiconductor Corporation | Multi-die assembly |
KR100583491B1 (ko) | 2000-04-07 | 2006-05-24 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 및 그 제조방법 |
JP3874062B2 (ja) | 2000-09-05 | 2007-01-31 | セイコーエプソン株式会社 | 半導体装置 |
US6492726B1 (en) | 2000-09-22 | 2002-12-10 | Chartered Semiconductor Manufacturing Ltd. | Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection |
TW511405B (en) | 2000-12-27 | 2002-11-21 | Matsushita Electric Ind Co Ltd | Device built-in module and manufacturing method thereof |
SG95637A1 (en) | 2001-03-15 | 2003-04-23 | Micron Technology Inc | Semiconductor/printed circuit board assembly, and computer system |
SG106054A1 (en) | 2001-04-17 | 2004-09-30 | Micron Technology Inc | Method and apparatus for package reduction in stacked chip and board assemblies |
JP2002353398A (ja) * | 2001-05-25 | 2002-12-06 | Nec Kyushu Ltd | 半導体装置 |
US6472741B1 (en) | 2001-07-14 | 2002-10-29 | Siliconware Precision Industries Co., Ltd. | Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same |
US6385049B1 (en) | 2001-07-05 | 2002-05-07 | Walsin Advanced Electronics Ltd | Multi-board BGA package |
JP2003101207A (ja) * | 2001-09-27 | 2003-04-04 | Nec Kyushu Ltd | 半田ボールおよびそれを用いた部品接続構造 |
US6977440B2 (en) | 2001-10-09 | 2005-12-20 | Tessera, Inc. | Stacked packages |
SG118103A1 (en) | 2001-12-12 | 2006-01-27 | Micron Technology Inc | BOC BGA package for die with I-shaped bond pad layout |
KR100480909B1 (ko) | 2001-12-29 | 2005-04-07 | 주식회사 하이닉스반도체 | 적층 칩 패키지의 제조 방법 |
TW523890B (en) | 2002-02-07 | 2003-03-11 | Macronix Int Co Ltd | Stacked semiconductor packaging device |
SG121705A1 (en) | 2002-02-21 | 2006-05-26 | United Test & Assembly Ct Ltd | Semiconductor package |
DE10215654A1 (de) | 2002-04-09 | 2003-11-06 | Infineon Technologies Ag | Elektronisches Bauteil mit mindestens einem Halbleiterchip und Flip-Chip-Kontakten sowie Verfahren zu seiner Herstellung |
US6924496B2 (en) | 2002-05-31 | 2005-08-02 | Fujitsu Limited | Fingerprint sensor and interconnect |
US7482699B2 (en) * | 2002-06-05 | 2009-01-27 | Renesas Technology Corp. | Semiconductor device |
US7132311B2 (en) * | 2002-07-26 | 2006-11-07 | Intel Corporation | Encapsulation of a stack of semiconductor dice |
JP2004063767A (ja) | 2002-07-29 | 2004-02-26 | Renesas Technology Corp | 半導体装置 |
US6762942B1 (en) | 2002-09-05 | 2004-07-13 | Gary W. Smith | Break away, high speed, folded, jumperless electronic assembly |
TW557556B (en) | 2002-09-10 | 2003-10-11 | Siliconware Precision Industries Co Ltd | Window-type multi-chip semiconductor package |
US7495326B2 (en) | 2002-10-22 | 2009-02-24 | Unitive International Limited | Stacked electronic structures including offset substrates |
US7268425B2 (en) * | 2003-03-05 | 2007-09-11 | Intel Corporation | Thermally enhanced electronic flip-chip packaging with external-connector-side die and method |
TW200419752A (en) | 2003-03-18 | 2004-10-01 | United Test Ct Inc | Semiconductor package with heat sink |
TWI313049B (en) | 2003-04-23 | 2009-08-01 | Advanced Semiconductor Eng | Multi-chips stacked package |
US7528421B2 (en) * | 2003-05-05 | 2009-05-05 | Lamina Lighting, Inc. | Surface mountable light emitting diode assemblies packaged for high temperature operation |
KR20050001159A (ko) | 2003-06-27 | 2005-01-06 | 삼성전자주식회사 | 복수개의 플립 칩들을 갖는 멀티칩 패키지 및 그 제조방법 |
SG148877A1 (en) | 2003-07-22 | 2009-01-29 | Micron Technology Inc | Semiconductor substrates including input/output redistribution using wire bonds and anisotropically conductive film, methods of fabrication and assemblies including same |
US7462936B2 (en) | 2003-10-06 | 2008-12-09 | Tessera, Inc. | Formation of circuitry with modification of feature height |
US7095104B2 (en) | 2003-11-21 | 2006-08-22 | International Business Machines Corporation | Overlap stacking of center bus bonded memory chips for double density and method of manufacturing the same |
JP2005166892A (ja) | 2003-12-02 | 2005-06-23 | Kingpak Technology Inc | スタック型小型メモリカード |
DE10360708B4 (de) | 2003-12-19 | 2008-04-10 | Infineon Technologies Ag | Halbleitermodul mit einem Halbleiterstapel, Umverdrahtungsplatte, und Verfahren zur Herstellung derselben |
US20050173807A1 (en) | 2004-02-05 | 2005-08-11 | Jianbai Zhu | High density vertically stacked semiconductor device |
JP2005251957A (ja) | 2004-03-04 | 2005-09-15 | Renesas Technology Corp | 半導体装置 |
US7489517B2 (en) * | 2004-04-05 | 2009-02-10 | Thomas Joel Massingill | Die down semiconductor package |
US7078808B2 (en) | 2004-05-20 | 2006-07-18 | Texas Instruments Incorporated | Double density method for wirebond interconnect |
CN100552926C (zh) * | 2004-05-21 | 2009-10-21 | 日本电气株式会社 | 半导体器件、配线基板及其制造方法 |
KR20050119414A (ko) | 2004-06-16 | 2005-12-21 | 삼성전자주식회사 | 에지 패드형 반도체 칩의 스택 패키지 및 그 제조방법 |
KR20060004298A (ko) | 2004-07-09 | 2006-01-12 | 삼성테크윈 주식회사 | 무선 전자 라벨 |
US7381593B2 (en) | 2004-08-05 | 2008-06-03 | St Assembly Test Services Ltd. | Method and apparatus for stacked die packaging |
JP4445351B2 (ja) * | 2004-08-31 | 2010-04-07 | 株式会社東芝 | 半導体モジュール |
JP4601365B2 (ja) | 2004-09-21 | 2010-12-22 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US20060097400A1 (en) * | 2004-11-03 | 2006-05-11 | Texas Instruments Incorporated | Substrate via pad structure providing reliable connectivity in array package devices |
US7217994B2 (en) | 2004-12-01 | 2007-05-15 | Kyocera Wireless Corp. | Stack package for high density integrated circuits |
TWI256092B (en) | 2004-12-02 | 2006-06-01 | Siliconware Precision Industries Co Ltd | Semiconductor package and fabrication method thereof |
JP2006172122A (ja) | 2004-12-15 | 2006-06-29 | Toshiba Corp | カード状記憶装置 |
CN100435324C (zh) * | 2004-12-20 | 2008-11-19 | 半导体元件工业有限责任公司 | 具有增强散热性的半导体封装结构 |
JP4086068B2 (ja) * | 2004-12-27 | 2008-05-14 | 日本電気株式会社 | 半導体装置 |
KR20060080424A (ko) | 2005-01-05 | 2006-07-10 | 삼성전자주식회사 | 멀티 칩 패키지를 장착하는 메모리 카드 |
US7205656B2 (en) | 2005-02-22 | 2007-04-17 | Micron Technology, Inc. | Stacked device package for peripheral and center device pad layout device |
KR100630741B1 (ko) * | 2005-03-04 | 2006-10-02 | 삼성전자주식회사 | 다중 몰딩에 의한 적층형 반도체 패키지 및 그 제조방법 |
US7196427B2 (en) | 2005-04-18 | 2007-03-27 | Freescale Semiconductor, Inc. | Structure having an integrated circuit on another integrated circuit with an intervening bent adhesive element |
US7250675B2 (en) | 2005-05-05 | 2007-07-31 | International Business Machines Corporation | Method and apparatus for forming stacked die and substrate structures for increased packing density |
KR101070913B1 (ko) * | 2005-05-19 | 2011-10-06 | 삼성테크윈 주식회사 | 반도체 칩 적층 패키지 |
US7402911B2 (en) | 2005-06-28 | 2008-07-22 | Infineon Technologies Ag | Multi-chip device and method for producing a multi-chip device |
SG130066A1 (en) | 2005-08-26 | 2007-03-20 | Micron Technology Inc | Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices |
DE102005041451A1 (de) | 2005-08-31 | 2007-03-01 | Infineon Technologies Ag | Elektronische Steckeinheit |
JP4108701B2 (ja) | 2005-09-12 | 2008-06-25 | 株式会社ルネサステクノロジ | Icカードの製造方法 |
US7602054B2 (en) * | 2005-10-05 | 2009-10-13 | Semiconductor Components Industries, L.L.C. | Method of forming a molded array package device having an exposed tab and structure |
US20070152310A1 (en) | 2005-12-29 | 2007-07-05 | Tessera, Inc. | Electrical ground method for ball stack package |
JP2007188916A (ja) * | 2006-01-11 | 2007-07-26 | Renesas Technology Corp | 半導体装置 |
KR100673965B1 (ko) | 2006-01-11 | 2007-01-24 | 삼성테크윈 주식회사 | 인쇄회로기판 및 반도체 패키지 제조방법 |
US20070176297A1 (en) | 2006-01-31 | 2007-08-02 | Tessera, Inc. | Reworkable stacked chip assembly |
CN101375299B (zh) | 2006-02-02 | 2012-08-08 | 松下电器产业株式会社 | 存储卡及存储卡的制造方法 |
SG135074A1 (en) | 2006-02-28 | 2007-09-28 | Micron Technology Inc | Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices |
KR20070088177A (ko) | 2006-02-24 | 2007-08-29 | 삼성테크윈 주식회사 | 반도체 패키지 및 그 제조 방법 |
US20080029879A1 (en) * | 2006-03-01 | 2008-02-07 | Tessera, Inc. | Structure and method of making lidded chips |
US7514780B2 (en) * | 2006-03-15 | 2009-04-07 | Hitachi, Ltd. | Power semiconductor device |
US7368319B2 (en) | 2006-03-17 | 2008-05-06 | Stats Chippac Ltd. | Stacked integrated circuit package-in-package system |
US7768075B2 (en) * | 2006-04-06 | 2010-08-03 | Fairchild Semiconductor Corporation | Semiconductor die packages using thin dies and metal substrates |
CN100511588C (zh) | 2006-04-14 | 2009-07-08 | 泰特科技股份有限公司 | 导线架型芯片级封装方法 |
SG136822A1 (en) | 2006-04-19 | 2007-11-29 | Micron Technology Inc | Integrated circuit devices with stacked package interposers |
TW200743190A (en) | 2006-05-10 | 2007-11-16 | Chung-Cheng Wang | A heat spreader for electrical device |
JP5026736B2 (ja) | 2006-05-15 | 2012-09-19 | パナソニックヘルスケア株式会社 | 冷凍装置 |
CN101473437B (zh) * | 2006-06-20 | 2011-01-12 | Nxp股份有限公司 | 集成电路以及采用该集成电路的装置 |
US20080023805A1 (en) | 2006-07-26 | 2008-01-31 | Texas Instruments Incorporated | Array-Processed Stacked Semiconductor Packages |
TWI306658B (en) | 2006-08-07 | 2009-02-21 | Chipmos Technologies Inc | Leadframe on offset stacked chips package |
US7638868B2 (en) * | 2006-08-16 | 2009-12-29 | Tessera, Inc. | Microelectronic package |
US7906844B2 (en) | 2006-09-26 | 2011-03-15 | Compass Technology Co. Ltd. | Multiple integrated circuit die package with thermal performance |
TWI370515B (en) | 2006-09-29 | 2012-08-11 | Megica Corp | Circuit component |
KR100825784B1 (ko) | 2006-10-18 | 2008-04-28 | 삼성전자주식회사 | 휨 및 와이어 단선을 억제하는 반도체 패키지 및 그제조방법 |
US7772683B2 (en) | 2006-12-09 | 2010-08-10 | Stats Chippac Ltd. | Stacked integrated circuit package-in-package system |
JP2008177241A (ja) * | 2007-01-16 | 2008-07-31 | Toshiba Corp | 半導体パッケージ |
WO2008093414A1 (ja) | 2007-01-31 | 2008-08-07 | Fujitsu Microelectronics Limited | 半導体装置及びその製造方法 |
JP5285224B2 (ja) | 2007-01-31 | 2013-09-11 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 回路装置 |
JP2008198841A (ja) | 2007-02-14 | 2008-08-28 | Elpida Memory Inc | 半導体装置 |
JP2008235576A (ja) * | 2007-03-20 | 2008-10-02 | Fujitsu Ltd | 電子部品の放熱構造及び半導体装置 |
US7638869B2 (en) * | 2007-03-28 | 2009-12-29 | Qimonda Ag | Semiconductor device |
US20080237844A1 (en) * | 2007-03-28 | 2008-10-02 | Aleksandar Aleksov | Microelectronic package and method of manufacturing same |
US20080237887A1 (en) * | 2007-03-29 | 2008-10-02 | Hem Takiar | Semiconductor die stack having heightened contact for wire bond |
US7872356B2 (en) | 2007-05-16 | 2011-01-18 | Qualcomm Incorporated | Die stacking system and method |
US20080296717A1 (en) * | 2007-06-01 | 2008-12-04 | Tessera, Inc. | Packages and assemblies including lidded chips |
JP2008306128A (ja) | 2007-06-11 | 2008-12-18 | Shinko Electric Ind Co Ltd | 半導体装置およびその製造方法 |
US7868445B2 (en) * | 2007-06-25 | 2011-01-11 | Epic Technologies, Inc. | Integrated structures and methods of fabrication thereof with fan-out metallization on a chips-first chip layer |
SG148901A1 (en) | 2007-07-09 | 2009-01-29 | Micron Technology Inc | Packaged semiconductor assemblies and methods for manufacturing such assemblies |
KR101341566B1 (ko) | 2007-07-10 | 2013-12-16 | 삼성전자주식회사 | 소켓, 검사 장치, 그리고 적층형 반도체 소자 제조 방법 |
US7442045B1 (en) * | 2007-08-17 | 2008-10-28 | Centipede Systems, Inc. | Miniature electrical ball and tube socket with self-capturing multiple-contact-point coupling |
US20090051043A1 (en) | 2007-08-21 | 2009-02-26 | Spansion Llc | Die stacking in multi-die stacks using die support mechanisms |
US7872340B2 (en) | 2007-08-31 | 2011-01-18 | Stats Chippac Ltd. | Integrated circuit package system employing an offset stacked configuration |
US7880310B2 (en) | 2007-09-28 | 2011-02-01 | Intel Corporation | Direct device attachment on dual-mode wirebond die |
US7851267B2 (en) * | 2007-10-18 | 2010-12-14 | Infineon Technologies Ag | Power semiconductor module method |
JP2009164160A (ja) * | 2007-12-28 | 2009-07-23 | Panasonic Corp | 半導体デバイス積層体および実装方法 |
US20090166065A1 (en) * | 2008-01-02 | 2009-07-02 | Clayton James E | Thin multi-chip flex module |
JP5207868B2 (ja) | 2008-02-08 | 2013-06-12 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US8138610B2 (en) | 2008-02-08 | 2012-03-20 | Qimonda Ag | Multi-chip package with interconnected stacked chips |
US8354742B2 (en) | 2008-03-31 | 2013-01-15 | Stats Chippac, Ltd. | Method and apparatus for a package having multiple stacked die |
US8159052B2 (en) * | 2008-04-10 | 2012-04-17 | Semtech Corporation | Apparatus and method for a chip assembly including a frequency extending device |
US7928562B2 (en) * | 2008-07-22 | 2011-04-19 | International Business Machines Corporation | Segmentation of a die stack for 3D packaging thermal management |
US20100044861A1 (en) * | 2008-08-20 | 2010-02-25 | Chin-Tien Chiu | Semiconductor die support in an offset die stack |
US8253231B2 (en) | 2008-09-23 | 2012-08-28 | Marvell International Ltd. | Stacked integrated circuit package using a window substrate |
KR101479461B1 (ko) | 2008-10-14 | 2015-01-06 | 삼성전자주식회사 | 적층 패키지 및 이의 제조 방법 |
JP5056718B2 (ja) | 2008-10-16 | 2012-10-24 | 株式会社デンソー | 電子装置の製造方法 |
JP5176893B2 (ja) * | 2008-11-18 | 2013-04-03 | 日立金属株式会社 | はんだボール |
US8049339B2 (en) | 2008-11-24 | 2011-11-01 | Powertech Technology Inc. | Semiconductor package having isolated inner lead |
US7951643B2 (en) | 2008-11-29 | 2011-05-31 | Stats Chippac Ltd. | Integrated circuit packaging system with lead frame and method of manufacture thereof |
KR101011863B1 (ko) | 2008-12-02 | 2011-01-31 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 그 제조 방법 |
US20100193930A1 (en) | 2009-02-02 | 2010-08-05 | Samsung Electronics Co., Ltd. | Multi-chip semiconductor devices having conductive vias and methods of forming the same |
US8026589B1 (en) | 2009-02-23 | 2011-09-27 | Amkor Technology, Inc. | Reduced profile stackable semiconductor package |
EP2406821A2 (en) * | 2009-03-13 | 2012-01-18 | Tessera, Inc. | Stacked microelectronic assemblies having vias extending through bond pads |
TWI401785B (zh) | 2009-03-27 | 2013-07-11 | Chipmos Technologies Inc | 多晶片堆疊封裝 |
US8039316B2 (en) | 2009-04-14 | 2011-10-18 | Stats Chippac Ltd. | Integrated circuit packaging system with stacked integrated circuit and heat spreader with openings and method of manufacture thereof |
KR101601847B1 (ko) | 2009-05-21 | 2016-03-09 | 삼성전자주식회사 | 반도체 패키지 |
KR20100134354A (ko) | 2009-06-15 | 2010-12-23 | 삼성전자주식회사 | 반도체 패키지, 스택 모듈, 카드 및 전자 시스템 |
TWM370767U (en) | 2009-06-19 | 2009-12-11 | fu-zhi Huang | Modulized computer |
US20100327419A1 (en) | 2009-06-26 | 2010-12-30 | Sriram Muthukumar | Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same |
US20110085304A1 (en) | 2009-10-14 | 2011-04-14 | Irvine Sensors Corporation | Thermal management device comprising thermally conductive heat spreader with electrically isolated through-hole vias |
US10128206B2 (en) | 2010-10-14 | 2018-11-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive pillar structure |
US8553420B2 (en) | 2010-10-19 | 2013-10-08 | Tessera, Inc. | Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics |
US8378478B2 (en) | 2010-11-24 | 2013-02-19 | Tessera, Inc. | Enhanced stacked microelectronic assemblies with central contacts and vias connected to the central contacts |
KR101061531B1 (ko) | 2010-12-17 | 2011-09-01 | 테세라 리써치 엘엘씨 | 중앙 콘택을 구비하며 접지 또는 배전을 개선한 적층형 마이크로전자 조립체 |
TW201239998A (en) | 2011-03-16 | 2012-10-01 | Walton Advanced Eng Inc | Method for mold array process to prevent peripheries of substrate exposed |
US8970028B2 (en) | 2011-12-29 | 2015-03-03 | Invensas Corporation | Embedded heat spreader for package with multiple microelectronic elements and face-down connection |
US8928153B2 (en) | 2011-04-21 | 2015-01-06 | Tessera, Inc. | Flip-chip, face-up and face-down centerbond memory wirebond assemblies |
US8338963B2 (en) | 2011-04-21 | 2012-12-25 | Tessera, Inc. | Multiple die face-down stacking for two or more die |
US8304881B1 (en) | 2011-04-21 | 2012-11-06 | Tessera, Inc. | Flip-chip, face-up and face-down wirebond combination package |
US8502390B2 (en) | 2011-07-12 | 2013-08-06 | Tessera, Inc. | De-skewed multi-die packages |
US8436457B2 (en) | 2011-10-03 | 2013-05-07 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
US8723327B2 (en) | 2011-10-20 | 2014-05-13 | Invensas Corporation | Microelectronic package with stacked microelectronic units and method for manufacture thereof |
-
2010
- 2010-10-19 US US12/907,522 patent/US8553420B2/en not_active Expired - Fee Related
-
2011
- 2011-10-14 CN CN201180060426.0A patent/CN103262237B/zh not_active Expired - Fee Related
- 2011-10-14 JP JP2013534971A patent/JP5883456B2/ja not_active Expired - Fee Related
- 2011-10-14 WO PCT/US2011/056352 patent/WO2012054335A1/en active Application Filing
- 2011-10-14 KR KR1020137012385A patent/KR101941615B1/ko active IP Right Grant
- 2011-10-14 EP EP11776969.5A patent/EP2630657A1/en not_active Withdrawn
- 2011-10-14 DE DE202011110802.7U patent/DE202011110802U1/de not_active Expired - Lifetime
- 2011-10-19 TW TW100137933A patent/TWI480960B/zh not_active IP Right Cessation
-
2013
- 2013-10-04 US US14/046,233 patent/US8941999B2/en active Active
-
2015
- 2015-01-26 US US14/605,208 patent/US9312239B2/en not_active Expired - Fee Related
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020053727A1 (en) * | 2000-08-31 | 2002-05-09 | Naoto Kimura | Semiconductor device |
US20020030267A1 (en) * | 2000-09-08 | 2002-03-14 | Fujitsu Quantum Devices Limited | Compound semiconductor device |
TWI301314B (en) * | 2002-03-22 | 2008-09-21 | Broadcom Corp | Low voltage drop and high thermal performance ball grid array package |
US20050116358A1 (en) * | 2003-11-12 | 2005-06-02 | Tessera,Inc. | Stacked microelectronic assemblies with central contacts |
US20060097379A1 (en) * | 2004-11-10 | 2006-05-11 | Chung-Cheng Wang | Substrate for electrical device and methods for making the same |
CN101034689A (zh) * | 2006-01-16 | 2007-09-12 | 三星电子株式会社 | 双密封半导体封装及其制造方法 |
US20080116557A1 (en) * | 2006-11-16 | 2008-05-22 | Samsung Electronics Co., Ltd. | Semiconductor package having improved heat spreading performance |
CN101315922A (zh) * | 2007-05-30 | 2008-12-03 | 力成科技股份有限公司 | 避免半导体堆叠发生微接触焊点断裂的半导体封装堆叠装置 |
US20090045524A1 (en) * | 2007-08-16 | 2009-02-19 | Tessera, Inc. | Microelectronic package |
KR20100050981A (ko) * | 2008-11-06 | 2010-05-14 | 주식회사 하이닉스반도체 | 반도체 패키지 및 이를 이용한 스택 패키지 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20200273768A1 (en) * | 2019-02-27 | 2020-08-27 | Intel Corporation | Crystalline carbon heat spreading materials for ic die hot spot reduction |
Also Published As
Publication number | Publication date |
---|---|
JP2013540371A (ja) | 2013-10-31 |
US8553420B2 (en) | 2013-10-08 |
TW201222682A (en) | 2012-06-01 |
WO2012054335A1 (en) | 2012-04-26 |
CN103262237B (zh) | 2016-06-15 |
KR101941615B1 (ko) | 2019-01-23 |
US20120092832A1 (en) | 2012-04-19 |
DE202011110802U1 (de) | 2016-06-15 |
JP5883456B2 (ja) | 2016-03-15 |
KR20140001898A (ko) | 2014-01-07 |
US9312239B2 (en) | 2016-04-12 |
US20140035121A1 (en) | 2014-02-06 |
TWI480960B (zh) | 2015-04-11 |
US20150145117A1 (en) | 2015-05-28 |
EP2630657A1 (en) | 2013-08-28 |
WO2012054335A8 (en) | 2013-06-06 |
US8941999B2 (en) | 2015-01-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103262237B (zh) | 具有中部触点并改善热性能的增强堆叠微电子组件 | |
CN103620773B (zh) | 两个或多个晶元的多晶元背面堆叠 | |
CN103620774B (zh) | 倒装芯片、正面和背面线键合相组合的封装 | |
JP3762844B2 (ja) | 対向マルチチップ用パッケージ | |
US6137164A (en) | Thin stacked integrated circuit device | |
US6525942B2 (en) | Heat dissipation ball grid array package | |
CN103620778A (zh) | 倒装芯片、正面和背面中心键合存储线键合组件 | |
US7495327B2 (en) | Chip stacking structure | |
CN103620772A (zh) | 具有堆叠的面朝下连接的裸片的多芯片模块 | |
US20090032923A1 (en) | Method and apparatus for stacking electrical components using via to provide interconnection | |
US11929337B2 (en) | 3D-interconnect | |
CN114651322A (zh) | 芯片堆叠封装结构、电子设备 | |
CN100524736C (zh) | 堆叠型晶片封装结构 | |
CN115241153A (zh) | 一种多芯片堆叠封装结构及封装方法 | |
US9721928B1 (en) | Integrated circuit package having two substrates | |
CN101118901A (zh) | 堆叠式芯片封装结构、芯片封装结构及其制程 | |
CN112614830A (zh) | 一种封装模组及电子设备 | |
TWI805164B (zh) | 垂直式多晶片裝置 | |
TWI781863B (zh) | 平面式多晶片裝置 | |
KR101811738B1 (ko) | 중앙 콘택을 구비한 적층형 마이크로전자 조립체 | |
CN104718619A (zh) | 用于两个或更多个裸片的多裸片倒装堆叠 | |
JP2006108150A (ja) | 半導体装置及び半導体装置の実装方法 | |
CN117393534A (zh) | 一种芯片封装结构及电子设备 | |
CN115472602A (zh) | 封装结构及其制作方法 | |
KR20000001313A (ko) | 적층형 반도체 패키지 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160615 Termination date: 20171014 |
|
CF01 | Termination of patent right due to non-payment of annual fee |