CN102214641A - 具堆栈功能的晶圆级半导体封装件 - Google Patents

具堆栈功能的晶圆级半导体封装件 Download PDF

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CN102214641A
CN102214641A CN2010102910323A CN201010291032A CN102214641A CN 102214641 A CN102214641 A CN 102214641A CN 2010102910323 A CN2010102910323 A CN 2010102910323A CN 201010291032 A CN201010291032 A CN 201010291032A CN 102214641 A CN102214641 A CN 102214641A
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semiconductor subassembly
coupling assembling
group
semiconductor
active surface
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CN102214641B (zh
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丁一权
陈家庆
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

具有堆栈功能的晶圆级半导体封装件及相关堆栈封装组装件及方法于此叙述。在一实施例中，一半导体封装件包含一组连接组件，其设置邻接于一组堆栈的半导体组件。至少有一连接组件为焊线接合于一堆栈于上方的半导体组件的一主动表面。

Description

具堆栈功能的晶圆级半导体封装件
技术领域
本发明是有关于一种半导体封装件，且特别是有关于一种具有堆栈功能的晶圆级半导体封装件。
背景技术
半导体组件日趋复杂，使其至少需要在某种程度上缩小尺寸以及增强功能。然而在缩小尺寸以及增强功能得到好处的时候，半导体组件也同时产生出相应的问题。
在一般的晶圆级封装，半导体组件先封装于晶圆中，在对晶圆作切割工艺。如此，一般的晶圆级封装会受限于一扇入结构(即电性接触件)，而一完成的半导体封装件的其它组件会被限制在由半导体组件周围所定义的区域。任何设置于半导体组件周围外的组件通常不被支持，且一般皆在切割工艺中被移除。在组件持续微缩而组件功能持续增加的情况下，此一扇入结构的限制将形成挑战。
电子产品通常必须在有限的空间中容置高密度的半导体组件。举例来说，对于制造者、内存组件、及其它主动或被动组件来说，在手机、PDA、膝上型计算机、及其它可携式消费产品中可用的空间是更进一步受到限制的。在半导体封装件中的半导体封装可在电子产品内产生额外新增的有用空间。如此，现有的强大的技术趋势是倾向在一半导体封装件所占有的一脚位区域(footprint)下增加半导体组件密度。不幸的是，一般传统的晶圆级封装对于处理此技术趋势是不恰当的。
这和背景有所冲突，因而产生发展晶圆级半导体封装件、相关的堆栈封装组装件及方法的需求。
发明内容
根据本发明的一方面提供一种具有堆栈功能的晶圆级半导体封装件及相关堆栈封装组装件。在一实施例中，一半导体封装件包括：(1)一重新分布单元包括一上表面；(2)一组堆栈半导体组件包括：(a)一第一半导体组件设置邻接于重新分布单元，且包括一第一主动表面，此第一主动表面面对重新分布单元的上表面，以及(b)一第二半导体组件设置邻接于该第一半导体组件，且包括一第二主动表面，此第二主动表面背向于第一主动表面；(3)一组连接组件设置邻接于堆栈半导体组件的一周围，且皆由重新分布单元的上表面向上延伸，此连接组件包括：(a)一第一连接组件包括一第一上底端，以及(b)一第二连接组件包括一第二上底端，第二上底端焊线接合至第二半导体组件的第二主动表面；以及(4)一封装体设置邻接于重新分布单元的上表面，且覆盖此堆栈半导体组件及连接组件，封装体包括一中央上表面和一外围上表面，封装体之中央上表面位于第二半导体组件的第二主动表面的上，第一连接组件的第一上底端暴露邻接于封装体的外围上表面。
根据本发明的另一方面，提出一种形成具有堆栈功能的晶圆级半导体封装件的制造方法。在一实施例中，一制造方法包括：(1)提供一第一半导体组件及一第二半导体组件，第一半导体组件包括一第一主动表面，第二半导体组件包括一第二主动表面；(2)堆栈第一半导体组件及第二半导体组件，使第一主动表面及第二主动表面彼此相背；(3)施加一第一封胶材料形成封胶结构，以覆盖第一半导体组件及第二半导体组件的边缘，封胶结构包括一前表面及一相对的背表面，第一半导体组件的第一主动表面至少部分暴露邻接封胶结构之前表面，第二半导体组件的第二主动表面至少部分暴露邻接封胶结构的背表面；(4)形成一组通孔，此组通孔于封胶结构之前表面和背表面间作延伸，且环绕第一半导体组件及第二半导体组件；(5)施加一导电材料于通孔中以形成一组连接组件；(6)形成一重新分布单元，此重新分布单元邻接于第一半导体组件的第一主动表面及封胶结构之前表面；(7)通过一组焊线，用以电性连接第二半导体组件的第二主动表面至连接组件中的至少其中之一；以及(8)施加一第二封胶材料，此第二封胶材料邻接于第二半导体组件的第二主动表面及封胶结构的背表面，以形成一封胶体，此封胶体包括一中央部分及一外围部分，中央部分有一中央厚度HP1以覆盖第二半导体组件的第二主动表面及焊线，外围部分有一外围厚度HP2以至少部分暴露至少一组连接组件的一底端。
本发明的其它方面和实施例也都被仔细考虑。前述发明内容及相关特殊实施例的详细描述并非用以限制本发明，仅用于说明本发明的部分实施例。
附图说明
图1A绘示依照本发明一较佳实施例的晶圆级半导体封装件的示意图。
图1B绘示一图1A中的线A-A的封装件的剖面图。
图2A～2B绘示于图1A及图1B中利用封装形成的一拉长、堆栈封装组装件剖面图。
图3绘示一于图1A及图1B中利用封装形成的一堆栈封装组装件剖面图。
图4A～4H绘示形成图1A及图1B中的封装件的制造方法。
主要组件符号说明：
100：封装件
102、104：半导体组件
106、110、120：下表面
108、112、122：上表面
114a、114b、116a、116b、204：接触垫
118：重新分布单元
124、126、146、148：侧向表面
128、130：介电层
132：导电层
132a、132b、132c、132d、150a、150b、304a、304b：电性接触件
134a、134b、134c：电性互连件
136a、136b、136c、136d：连接组件
138：焊线
140：封装体
142：中央上表面
144：外围上表面
200：导电柱
202：导电通道
300：堆栈封装组装件
302：半导体封装件
400：载具
402、412：封胶材料
404：封胶结构
406a、406b、406c、406d：通孔
408：前表面
410：背表面
418：导电材料
HP1：中央厚度
HP2：外围厚度
HC：高度
WC：宽度
具体实施方式
下列定义本发明的某些实施例在某些观点上的应用说明。这些定义同样也可以与此的上作延伸。
除非内文中明确地指明，否则于此所用的单数项“a”、“an”以及“the”包含了数个指示对象。故举例来说，除非内文中明确地指明，否则当提及一电性互连件时，此一电性互连件可包含数个电性互连件。
于此所用的项目“set”表示一个或多个组件的集合。故举例来说，一层组可以包含单一个层或多个层。一组的组件(components of a set)也可以视为是此组的一部份(members of the set)。一组的组件可以是相同或不同的。在某些例子中，一组的组件可以共享一个或多个共同的特征。
于此所用的项目“adjacent”表示邻近或靠近。邻近的数个组件可彼此相互分开或者是实质上彼此相互直接接触。在某些例子中，邻近的数个组件可以彼此相互连接或者是一体成形。
于此所用例如是“inner”、“interior”、“outer”、“exterior”、“top”、“bottom”、“front”、“back”、“upper”、“upwardly”、“lower”、“downwardly”、“vertical”、“vertically”、“lateral”、“laterally”、“above”以及“below”的相关项目表示一组件组相对于另一组件组的方向，例如是如图式所示，但此些组件在制造过程中或使用中并不需要局限在特定的方向。
于此所用的项目“connect”、“connected”以及“connection”表示操作上的耦合或连结。数个连接组件可以彼此相互直接耦合，或者是彼此相互间接耦合，彼此相互间接耦接例如经由另一组的组件来达成。
于此所用的项目“substantially”以及“substantial”表示一应考虑的等级程度或范围。当上述的项目连同一个事件或情况一起使用时，上述的项目可以表示事件或情况准确地发生的实例，以及可以表示事件或情况在非常接近地状况下发生的实例，例如像是在此说明的一般制造操作的容忍程度。
于此所用的项目“electrically conductive”以及“electrically conductivity”表示一电流传输的能力。电性传导材料通常是那些显现出极小或者没有反抗电流流通的材料。每公尺数个西门子(Siemens per meter，“S·m-1”)为导电性的一种度量单位。一般来说，一电性传导材料具有大于104S·m-1的传导性，例如是最少约为105S·m-1或者最少约为106S·m-1。一材料的导电性有时可以随温度而变化。除非另有明确说明，一材料的导电性是于室温下所定义。
首先请参照图1A和图1B，图1A和图1B绘示依照本发明实施例的晶圆级半导体封装件100的示意图。其中图1A绘示封装件100的示意图，而图1B绘示乃图1A的封装件100沿着图1A的A-A线的剖面图。
请参照图1B，封装件100包括数个半导体组件，其中包括半导体组件102及半导体组件104，半导体组件104设置邻接于半导体组件102。在此实施例，于封装件100中，半导体组件102及104被设置为一堆栈结构，组件彼此之间为一安全的合适形式，比如利用一晶粒贴附薄膜或一黏着层。于封装件100中，此半导体组件102及104的堆栈结构具有可在一给定的脚位区域之下，于封装件100中达到一更高密度的半导体组件的优点。虽然图1B中绘示二个半导体组件102及104，在其它实施中，其中亦可以包括更多或更少的半导体组件来用以实现其它的应用。更特别的是，经由额外增加的半导体组件在封装件100中，可以实现出具有更高密度的半导体组件。
如图1B所示，半导体组件102包括一上表面108和一下表面106，上表面108为半导体组件102的背表面，而下表面106为半导体组件102的一主动表面，下表面106上具有接触垫114a和114b，接触垫114a和114b和下表面106邻接设置。半导体组件104包括一下表面110和一上表面112，下表面110为半导体组件104的一背表面，上表面112为半导体组件104的一主动表面，上表面112上具有接触垫116a和116b，接触垫116a和116b和上表面112邻接设置。接触垫114a和114b为半导体组件102提供输入电性连接点和输出电性连接点，而接触垫116a和116b为半导体组件104提供输入电性连接点和输出电性连接点。在此实施例中，半导体组件102和104为一背对背堆栈结构来设置，如此，半导体组件102和104的背表面彼此面对，而半导体组件102和104的主动表面为彼此背向。然而，可以推想得到的是，在其它实际应用情形中，半导体组件102和104的堆栈可以具有不同的结构。于此实施例中，虽然各半导体组件102和104为一半导体芯片，然而一般来说，半导体组件102和104亦可以是任意的主动组件、任意的被动组件、或其中任意组件的组合。如图1B所示，相较于半导体组件104，半导体组件102有一较大的横向延伸，然而半导体组件102也可以具有一较小的横向延伸，或者半导体组件102和104具有一实质上相同的横向延伸。
参照图1A和图1B，封装件100也包括一重新分布单元118，重新分布单元118邻接地设置于半导体组件102的下表面106。重新分布单元118电性连接于半导体组件102和104，其不但提供电性路径，更提供机械稳定度及针对环境因素的保护。如图1A和图1B所示，重新分布单元118包括一下表面120、一上表面122、以及侧向表面124和126，侧向表面124和126邻接地设置于重新分布单元118的周围，且于下表面120和上表面122之间延伸。在此实施例中，各表面120、122、124、及126实质上为平面，侧向表面124和126相对下表面120或上表面122实质上具有直角方向，然而在其它实施中，表面120、122、124、及126的形状及方向可以有所改变。相对于半导体组件102和104，重新分布单元118的周围(由侧向表面124和126所定义)具有较大的侧向范围，因此可使封装件100以扇出结构来实现，即封装件100的组件可设置于由半导体组件102或104周围所定义的区域之内和之外。
在此实施例中，重新分布单元118于制造中形成一组重新分布层，然而在其它实施中，重新分布单元118可以包括一预先形成结构。参照图1B，重新分布单元118为多层的，且包含一对介电层128和130及导电层132，至少部分的导电层132被夹于介电层128及130之间形成三明治结构。一般来说，各一介电层128和130可由一介电材料所形成，此介电材料可为聚合物或非聚合物。举例来说，介电层128和130中至少有一者由聚亚酰胺(polyimide)、聚苯恶唑(polybenzoxazole)、苯环丁烯(benzocyclobutene)或以上材料的组合物所形成。介电层128和130可由相同的介电材料或不同的介电材料形成。就一个实例来说，介电层128和130中至少有一层可由光可成像或感光的介电材料来形成，如此可经由利用微影工艺制作图案来减少制造成本与时间。虽然图1B中绘示二个介电层128和130，然而在其它实施中，其中亦可以包含更多或更少的介电层。
如图1B所示，介电层128具有一组开口，此开口经过位置上的对准及尺寸上的调整，以至少可部分暴露出接触垫114a和114b，且允许接触垫114a和114b电性连接至导电层132，且另一组经过位置上的对准及尺寸上的调整的开口至少部分暴露出导电层132，以邻接至重新分布单元118的上表面122及半导体组件102或104周围的外围。参照图1B，介电层130具有数个开口，此些开口经由位置上的对准，使介电层130至少部分暴露出导电层132，以邻接重新分布单元118的下表面120，且此些开口经过尺寸上的调整以容纳电性接触件132a、132b、132c、及132d。电性接触件132a、132b、132c、及132d为封装件100提供输入电性连接点和输出电性连接点，且电性接触件132a、132b、132c、及132d的至少一个子集通过导电层132电性连接至半导体组件102和104。于此实施例中，电性接触件132a、132b、132c、及132d为焊接凸块，且依照封装件100的扇出结构，电性接触件132a、132b、132c、及132d横向地设置于半导体组件102或104周围的外部。然而，一般来说，电性接触件132a、132b、132c、及132d可以横向地设置于半导体组件102或104周围之内、半导体组件102或104周围之外、或分布于半导体组件102或104周围的内外。据此，经由降低对半导体组件102的接触垫114a和114b的空间设置和间距的相依关系及降低对半导体组件104的接触垫116a和116b的空间设置和间距的相依关系，可使得封装件100的扇出结构可就电性接触件132a、132b、132c、及132d的空间设置和间距的设计提供允许更大的弹性。
对于半导体组件102的接触垫114a和114b以及半导体组件104的接触垫116a和116b来说，导电层132为一重新分布网络，且依照封装件100的扇出结构，导电层132横向地延伸于重新分布单元118中以及半导体组件102或104周围的内部跟外部。如图1B所示，导电层132包括一电性互连件134a、一电性互连件134b，以及一电性互连件134c，电性互连件134a电性连接至电性接触件132a，且暴露并邻接于重新分布单元118的上表面122。电性互连件134b将电性接触件114a和116a电性连接至电性接触件132b，且暴露并邻接于重新分布单元118的上表面122。电性互连件134c将接触垫114b和116b电性连接至电性接触垫132c和132d，且暴露并邻接于重新分布单元118的上表面122。一般来说，各电性互连件134a、134b、及134c可由金属、金属合金、金属或金属合金分散于其中的材料、或另一合适的导电材料形成。举例来说，电性互连件134a、134b、及134c中至少有一可被当作是一组孔洞及一组电性线路，该组孔洞及电性线路由铝、铜、钛或其组合物所形成。电性互连件134a、134b、及134c可由相同的导电材料或不同的导电材料所形成。虽然图1B中绘示一个导电层132，然而在其它实施中，其亦可以包含有额外增加的导电层。
如图1B所示，封装件100也包含了连接组件136a、136b、136c、及136d，连接组件136a、136b、136c、及136d设置于半导体组件102或104周围的外部。连接组件136a、136b、136c、及136d自导电层132向上作延伸。连接组件136a电性连接电性互连件134a，并且自电性互连件134a向上作延伸；连接组件136b电性连接电性互连件134b，并且自电性互连件134b向上作延伸；连接组件136c及136d电性连接电性互连件134c，并且自电性互连件134c向上作延伸。参照图1A和图1B，连接组件136a、136b、136c、及136d以列的形式作分布，其中每一列沿着实质上为矩形图案或为正方型图案的四边做延伸。此些列包括外部列和内部列，外部列包括连接组件136a和136d，而内部列包括连接组件136b和136c。在此实施例中，外部列的连接组件(如连接组件136a和136d)提供数个电性路径，此些电性路径位于封装件100和另一在一堆栈封装组装件中的封装件之间，而内部列的连接组件(如连接组件136b和136c)提供数个电性路径，此些电性路径位于封装件100中，且位于半导体组件104和封装件100的其它组件之间。然而，连接组件136a、136b、136c、及136d其中之一个或多个亦可结合跨封装件(inter-package)和内封装件(intra-package)电性路径。经由提供此些垂直延伸的电性路径，连接组件136a、136b、136c、及136d可使此由导电层132所提供的重新分布网络延伸为三维。据此，连接组件136a、136b、136c、及136d有助于半导体组件102和104在封装件100中的堆栈，以及封装件100和另一个(在堆栈封装组装件中的)封装件间的堆栈，从而在一给定的脚位区域中实现出更高密度的半导体组件。虽然图1B绘示出两列连接组件136a、136b、136c、及136d，然而在其它实施中，其中可以包含有更多或更少列的连接组件，且连接组件136a、136b、136c、及136d在一般情况下可以是任意一种一维图案或二维图案的分布。
在此实施例中，连接组件136a、136b、136c、及136d被作成伸长结构，更进一步的说，导电结构被设置于其中，且至少部分填充其所形成的通孔，依照下述的制造操作。连接组件136a、136b、136c、及136d由金属、金属合金、金属或金属合金分散于其中的材料、或另一合适的导电材料。举例来说，连接组件136a、136b、136c、及136d中的至少一个由铜或铜合金所形成。如图1B所示，各连接组件136a、136b、136c、或136d的尺寸可以是依照连接组件136a、136b、136c、及136d的一高度HC(即是连接组件136a、136b、136c、或136d的垂直范围)以及连接组件136a、136b、136c、或136d的宽度WC(即是连接组件136a、136b、136c、或136d的横向范围)来做明确指定。如果连接组件136a、136b、136c、及136d有一非均匀横向范围，举例来说，该宽度WC可依照一沿着一组直角方向的平均横向范围来指定。对一特殊的实施，每一连接组件136a、136b、136c、或136d的高度HC可在大约100微米到700微米(μm)的范围之间，例如大约150微米到650微米间，或200微米到600微米间，而连接组件136a、136b、136c、或136d的宽度WC可在大约100微米到50微米的范围之间，例如大约150微米到450微米间，或200微米到400微米间。
参照图1B，每一连接组件136a、136b、136c、或136d的上底端实质上对准半导体组件104的上表面112或与其为共平面，而每一连接组件136a、136b、136c、或136d的下底端实质上对准半导体组件102的下表面106或与其为共平面。以另一种方式来说，每一连接组件136a、136b、136c、或136d的高度HC实质上与半导体组件102和104的堆栈结构的垂直延伸总和相等。然而在其它实施中，连接组件136a、136b、136c、及136d的垂直范围，以及连接组件136a、136b、136c、及136d与上表面112及下表面106的对准关可以有所变更的。如图1B所示，半导体组件104通过一组焊线138焊线接合至连接组件136b和136c，此组焊线138将连接垫116a和116b分别电性连接至连接组件136b和136c的上底端(以及其它内部列连接组件)。焊线138由金、铜、或其它合适的导电材料所形成。在一实例中，因为铜相较于金有更佳的导电性以及更低的成本，同时可允许焊线138以一减少的直径来形成，故而焊线138中至少一个子集合由铜所形成。焊线138可以一合适的金属镀膜来形成，如钯，以保护不受氧化及外界环境影响。使用焊线接合有益于帮助封装件100的堆栈功能，包括不需形成另一重新分布单元来提供电性路径，即可于封装件100内堆栈半导体组件102和104，所以可减少制造成本及时间。此外，使用焊线接合可以更容易地容纳特定形式的半导体组件，如焊线接合特殊设计以用来焊线接合的芯片。
参照图1A和图1B，封装件100包括一封装体140，封装体140设置邻接于重新分布单元118的上表面122。封装体140连接重新分布单元118，且实质上包覆或覆盖半导体组件102和104、焊线138、以及连接组件136b和136c(及其它内部列连接组件)以提供结构刚性并且保护不受外界环境影响。此外，封装体140延伸至重新分布单元118的周边，并且包覆或覆盖连接组件136a和136d(及其它外部列连接组件)，至少部分暴露出连接组件136a和136d的上底端，以堆栈另一封装件于封装件100之上。
封装体140由封胶材料所形成，并且包括一中央上表面142、一外围上表面144、以及侧向表面146和148，侧向表面146和148设置邻接于封胶体140的周边。在此实施例中，每一中央上表面142及外围上表面144实质上为平面，且有实质上和重新分布单元118的下表面120或上表面122平行的方向，然而在其它实施中，上表面142和144的形状与方向可以有所变更。参照图1A和图1B，封装体140于邻接于封装体140的一中央部分处有一较大的厚度，以实质上覆盖半导体组件102和104、焊线138、以及连接组件136b和136c，而封装体140于邻接于封装体140的外围部分处有减少的厚度，以至少部分暴露出连接组件136a和136d，而连接组件136a和136d的上底端实质上和外围上表面144对准或共平面。另外，封胶体140之中央厚度HP1，即垂直距离。此垂直距离位于封胶体140之中央上表面142和重新分布单元118的上表面122之间，此距离大于封胶体140的外围厚度HP2，此厚度HP2为一垂直距离。此垂直距离位于封胶体140的外围上表面144和重新分布单元118的上表面122之间，且实质上和各连接组件136a、136b、136c、或136d的高度HC相同。更特别的，外围厚度HP2不大于中央厚度HP1的9/10，例如约2/1到约9/10HP1，或者约2/3到约9/10HP1。在一实例中，中央厚度HP1可在约200微米到800微米的范围之间，如约250微米到750微米或者约300微米到700微米，而外围厚度HP2可在约100微米到700微米的范围之间，如约150微米到650微米或者约200微米到600微米。如图所示的连接组件136a和136d的上底端为实质上对准外围上表面144，连接组件136a和136d的上底端也可以向下凹或突出外围上表面144。
参照图1A和图1B，封胶体140的侧向表面146及148实质上为平面，且和重新分布单元118的下表面120或上表面122实质上有一直角方向，然而在其它实施中，侧向表面146和148的形状及方向可以有所变更。侧向表面146及148实质上分别对准重新分布单元118的侧向表面124及126或者是共平面，使得侧向表面146及148与侧向表面124及126相连接，侧向表面146及148定义出封装件100的周边。经由实行此表面对准操作可使得封胶体140有一侧向范围，此侧向范围实质上和重新分布单元118的侧向范围相符，虽然此侧向范围在邻接于封装件100的周边上会有一减少的厚度。对其他实施来说，图1A及图1B中所示的侧向表面124、126、146、及148可以有所变更的。
电性接触件设置邻接于封装体140的外围上表面144，包括电性接触件150a及150b，电性接触件150a及150b分别和连接组件136a及136d的上底端(及其它外部列连接组件)电性接触且由连接组件136a及136d的上底端向上延伸。电性接触件150a及150b当作预先焊接材料，用以堆栈另一封装件于封装件100之上，并且如同连接组件136a和136d，电性接触件150a和150b以一列的形式沿着实质上为矩形图案或实质上为方型图案的四边做延伸分布。在实施例中，电性接触件150a及150b被形成作为焊接凸块，且依照封装件100的扇出结构，电性接触件150a及150b横向分布于半导体组件102或104的周围外部，然而一般来说，电性接触件150a及150b可以是横向设置于周围的内部、周围的外部、或周围的内外部。
接着请参照图2A和图2B，图2A和图2B绘示出图1A和图1B的封装件100的部分放大剖面图，为简单表示，故省略相关细节。且其中，图2A绘示一连接组件136b的一特殊实施，而图2B绘示另一连接组件136b的特殊实施。虽然下列特征的描述参照连接组件136b，然而这些特征可以类似地应用于封装件100的其它连接组件。
首先请参照图2A，连接组件136b以固态伸长结构来做实施，且更特殊的是，例如是设置一导电柱或导电桩200于连接组件136b中，且实质上填充由封装体140所定义出的通孔。导电柱200的上底端包括一连接表面，此连接表面和焊线138为电性连接。在制造中，此连接表面可由经过导电柱200的上底端至一组表面终止操作(surface finishing operation)而形成，此组表面终止操作产生一组组层以增强连接至焊线138的电性连接可靠度。以表面终止层包括那些以金为基底的例子，例如化学金、无电镀镍/化学金、以及非电镀镍/非电镀钯/化学金。
接着参照图2B，连接组件136b以空心伸长结构来做实行，且更特殊的是，设置导电材料202于连接组件136b中，且部分填充由封装体140定义出的通孔。参照图2B，用以形成封装体140的封胶材料可填充部分的通孔，然而其它合适的填充材料也可以拿来使用。另外，通孔可以是至少部分为空心的。导电通道202的上底端有一较大的横向范围，且此横向范围被用来实行成为一连接垫204，此连接垫204包含一连接表面，此连接表面电性连接至焊线138。在制造中，此连接表面可以由通过接触垫204至一组类似于图2A所述的表面终止操作而形成。
图3绘示依照本发明一实施例的堆栈封装组装件300的剖面图，为简单表示，故省略相关细节。其中，图3绘示组装件300的特殊实施，此组装件300使用图1A到图2B的封装件100所形成。
如图3所示，组装件300包括一半导体封装件302，此半导体封装件302相当于一设置于封装件100上的上封装件，并且和相对于其下的封装件100作电性连接。在此实施例中，封装件302以一球栅矩阵排列(ball grid array，BGA)封装件来作实施，然而其它形式的封装件也可拿来作使用，包括一接点栅格矩阵排列(land gridarray，LGA)封装件、一四方扁平无外引脚(quad flat no-lead，QFN)封装件、一先进四方扁平无外引脚(advanced quad flat no-lead，aQFN)封装件、以及其它形式的球栅矩阵排列封装件，例如一窗型球栅矩阵排列封装件。虽然图3绘示二个堆栈封装件100和302，然而在其它实施中可包含有额外增加的封装件。封装件302的一特殊方面，可以用一和前述封装件100类似的形式执行，故而不于此再作描述。
参照图3，封装件302包括电性接触件，电性接触件包括电性接触件304a和304b，电性接触件304a和304b为封装件302提供了输入电性连接点和输出电性连接点，且从封装件302的一下表面向下延伸。在一实施例中，电性接触件304a和304b为焊接凸块，且电性接触件150a和150b亦为焊接凸块，电性接触件304a和304b以一列状分布，且沿着一实质上为矩形图案或为正方形图案的四边做延伸。在堆栈操作中，封装件302的电性接触件304a和304b为回流的，并且金属接线至封装件100的电性接触件150a和150b。其中，电性接触件304a和304b和电性接触件150a和150b的其中之一接合或融合，以提供封装件100和302间的电性路径。
图4A至图4H绘示依照本发明一实施例的一形成晶圆级半导体封装件的制造流程。为简单表示，下列制造操作参照图1A至图2B的封装件100作描述。然而，此制造操作可类似地执行以形成其它半导体封装件。
首先请参照图4A，提供一载具400，多对半导体组件以一堆栈结构设置邻接于载具400之上，包括半导体组件102和104。在此实施例中，半导体组件102和104为一背对背堆栈结构，半导体组件104的主动表面112面向载具400，而半导体组件102的主动表面106背向载具400。
成对堆栈的半导体组件可以一数组方式设置安排于载具400上，其中成对堆栈的半导体组件以一二维形式作设置安排，或用一带状方式，其中成对堆栈的半导体组件以一线性方式做连续设置安排。开始时，相对于邻近的半导体组件，半导体组件102或104被包含在一晶圆的一起始空间中，接着此晶圆经过切割工艺，将半导体组件102或104和其相邻的半导体组件分隔开。在此实施例中，相较于晶圆中的起始最近相邻空间，安排设置成对堆栈的半导体组件，以得到相对于彼此的一最大的最近相邻空间，如此有助于一完成封装件的扇出结构。为简单表示，下列制造操作主要对照半导体组件102和104及相关组件作描述，然而制造操作可以类似地执行于其它以平行方式或连续的成对堆栈半导体组件。
如图4B所示，施以一封胶材料402于载具400上，以覆盖或包覆半导体组件102和104，而半导体组件102和104的主动表面106和112依然是至少部分暴露。由于半导体组件104的主动表面112设置面向载具400，半导体组件104的周边实质上被封胶材料402所包覆，故而其主动表面112实质上不受封胶材料402包覆。经由设置封胶盘或其它封胶结构，并使封胶盘或其它封胶结构邻接于半导体组件102的主动表面106，半导体组件102的周边实质上被封胶材料402所包覆，半导体组件102的主动表面106实质上不受封胶材料402所包覆。
举例来说，封胶材料402包括一酚醛基树脂、一环氧基树脂、一硅基树脂、或其它适合的密封材料。合适的填充物可以包含在内，如粉末状二氧化硅(SiO2)。可以使用任意一种封胶技术来施加封胶材料402，例如压缩封胶、射出成型封胶、或转换封胶。一旦施以，封胶材料402即硬化或固化，例如降低温度以使封胶材料402的熔点下降，因而形成封胶结构404。参照图4B，一完成的封胶结构404包括一前表面408，前表面408和半导体组件102的主动表面106为实质上地对准或共平面，且一和前表面408相对的背表面410和半导体组件104的主动表面112为实质上地对准或共平面。以另一方式说明，封胶结构404的厚度和堆栈的半导体组件102和104的垂直范围总和实质上为相同。封胶结构404沿着被覆盖的半导体组件102和104，封胶结构404可以被视为是一重新组合晶圆。
接着请参照图4C，数个通孔形成于封胶结构404之中，包括通孔406a、406b、406c、及406d，其以一外部列和一内部列的形式分布，且环绕于半导体组件102和104周围，每一列皆沿着实质上为矩形图案或为正方形图案的四边作延伸。可以用任意一种方法形成通孔406a、406b、406c、及406d，例如化学蚀刻、激光钻孔、或机械钻孔以形成开口。举例来说，激光钻孔可以使用一绿光激光、一红外光激光、一固态激光、或一CO2激光来作实行，其应用为一脉冲形式或连续波形式的一激光束。
在此实施例中，每一通孔406a、406b、406c、及406d有一侧向边界，其形状为一圆柱状，包括一实质上的圆剖面。然而，一般来说，406a、406b、406c、及406d的形状可以是任意一种形状，例如另一形式的圆柱状，例如一椭圆柱状、一方形柱状、或一矩形柱状、或一非柱状，例如一圆锥、一漏斗状、或另一锥状。通孔406a，406b，406c，及406d的侧向边界也可以是曲线或粗糙纹理。
依然参照图4C，每一通孔406a、406b、406c、及406d通过封胶结构404实质地全部厚度作垂直延伸，即实质上延伸一半导体组件102和104的主动表面106和112之间的垂直距离。然而，在其它实施方式中，通孔406a、406b、406c、及406d的垂直延伸可以有所改变。在激光钻孔的例子中，适当地选择和控制激光的操作参数，可控制通孔406a、406b、406c、及406d的尺寸大小和形状。
接着，施加一导电材料418于通孔406a、406b、406c、及406d中，以至少部分填充通孔406a、406b、406c、及406d，从而形成图4D中所示的连接组件136a、136b、136c、及136d。导电材料418包括金属、金属合金、金属或金属合金分散于其中的材料、或其它合适的导电材料。举例来说，导电材料418可以包括金属，例如是铜，一焊接材料，例如是任意一种熔点位于约90℃到450℃范围之间的易熔金属合金，或者一导电附着物或糊状物，例如是任意一种树脂，此树脂具有导电填充物散布于其中。合适的焊接凸块例子包括锡铅合金、铜锌合金、铜银合金、锡银铜合金、含铋合金、含铟合金、及含锑合金，以及合适的附着物例子包括环氧基树脂及具有银填充物或碳填充物的硅基树脂。可以任意一种方式施加导电材料418，例如无电电镀沉积、电镀沉积、或经由使用一分配器施加导电材料418。
依然参照图4D，每一完成的连接组件136a、136b、136c、及136d包括一底端和一相对的底端，连接组件136a、136b、136c、及136d的底端和封胶结构404(且和半导体组件102的主动表面106)之前表面408为实质上地对准或共平面，连接组件136a、136b、136c、及136d的相对底端和封胶结构404(且和半导体组件104的主动表面112)的背表面410为实质上地对准或共平面。以另一方式说明，每一连接组件136a、136b、136c、及136d的高度HC和封胶结构404的厚度实质上相同。然而，在其它实施中，连接组件136a、136b、136c、及136d的垂直范围以及其与表面408和410的对准可以有所变更。
接着形成一组重新分布层，此组重新分布层邻接于封胶结构404之前表面408以及半导体组件102的主动表面106，因此形成图4E中的重新分布单元118。重新分布单元118包括一对介电层128和130、以及导电层132，至少部分的导电层132被夹于介电层128及130之间形成三明治结构。使用任意一种镀膜技术来施加一介电材料以形成每一介电层128和130，例如印刷、旋涂、或喷雾，接着图案化，以形成合适大小的尺寸及位置上对准的开口。使用任意一种技术以类似地施加一导电材料，例如化学气相沉积、无电电镀沉积、电镀沉积、印刷、旋涂、喷雾、溅镀、或真空沉积，接着图案化以形成导电层132。介电层128和130以及导电层132的图案化可以任意一种方法实行，例如微影工艺、化学蚀刻、激光钻孔、或机械钻孔。当形成重新分布单元118后，接着形成电性连接件12a，132b，132c，及132d，例如是施加一焊接材料并且回流及固化，使焊接材料形成焊接凸块，并且容纳于由介电层130定义出的开口中。
接着，沿着不同被覆盖组件的封胶结构404自载具400上分隔开，并且再转换至一直立方向，如图4F所示。半导体组件104接着通过焊线138，焊线接合至连接组件136b和136c(以及其它内部列连接组件)。可如前述一样实行或连接一组表面终止操作，焊线接合可增强电性连接件的可靠性。如前所述，焊线接合的使用提供了电性路径可允许半导体组件102和104的堆栈，而不需去形成另一重新分布单元以邻接至封胶结构404的背表面410以及半导体组件104的主动表面112。
如图4F和图4G所示，接着，选择性地施加封胶材料412于一封胶结构404之中央部分，以实质上覆盖或包覆半导体组件104的主动表面112、焊线138、以及连接组件136b和136c的上底端(以及其它内部列连接组件)。对照于图4B，封胶材料412和前述的封胶材料402可以是相同的或不同的，且可以任意一封胶技术施加，例如压缩封胶、射出成型封胶、或转换封胶。一旦施加，封胶材料412即硬化或固化，例如降低温度以使封胶材料412的熔点下降，而形成封胶体140。
参照图4G，位于邻接于封装体140边缘的地方，封装体140有一减少的厚度，封装体140邻接于连接组件136a和136d上底端之处为暴露的。封装体140亦可经由施加封胶材料412来形成，以得到一实质上均匀的厚度，之后接续一厚度缩减操作，例如化学蚀刻、激光钻孔、机械切割、钻孔、布线、或研磨、或其它移除技术以产生不同的厚度外型。
接着，如图4H所示，形成电性连接件150a和150b，且电性连接件150a和150b设置邻接于连接组件136a和136d的上底端，例如施加一焊接材料并且回流和固化，使焊接材料形成焊接凸块，从而形成封装件100。依照此特殊实施，执行一列的切割操作将封装件100分隔为相邻的封装件。
本发明已参照较佳实施例揭露如上，然其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰。此外，在不脱本发明的范围和精神下，为适应一特殊环境可针对材料、事件组成、方法、或工艺上做更多的修改。所有的修改皆在本专利范围所界定的范围内。更特别的，于此所揭露的方法参照一特殊的操作，在不脱离本发明的教导下，该些操作可以被合并、分开、或重新排列组合以形成一等同的方法。除了于此特别指出，该些组合与操作并非用以限定本发明。本发明的保护范围当视权利要求书所界定者为准。

Claims (20)

1.一种堆栈封装组装件，包括：
一第一半导体封装件包括：
一重新分布单元，包括一上表面；
一组堆栈半导体组件，包括：
(a)一第一半导体组件，设置邻接于该重新分布单元，该第一半导体组件包括一第一主动表面，该第一主动表面面对该重新分布单元的该上表面：以及
(b)一第二半导体组件，设置邻接于该第一半导体组件，该第二半导体组件包括一第二主动表面，该第二主动表面背向该第一主动表面；
一组连接组件，设置邻接于该组堆栈半导体组件的一周围，且各该组连接组件皆由该重新分布单元的该上表面向上延伸，该组连接组件包括：
(a)一第一连接组件，包括一第一上底端；及
(b)一第二连接组件，包括一第二上底端，该第二上底端焊线接合至该第二半导体组件的该第二主动表面；以及
一封装体，设置邻接于该重新分布单元的该上表面，该封装体包覆该组堆栈半导体组件及该组连接组件，该封装体包括一中央上表面及一外围上表面，该中央上表面位于该第二半导体组件的该第二主动表面上，该第一连接组件的该第一上底端暴露邻接于该封装体的该外围上表面。
2.如权利要求1所述的该堆栈封装组装件，其中该第二半导体组件的该第二主动表面实质上对准至少与该第一连接组件的该第一上底端及该第二连接组件的该第二上底端其中之一对准。
3.如权利要求2所述的该堆栈封装组装件，其中该第二半导体组件的该第二主动表面实质上对准该封装体的该外围上表面。
4.如权利要求3所述的该堆栈封装组装件，其中该第一连接组件的该第一上底端实质上对准该封装体的该外围上表面。
5.如权利要求1所述的该堆栈封装组装件，其中该封装体有一中央厚度HP1和该中央上表面相对应，以及一外围厚度HP2和外围上表面相对应，且该第一中央厚度HP1大于该外围厚度HP2。
6.如权利要求5所述的该堆栈封装组装件，其中该外围厚度HP2介于1/2该中央厚度HP1到9/10该中央厚度HP1的范围之间。
7.如权利要求5所述的该堆栈封装组装件，其中该第一连接组件及该第二连接组件其中的至少一者有一高度HC，且该高度HC实质上等同于该外围厚度HP2。
8.如权利要求1所述的该堆栈封装组装件，其中该第一连接组件及该第二连接组件其中的至少一者对应至一固体连续延伸结构。
9.如权利要求1所述的该堆栈封装组装件，其中该第一连接组件及该第二连接组件其中的至少一者对应至一中空延伸的结构。
10.如权利要求9所述的该堆栈封装组装件，其中该第二连接组件的该第二上底端对应至一接触垫，该接触垫焊线接合至该第二半导体组件的该第二主动表面。
11.如权利要求1所述的该堆栈封装组装件，其中该重新分布单元包括数个侧向表面，与该重新分布单元的一周围相邻，该封装体包括数个侧向表面与该封装体的一周围相邻，该封装体的该些侧向表面实质上分别对准该重新分布单元的该些侧向表面。
12.如权利要求1所述的该堆栈封装组装件，更包括：
一第二半导体封装件设置邻接于该第一半导体封装件的该封装体，该第二半导体封装件电性连接于该第一连接组件的该第一上底端。
13.如权利要求12所述的该堆栈封装组装件，其中该第二半导体封装件经由一组焊接凸块电性连接至该第一连接组件的该第一上底端。
14.一制造方法，包括：
提供一第一半导体组件及一第二半导体组件，该第一半导体组件包括一第一主动表面，该第二半导体组件包括一第二主动表面；
堆栈该第一半导体组件及该第二半导体组件，使得该第一主动表面及该第二主动表面彼此为背向；
施加一第一封胶材料以形成一封胶结构，覆盖该第一半导体组件的边缘及该第二半导体组件的边缘，该封胶结构包括一前表面及一相对的背表面，该第一半导体组件的该第一主动表面至少部分暴露邻接于该封胶结构的该前表面，该第二半导体组件的该第二主动表面至少部分暴露邻接于该封胶结构的该背表面；
形成一组通孔，从该组通孔于该封胶结构的该前表面延伸至该封胶结构的该背表面，并围绕该第一半导体组件及该第二半导体组件；
施加一导电材料至该组通孔，以形成一组连接组件；
形成一重新分布单元邻接该第一半导体组件的该第一主动表面及该封胶结构的该前表面；
通过一组焊线，电性连接该第二半导体组件的该第二主动表面至该组连接组件中的至少其中之一；以及
施加一第二封胶材料，该第二封胶材料邻接于该第二半导体组件的该第二主动表面及该封胶结构的该背表面，以形成一封装体，该封装体包括一中央部分及一外围部分，该中央部分有一中央厚度HP1，并覆盖该第二半导体组件的该第二主动表面及该组焊线，该外围部分有一外围厚度HP2，以使该组连接组件中的至少一个连接组件的一底端部分暴露。
15.如权利要求14所述的该制造方法，其中使用激光钻孔以形成该组通孔。
16.如权利要求14所述的该制造方法，其中经由形成该组通孔的步骤来形成一第一组通孔及一第二组通孔，该第一组通孔分布于一外部列上，该外部列环绕该第一半导体组件及该第二半导体组件，该第二组通孔分布于一内部列上，该内部列环绕该第一半导体组件及该第二半导体组件。
17.如权利要求14所述的该制造方法，其中至少使用一化学电镀及一电解电镀其中至少一者，以施加该导电材料。
18.如权利要求14所述的该制造方法，其中提供一焊料及一导电黏着剂其中至少一者，以施加该导电材料。
19.如权利要求14所述的该制造方法，其中中央厚度HP1大于外围厚度HP2。
20.如权利要求14所述的该制造方法，其中外围厚度HP2介于2/3中央厚度HP1到9/10中央厚度HP1的范围之间。
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