FR3085576B1 - Couvercle pour boitier de circuit integre - Google Patents
Couvercle pour boitier de circuit integre Download PDFInfo
- Publication number
- FR3085576B1 FR3085576B1 FR1857919A FR1857919A FR3085576B1 FR 3085576 B1 FR3085576 B1 FR 3085576B1 FR 1857919 A FR1857919 A FR 1857919A FR 1857919 A FR1857919 A FR 1857919A FR 3085576 B1 FR3085576 B1 FR 3085576B1
- Authority
- FR
- France
- Prior art keywords
- cover
- integrated circuit
- circuit box
- openings
- peripheral
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000002093 peripheral effect Effects 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
- H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L21/603—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the application of pressure, e.g. thermo-compression bonding
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Casings For Electric Apparatus (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
La présente description concerne un couvercle pour boîtier de circuit intégré, comprenant des ouvertures (150) traversantes périphériques.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1857919A FR3085576B1 (fr) | 2018-09-04 | 2018-09-04 | Couvercle pour boitier de circuit integre |
US16/551,241 US11101188B2 (en) | 2018-09-04 | 2019-08-26 | Cap for package of integrated circuit |
US17/378,398 US11923256B2 (en) | 2018-09-04 | 2021-07-16 | Cap for package of integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1857919A FR3085576B1 (fr) | 2018-09-04 | 2018-09-04 | Couvercle pour boitier de circuit integre |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3085576A1 FR3085576A1 (fr) | 2020-03-06 |
FR3085576B1 true FR3085576B1 (fr) | 2021-07-16 |
Family
ID=65201263
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1857919A Active FR3085576B1 (fr) | 2018-09-04 | 2018-09-04 | Couvercle pour boitier de circuit integre |
Country Status (2)
Country | Link |
---|---|
US (2) | US11101188B2 (fr) |
FR (1) | FR3085576B1 (fr) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11682602B2 (en) | 2021-02-04 | 2023-06-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of manufacture |
CN114156238A (zh) * | 2021-12-22 | 2022-03-08 | 苏州科阳半导体有限公司 | 一种半导体芯片的封装结构及封装方法 |
CN115923309B (zh) * | 2023-01-13 | 2024-06-04 | 江西省瑞烜新材料有限公司 | 一种环保型新材料覆铜板生产装置及其生产方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4166665A (en) * | 1976-12-27 | 1979-09-04 | Cutchaw John M | Liquid cooled connector for large scale integrated circuit packages |
US5473512A (en) * | 1993-12-16 | 1995-12-05 | At&T Corp. | Electronic device package having electronic device boonded, at a localized region thereof, to circuit board |
US5739584A (en) * | 1995-06-07 | 1998-04-14 | Lsi Logic Corporation | Multiple pin die package |
US6000120A (en) * | 1998-04-16 | 1999-12-14 | Motorola, Inc. | Method of making coaxial transmission lines on a printed circuit board |
TWI397978B (zh) * | 2007-12-12 | 2013-06-01 | Ind Tech Res Inst | 晶片結構及其製程與覆晶封裝結構及其製程 |
US8278746B2 (en) * | 2010-04-02 | 2012-10-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages including connecting elements |
CN105244314A (zh) * | 2015-10-08 | 2016-01-13 | 上海和辉光电有限公司 | 一种显示器件及其制备方法 |
-
2018
- 2018-09-04 FR FR1857919A patent/FR3085576B1/fr active Active
-
2019
- 2019-08-26 US US16/551,241 patent/US11101188B2/en active Active
-
2021
- 2021-07-16 US US17/378,398 patent/US11923256B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20210343609A1 (en) | 2021-11-04 |
US11101188B2 (en) | 2021-08-24 |
US20200075436A1 (en) | 2020-03-05 |
FR3085576A1 (fr) | 2020-03-06 |
US11923256B2 (en) | 2024-03-05 |
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Legal Events
Date | Code | Title | Description |
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PLFP | Fee payment |
Year of fee payment: 2 |
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PLSC | Publication of the preliminary search report |
Effective date: 20200306 |
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PLFP | Fee payment |
Year of fee payment: 3 |
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PLFP | Fee payment |
Year of fee payment: 4 |
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PLFP | Fee payment |
Year of fee payment: 5 |
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PLFP | Fee payment |
Year of fee payment: 6 |
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PLFP | Fee payment |
Year of fee payment: 7 |