TWI517341B - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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Publication number
TWI517341B
TWI517341B TW102116654A TW102116654A TWI517341B TW I517341 B TWI517341 B TW I517341B TW 102116654 A TW102116654 A TW 102116654A TW 102116654 A TW102116654 A TW 102116654A TW I517341 B TWI517341 B TW I517341B
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Taiwan
Prior art keywords
semiconductor
opening
carrier
semiconductor package
conductive
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TW102116654A
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English (en)
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TW201444047A (zh
Inventor
陳彥亨
林畯棠
廖宴逸
劉鴻汶
紀傑元
許習彰
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW102116654A priority Critical patent/TWI517341B/zh
Priority to CN201310183339.5A priority patent/CN104143537A/zh
Priority to US14/013,420 priority patent/US9177859B2/en
Publication of TW201444047A publication Critical patent/TW201444047A/zh
Priority to US14/873,445 priority patent/US9397081B2/en
Application granted granted Critical
Publication of TWI517341B publication Critical patent/TWI517341B/zh

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Description

半導體封裝件及其製法
本發明係有關一種半導體封裝件，尤指一種可防止於固晶時半導體元件偏移的嵌埋半導體元件之半導體封裝件及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足半導體封裝件微型化(miniaturization)的封裝需求，係發展出晶圓級封裝(Wafer Level Packaging,WLP)的技術。
如第1A至1D圖，係為習知晶圓級半導體封裝件1之製法之剖面示意圖。
如第1A圖所示，形成一熱化離型膠層(thermal release tape)11於一承載件10上。
接著，置放複數半導體元件12於該熱化離型膠層11上，該些半導體元件12具有相對之主動面12a與非主動面12b，各該主動面12a上均具有複數電極墊120，且各該主動面12a黏著於該熱化離型膠層11上。
如第1B圖所示，以模壓(molding)方式形成一封裝 膠體13於該熱化離型膠層11上，以包覆該半導體元件12。
如第1C圖所示，進行烘烤製程以硬化該封裝膠體13，而同時該熱化離型膠層11因受熱後會失去黏性，故可一併移除該熱化離型膠層11與該承載件10，以外露該半導體元件12之主動面12a。
如第1D圖所示，進行線路重佈層(Redistribution layer,RDL)製程，係形成一線路重佈結構14於該封裝膠體13與該半導體元件12之主動面12a上，令該線路重佈結構14電性連接該半導體元件12之電極墊120。
接著，形成一絕緣保護層15於該線路重佈結構14上，且該絕緣保護層15外露該線路重佈結構14之部分表面，以供結合如銲球之導電元件16。
惟，習知半導體封裝件1之製法中，該熱化離型膠層11具有撓性，且其熱膨脹係數(Coefficient of thermal expansion,CTE)與該封裝膠體13注入封裝用之模具時之膠體流動所產生之側推力，將一同影響該半導體晶片12固定之精度，亦即容易使半導體元件12產生偏移，致使該半導體元件12未置於該熱化離型膠層11之置放區B上，如第1D’圖所示，且當該承載件10移除後會造成該封裝膠體13翹曲(warpage)過大。故而，該線路重佈結構14與該半導體元件12之電極墊120間的對位將產生偏移，當該承載件10之尺寸越大時，各該半導體元件12間之位置公差亦隨之加大，而當偏移公差過大時，將使該線路重佈結構14無法與該電極墊120連接，亦即對該線路重佈結構 14與該半導體元件12間之電性連接造成極大影響，因而造成良率過低及產品可靠度不佳等問題。
再者，習知製法中，因需使用該熱化離型膠層11，故無法降低製造成本。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種半導體封裝件，係包括：承載件，係具有相對之第一表面與第二表面，且形成有連通至該第一表面並具有底部之開口；複數導電跡線，係形成於該開口之底部、該開口之側壁與該承載件之第一表面上；第一半導體元件，係設於該開口中，該第一半導體元件具有相對之第一主動面與第一非主動面，該主動面上具有複數第一電極墊，且該第一主動面係朝向該開口之底部，以令該些第一電極墊電性連接該導電跡線；第二半導體元件，係設於該第一半導體元件上，該第二半導體元件具有相對之第二主動面與第二非主動面，該第二主動面上具有複數第二電極墊，且該第二非主動面係結合至該第一半導體元件之第一非主動面上，以令該第二主動面及第二電極墊外露於該開口；以及線路重佈結構，係形成於該承載件之第一表面與該第二半導體元件之第二主動面上，而藉該線路重佈結構電性連接該導電跡線及該第二主動面上之第二電極墊。
本發明復提供一種半導體封裝件之製法，係包括：提 供一具有相對之第一表面與第二表面之承載件；形成連通至該承載件之第一表面之開口，該開口具有底部；形成複數導電跡線於該承載件之第一表面、該開口之底部與該開口之側壁上；設置第一半導體元件於該開口中，該第一半導體元件具有相對之第一主動面與第一非主動面，該主動面上具有複數第一電極墊，且該第一主動面係朝向該開口之底部，並令該些第一電極墊電性連接該導電跡線；設置第二半導體元件於該第一半導體元件上，該第二半導體元件具有相對之第二主動面與第二非主動面，該第二主動面上具有複數第二電極墊，且該第二非主動面係接合至該第一半導體元件之第一非主動面上，而令該第二主動面及第二電極墊外露於該開口；以及形成線路重佈結構於該承載件之第一表面與該第二半導體元件之第二主動面上，以藉該線路重佈結構電性連接該導電跡線及該些第二電極墊。
前述之半導體封裝件及其製法中，該承載件係為半導體基板或玻璃基板。
前述之半導體封裝件及其製法中，該開口具有連通之第一容置空間與第二容置空間，該第一容置空間係由該底部及與該底部鄰接的開口之側壁所構成，以收納該第一半導體元件，例如，該第一容置空間之容積小於或等於該第二容置空間之容積。
前述之半導體封裝件及其製法中，該開口之側壁係呈階梯狀。
前述之半導體封裝件及其製法中，該第一半導體元件 之寬度小於或等於該第二半導體元件之寬度。
前述之半導體封裝件及其製法中，該承載件復具有導電孔部，係由該承載件之第二表面延伸至該開口之底部，以令該導電孔部電性連接該第一半導體元件。例如，形成該導電孔部之製程係包括：形成通孔於該開口之底部上；以及於形成該導電跡線時，形成該導電孔部於該通孔中。
依上述，該第一半導體元件係以導電元件電性連接該導電孔部。例如，薄化該承載件之第二表面，使該些導電孔部外露於該承載件之第二表面；或者，該通孔係連通該承載件之第二表面與該開口之底部，使該些導電孔部外露於該承載件之第二表面。
另外，依上述，本發明復包括結合電子元件於該承載件之第二表面上，且該電子元件電性連接該導電孔部。
由上可知，本發明之半導體封裝件及其製法，係藉由將該第一與第二半導體元件嵌埋於該承載件之開口中，以令該第一與第二半導體元件定位於該開口中，故相較於習知技術，本發明不需使用習知熱化離型膠層，且不需進行模壓製程，因而能避免該第一與第二半導體元件產生偏移。因此，於量產時，當該承載件之尺寸越大時，該第二半導體元件間之位置公差不會隨之加大，故於製作該線路重佈結構時，其與該第二半導體元件間之電性連接能有效對接，因而能提高良率及提升產品可靠度。
再者，本發明之承載件係為硬質材，亦即未經加熱即已硬化，故相較於習知技術，本發明不需進行加熱製程， 因而能避免該承載件翹曲過大。
另外，相較於習知熱化離型膠層，該承載件係為半導體基板或玻璃基板，因而極易製作，故能大幅降低製造成本。
1,2,3‧‧‧半導體封裝件
10‧‧‧承載件
11‧‧‧熱化離型膠層
12‧‧‧半導體元件
12a‧‧‧主動面
12b‧‧‧非主動面
120‧‧‧電極墊
13‧‧‧封裝膠體
14,24‧‧‧線路重佈結構
15,25‧‧‧絕緣保護層
16,26,31‧‧‧導電元件
20‧‧‧承載件
20a‧‧‧第一表面
20b,20b’‧‧‧第二表面
200‧‧‧開口
200a‧‧‧底部
200b‧‧‧側壁
201‧‧‧第一容置空間
202‧‧‧第二容置空間
21‧‧‧第一半導體元件
21a‧‧‧第一主動面
21b‧‧‧第一非主動面
210‧‧‧第一電極墊
22‧‧‧第二半導體元件
22a‧‧‧第二主動面
22b‧‧‧第二非主動面
220‧‧‧第二電極墊
23‧‧‧導電跡線
240‧‧‧介電層
241‧‧‧線路層
242‧‧‧導電盲孔
243‧‧‧電性接觸墊
250‧‧‧開孔
27‧‧‧黏著層
30‧‧‧導電孔部
300,300’‧‧‧通孔
32‧‧‧電子元件
B‧‧‧置放區
D,R,T,W‧‧‧寬度
S‧‧‧切割路徑
第1A至1D圖係為習知半導體封裝件之製法的剖視示意圖；其中，第1D’圖係為第1C圖之上視圖；第2A至2F圖係為本發明之半導體封裝件之製法之第一實施例的剖視示意圖；以及第3A至3F圖係為本發明之半導體封裝件之製法之第二實施例的剖視示意圖；其中，第3A’及3B’圖係為第3A及3B圖之另一實施例。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述 之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2F圖係為本發明之半導體封裝件2之製法之第一實施例的剖面示意圖。本發明之封裝件製程係可採用整版面(Panel)製程或晶圓級封裝(Wafer Level Package)製程。
如第2A圖所示，提供一具有相對之第一表面20a與第二表面20b之承載件20，且形成複數連通至該承載件20之第一表面20a之開口200，各該開口200具有一底部200a。
於本實施例中，該承載件20係為如晶圓、矽板之半導體基板或玻璃基板，其中，該晶圓之材質可為碳化矽(SiC)、非晶矽(amorphos Si)、砷化鎵(GaAs)、氧化鋁(Al2O3)。
再者，該開口200具有連通之一第一容置空間201與一第二容置空間202，且該第一容置空間201係由該底部200a及與該底部200a鄰接的側壁200b所構成。
又，該開口200之側壁200b係呈階梯狀，例如，第2A圖所示之垂直式階梯或呈非垂直狀階梯(圖未示)，且該第一容置空間201之容積(或寬度W)小於該第二容置空間202之容積(或寬度T)。因此，本發明可利用黃光製程及蝕刻(乾式或溼式)製作階梯狀之開口200。
另外，於其它實施例中，該第一容置空間201之容積(或寬度W)可等於該第二容置空間202之容積(或寬度 T)，致使該開口200之側壁200b係呈垂直平面。
如第2B圖所示，形成複數導電跡線23於該承載件20之第一表面20a上，並由該開口200之底部200a經該開口200之側壁200b延伸至該承載件20之第一表面20a上。
於本實施例中，係利用黃光製程製作圖案化導電跡線23。
如第2C圖所示，設置一第一半導體元件21於該開口200中，亦即該第一容置空間201收納該第一半導體元件21。
於本實施例中，該第一半導體元件21具有相對之一第一主動面21a與一第一非主動面21b，該第一主動面21a上具有複數第一電極墊210，且該第一主動面21a係朝向該開口200之底部200a，且令該些第一電極墊210接觸且電性連接該開口200之底部200a上之導電跡線23。
如第2D圖所示，藉由黏著層27以將一第二半導體元件22堆疊於該第一半導體元件21上，該第二半導體元件22具有相對之一第二主動面22a與一第二非主動面22b，該第二主動面22a上具有複數第二電極墊220，且該第二非主動面22b係接合至該第一半導體元件21之第一非主動面21b上，而令該第二主動面22a及第二電極墊220係與該第一表面20a同側並外露於該開口200。
於本實施例中，該第二容置空間202係收納該第二半導體元件22。
再者，該第一半導體元件21之平面尺寸(即水平面方 向之尺寸，如寬度D)係小於或等於該第二半導體元件22之平面尺寸(即寬度R)。
又，於其它實施例中，該第一半導體元件21之平面尺寸(即水平面方向之尺寸，如寬度D)可等於該第二半導體元件22之平面尺寸(即寬度R)。
另外，於其它實施例中，該第二半導體元件22之數量可依需求設計為複數個。
如第2E圖所示，進行線路重佈層(RDL)製程，形成一線路重佈結構24於該承載件20之第一表面20a與該第二半導體元件22之第二主動面22a上，以藉該線路重佈結構24電性連接該導電跡線23及該些第二電極墊220。
於本實施例中，該線路重佈結構24係包含複數介電層240、形成於各該介電層240上之複數線路層241、及形成於該介電層240中之複數導電盲孔242，且該線路層241藉由該些導電盲孔242電性連接該承載件20之第一表面20a上之導電跡線23及該第二半導體元件22之第二電極墊220。
再者，最外層之該線路層241具有複數電性接觸墊243，且形成一絕緣保護層25於該線路重佈結構24上，該絕緣保護層25具有外露該些電性接觸墊243之複數開孔250，以於各該開孔250處形成如銲球之導電元件26，俾供電性連接該些電性接觸墊243與外部元件(圖未示)。
又，該第二半導體元件22可藉由該線路層241與導電盲孔242電性連接該導電跡線23。
如第2F圖所示，進行切單製程，係沿如第2E圖所示之切割路徑S進行切割，以製作複數個半導體封裝件2。
本發明之製法中，係藉由將該第一與第二半導體元件21,22嵌埋於該承載件20之開口200中，以令該第一與第二半導體元件21,22定位於該開口200中，故本發明不需使用習知熱化離型膠層，且不需進行模壓製程，因而可避免熱膨脹係數及封裝膠體所產生之側推力等之影響，致能避免該第一與第二半導體元件21,22產生偏移。因此，當該承載件20之尺寸越大時，各該第二半導體元件22間之位置公差不會隨之加大，故可精確控制該第二半導體元件22之精度，以於製作該線路重佈結構24時，該導電盲孔242與該第二半導體元件22間之電性連接能有效對接，而能提高良率及提升產品可靠度。
再者，本發明之承載件20係為硬質材，亦即未經加熱即已硬化，故本發明之製法不需進行加熱製程，因而能避免該承載件20翹曲(warpage)過大。
另外，於本發明之製法中，該承載件20係為半導體基板或玻璃基板，因而極易製作，故無需使用習知特製之熱化離型膠層，俾能大幅降低製造成本。
第3A至3F圖係為本發明之半導體封裝件3之製法之第二實施例的剖面示意圖。本實施例與第一實施例之差異在於增設導電孔部30，其它結構與製程大致相同。
如第3A圖所示，形成該開口200後，以雷射鑽孔方式形成通孔300於該開口200之底部200a上。
於本實施例中，該通孔300未延伸至該承載件20之第二表面20b，但於其它實施例中，如第3A’圖所示，該通孔300’可連通該承載件20之第二表面20b與開口200之底部200a。
如第3B圖所示，接續第3A圖之製程，係於形成該導電跡線23時，形成如銅之金屬材質之導電孔部30於該通孔300中。
於本實施例中，因該通孔300之深度不深，故可採用一次圖案化之方式，亦即同時圖案化電鍍形成該導電跡線23與導電孔部30。
再者，有關電鍍之方式繁多，例如導電層(seed layer)與光阻之應用，並無特別限制。
又，當該通孔300’之深度較深時，如第3A’及3B’圖所示，可採用兩次圖案化之方式，亦即先進行第一次圖案化製程，以形成該導電孔部30，待移除第一次圖案化製程之耗材，如導電層(圖略)與光阻(圖略)，再形成第二次圖案化製程之耗材，以形成該導電跡線23。
另外，有關圖案化製程之方式繁多，例如沉積、蝕刻等方式，並不限於上述電鍍方式。
如第3C圖所示，設置第一半導體元件21與第二半導體元件22，且令該導電孔部30電性連接該第一半導體元件21之第一電極墊210。
於本實施例中，該第一半導體元件21之部分第一電極墊210係以如金屬塊之導電元件31電性連接該導電孔部 30，且該第一半導體元件21之部分第一電極墊210係電性連接該導電跡線23。
如第3D圖所示，形成該線路重佈結構24、絕緣保護層25及導電元件26。
如第3E圖所示，薄化該承載件20之第二表面20b’，使該些導電孔部30外露於該承載件20之第二表面20b’。
若接續第3A’圖所示之製程，因該通孔300’連通該承載件20之第二表面20b，使該些導電孔部30於成形時已外露於該承載件20之第二表面20b，故薄化製程可視需求而定。
如第3F圖所示，結合複數電子元件32於該承載件20之第二表面20b上，且該電子元件32電性連接該導電孔部30之外露表面。之後，進行切單製程，係沿如第3E圖所示之切割路徑S進行切割，以製作複數個半導體封裝件3。亦可先切割，再結合該電子元件32。
於本實施例中，該電子元件32係例如封裝件、晶片、被動元件等，並無特別限制。
再者，該電子元件32係以底膠固定於該承載件20之第二表面20b’上，亦可使用模壓製程進行固定。
另外，有關該導電孔部30之製程步驟不限於上述，例如，可於第2E圖之製程後，再形成該通孔300與該導電孔部30。因此，該導電孔部30之製作可依需求而定。
本發明復提供一種半導體封裝件2,3，係包括：一承載件20、複數導電跡線23、一第一半導體元件21、一第二 半導體元件22以及一線路重佈結構24。
所述之承載件20係為半導體基板或玻璃基板，其具有相對之第一表面20a與第二表面20b,20b’，且形成有連通至該第一表面20a並具有底部200a之開口200。
所述之導電跡線23係形成於該開口200之底部200a、該開口200之側壁200b與該承載件20之第一表面20a上。
所述之第一半導體元件21係設於該開口200中，該第一半導體元件21具有相對之第一主動面21a與第一非主動面21b，該第一主動面21a上具有複數第一電極墊210，且該第一主動面21a係朝向該開口200之底部200a，以令該些第一電極墊210電性連接該導電跡線23。
所述之第二半導體元件22係設於該第一半導體元件21上，該第二半導體元件22具有相對之第二主動面22a與第二非主動面22b，該第二主動面22a上具有複數第二電極墊220，且該第二非主動面22b係接合至該第一半導體元件21之第一非主動面21b上，而令該第二主動面22a及第二電極墊220外露於該開口200。
所述之線路重佈結構24係形成於該承載件20之第一表面20a與該第二半導體元件22上，而藉該線路重佈結構24電性連接該導電跡線23及該些第二電極墊220。
於一實施例中，該開口200具有連通之第一容置空間201與第二容置空間202，且該第一容置空間201係由該底部200a及側壁200b所構成，以收納該第一半導體元件21，又該第一容置空間201之容積係小於或等於該第二容置空 間202之容積。
於一實施例中，該開口200之側壁200b係呈階梯狀。
於一實施例中，該第一半導體元件21之寬度D小於或等於該第二半導體元件22之寬度R。
於一實施例中，該承載件20復具有複數導電孔部30，係由該承載件20之第二表面20b’直線延伸至該開口200之底部200a，以令該導電孔部30藉由複數導電元件31電性連接該第一電極墊210。
所述之半導體封裝件3復包括一電子元件32，係結合於該承載件20之第二表面20b上且電性連接該導電孔部30。
綜上所述，本發明之半導體封裝件及其製法，主要藉由將該第一與第二半導體元件嵌埋於該承載件之開口中，使該第一與第二半導體元件定位於該開口中，故該第一與第二半導體元件不會偏位。因此，不論該承載件之尺寸大小，各該第二半導體元件間之位置公差均不會隨之變化，故可精確控制該第二半導體元件之精度，以於製作該重佈線路結構時，其與該第二半導體元件間之電性連接能有效對接，而能提高良率及提升產品可靠度。
再者，本發明之承載件係為硬質材，故能避免該承載件翹曲過大。
另外，於本發明之製法中，該承載件係為半導體基板或玻璃基板，因而極易製作，故能大幅降低製造成本。
上述實施例係用以例示性說明本發明之原理及其功 效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
20‧‧‧承載件
20a‧‧‧第一表面
20b‧‧‧第二表面
200‧‧‧開口
200a‧‧‧底部
201‧‧‧第一容置空間
21‧‧‧第一半導體元件
21a‧‧‧第一主動面
21b‧‧‧第一非主動面
210‧‧‧第一電極墊
23‧‧‧導電跡線

Claims (22)

  1. 一種半導體封裝件，係包括：承載件，係具有相對之第一表面與第二表面，且形成有連通至該第一表面並具有底部之開口；複數導電跡線，係形成於該開口之底部、該開口之側壁與該承載件之第一表面上；第一半導體元件，係設於該開口中，該第一半導體元件具有相對之第一主動面與第一非主動面，該主動面上具有複數第一電極墊，且該第一主動面係朝向該開口之底部，以令該些第一電極墊電性連接該導電跡線；第二半導體元件，係設於該第一半導體元件上，該第二半導體元件具有相對之第二主動面與第二非主動面，該第二主動面上具有複數第二電極墊，且該第二非主動面係結合至該第一半導體元件之第一非主動面上，以令該第二主動面及第二電極墊外露於該開口；以及線路重佈結構，係形成於該承載件之第一表面與該第二半導體元件之第二主動面上，而藉該線路重佈結構電性連接該導電跡線及該第二主動面上之第二電極墊。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該承載件係為半導體基板或玻璃基板。
  3. 如申請專利範圍第1項所述之半導體封裝件，其中， 該開口具有連通之第一容置空間與第二容置空間，該第一容置空間係由該底部及與該底部鄰接的開口之側壁所構成，以收納該第一半導體元件。
  4. 如申請專利範圍第3項所述之半導體封裝件，其中，該第一容置空間之容積係小於或等於該第二容置空間之容積。
  5. 如申請專利範圍第1項所述之半導體封裝件，其中，該開口之側壁係呈階梯狀。
  6. 如申請專利範圍第1項所述之半導體封裝件，其中，該第一半導體元件之寬度係小於或等於該第二半導體元件之寬度。
  7. 如申請專利範圍第1項所述之半導體封裝件，其中，該承載件復具有導電孔部，係由該承載件之第二表面延伸至該開口之底部，以令該導電孔部電性連接該第一半導體元件。
  8. 如申請專利範圍第7項所述之半導體封裝件，其中，該導電孔部電性連接該第一電極墊。
  9. 如申請專利範圍第7項所述之半導體封裝件，其中，該第一半導體元件係以導電元件電性連接該導電孔部。
  10. 如申請專利範圍第7項所述之半導體封裝件，復包括電子元件，係結合於該承載件之第二表面上且電性連接該導電孔部。
  11. 一種半導體封裝件之製法，係包括： 提供一具有相對之第一表面與第二表面之承載件；形成連通至該承載件之第一表面之開口，該開口具有底部；形成複數導電跡線於該承載件之第一表面、該開口之底部與該開口之側壁上；設置第一半導體元件於該開口中，該第一半導體元件具有相對之第一主動面與第一非主動面，該主動面上具有複數第一電極墊，且該第一主動面係朝向該開口之底部，並令該些第一電極墊電性連接該導電跡線；設置第二半導體元件於該第一半導體元件上，該第二半導體元件具有相對之第二主動面與第二非主動面，該第二主動面上具有複數第二電極墊，且該第二非主動面係接合至該第一半導體元件之第一非主動面上，而令該第二主動面及第二電極墊外露於該開口；以及形成線路重佈結構於該承載件之第一表面與該第二半導體元件之第二主動面上，以藉該線路重佈結構電性連接該導電跡線及該些第二電極墊。
  12. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該承載件係為半導體基板或玻璃基板。
  13. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該開口具有連通之第一容置空間與第二容置空 間，該第一容置空間係由該底部及與該底部鄰接的開口之側壁所構成，以收納該第一半導體元件。
  14. 如申請專利範圍第13項所述之半導體封裝件之製法，其中，該第一容置空間之容積係小於或等於該第二容置空間之容積。
  15. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該開口之側壁係呈階梯狀。
  16. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該第一半導體元件之寬度係小於或等於該第二半導體元件之寬度。
  17. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該承載件復具有導電孔部，係由該承載件之第二表面延伸至該開口之底部，以令該導電孔部電性連接該第一半導體元件。
  18. 如申請專利範圍第17項所述之半導體封裝件之製法，其中，形成該導電孔部之製程係包括：形成通孔於該開口之底部上；以及於形成該導電跡線時，形成該導電孔部於該通孔中。
  19. 如申請專利範圍第18項所述之半導體封裝件之製法，復包括薄化該承載件之第二表面，使該些導電孔部外露於該承載件之第二表面。
  20. 如申請專利範圍第18項所述之半導體封裝件之製法，其中，該通孔係連通該承載件之第二表面與該開口之 底部，使該些導電孔部外露於該承載件之第二表面。
  21. 如申請專利範圍第17項所述之半導體封裝件之製法，其中，該第一半導體元件係以導電元件電性連接該導電孔部。
  22. 如申請專利範圍第17項所述之半導體封裝件之製法，復包括結合電子元件於該承載件之第二表面上，且該電子元件電性連接該導電孔部。
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