1298195 九、發明說明： 【發明所屬之技術領域】 本發明係錢於-種堆“粒的封裝結構與其封料方法，特別是有 關於-種整合微機電(MEMS)與接觸式影像感測器(c〇nta⑴明❿ CIS)之堆疊相同晶粒騎裝結構與其封裝的方法。 【先前技術】 半導體製程的魏使得鱗_元件柯峨料體元射形成，例 如接觸式影像感測器(卿。相較於CCD影像感測树，CIS元件即使加 上其封裝結構，在體積與價格上仍具有其優點，耻郎影像制封裝產 品推及各式各樣的產品之中1而，在不A幅變更既有的產品設計的考量 下’如何增加影像感測封裝^件的設計彈性便成為CIS元件之廣泛應用的 重要因素之-。此外，當CIS耕應用於平價產品中時，如何降低CIS元 件的製程成本亦是重要的課題之一。 此外，將微機電(MEMS)元件與CIS元件整合成一封裝元件亦是現今微 型化封裝的重要課題之-，其巾需考量職機電元件動作較間，因此如 何製作低成本整合的封裝結構與方法是靜急需解決的課題之… 【發明内容】 有鑑於上述背景巾有關整合微機電元件與接赋影像感測器封裝設計 I 1298195 的彈性，於此提供一種堆叠晶片的封裝結構與其形成方法 形成Γ結構貫穿另—晶圓與晶粒的整合結構，可將堆叠晶圓上的= 一面傳遞至另—面’增加微機電元件與接觸式影像感測器封裝設計的彈性。 ^再者’欲输蝴&輪_蝴剛細縣，於此提 整合性堆“片的封裝結構與其形成方法，基板製程形成可貫 堆叠晶圓的結構’可以減少晶圓製程的複雜性並提高晶圓的良率。 虞述本务明之一實施例，提供一種晶圓級堆疊封裝的方法，一 基板具有複數個導電連接結淑•其上。兩《，每—純具有一主動 面與位於相反側的-背面’射每—晶圓包含複數個晶片彼此相鄰接及複 數個導電魏置轉’面±。圓，她㈣之兩背面互 相連接。移除部份兩晶關以形成複數個貫孔，其中每—貫孔位於任兩晶 片之間的-切割道上。填人—黏著層於每—個貫孔h接合基板與兩晶圓， 其中每-導電連接結構係位於其相對應之每—貫孔_著射，並暴露於 通離《板之該晶圓的該主動面。一導電線路層形成於遠離該基板之晶圓 的主動面上並接觸每-導電連接結構與遠離基板之晶圓的主動面上之導電 塾。-介電層形成於導電線路層之間且暴露出部分導電線路層。複數個導 電凸塊形成於介電層上並接觸暴露出的導電線路層。 根據上述，兩晶粒以各自的背面固定，每一晶粒的主動面上配置複數 個導電墊，其中一晶粒的主動面面對一基板，且兩晶粒的尺寸相同。複數 個導電連接結構，個別地固定於基板上與兩晶粒之邊緣，其中每一導電連 1298195 接結構從基板延伸至遠離基板的主動面上且每一導電連接結構暴露於遠離 • 基板的主動面上。一導電線路層位於遠離基板的主動面上並接觸每一導電 連接結構與达離基板的主動面上複數個導電墊。一介電結構位於等電線路 層上並暴露出部分導電線路層。 【實施方式】 本發明的一些實施例會詳細描述如下。然而，除了該詳細描述外，本 發明還可以廣泛地在其他的實施例施行。亦即，本^發明的範圍不受已提出 之實施例的限制，而應以本發明提出之申請專利範圍為準。其次，當本發 明之實施例圖示巾的各元件或結構以單-元件或結構描述制時，不應以 . 此做為有限定的認知，即如下之制未特別_數目上的關時，本發明 ' 之精神與應用範圍可推及多數個元件或結構並存的結構與方法上。再者， 在本說明書巾，各元件之不同部分並沒有依照尺寸繪目。某些尺度與其他 相關尺度相比已經被誇張或是簡化，以提供更清楚的描述和本發明的理 #解。而本發日蘭沿㈣現有技藝，在此僅作重點式的制，以助本發明的 闡述。 第-圖為根據本發明之-實施例，提供透明基板的剖面示意圖。參照 第-圖’基板10係具有-透明基板101與若干導電連接結構突出於透明基 板101上。於一實施例中，透明基板1〇1為一玻璃基板，利用適當的方式， 例如乾_的方式’先於透明基板，⑴之適當位置處形成若干凹陷(圖上未 不)並配置中間結構1〇2，例如苯環丁稀(Benz〇cyc丨〇but的㊀,BCB)或其他非 7 1298195 / 導電性黏著材料於凹陷中形成突起後，再以適當方式，例如電鍍的方i， • 形成一導電層· 1〇3於中間結構1〇2上與導電墊1〇4以構成導電連接結構 105連接透明基板101上的導電跡線(trace，圖上未示）。 第二A圖為根據本發明之一實施例，提供半導體晶圓的剖面示意圖。 參照第二A圖，晶圓20a具有若干的晶片201a、201b與201c彼此以切 割道205相鄰。每一晶片201a、201b與201c的一主動面具有一感測區域 203a、203b、203c與若干導電墊2〇4a、204b、204c配置於感測區域2〇3a、 參203b、203c的周圍。其次，於晶圓2〇a的主動面之相反側的一背面上以適 當的方式形成黏著層401後接合另一相同的晶圓2〇b，即堆疊晶圓以背靠 背的方式接合。 於此實施例中，晶片20ia、201b與201c係為尺寸相同的晶片，然本 發明亦可應用具有不同尺寸晶片的晶圓。其次，晶片2〇1a、2〇化與2〇化 為與光感測功能相關的晶片，因此感測區域2〇3a、2〇3b、2〇3c為一接受 φ光線的區域’然本發明不限於此種功能的晶片。再者，導電墊204a、204b、 204c係以適當的方式，例如電麟方式形成。由於導錢2_、2〇北、 204c與透明基板仙之導電墊，〇4係、可用以控制基板與晶圓的間隙，因此 V電塾204a 204b、204c與導電塾1〇4兩者的厚度可以相互搭配以符合 ❿十所需。於另一實施例中，導電塾2〇4a、2〇4b、2〇4c與導電塾1〇4亦 可擇-形成所需的高度即可，且f性連接至導電連接結構·。根據本發 明之精神’可制於對應位置具有相同尺寸之晶#的接合。 1298195 第二B圖為根據本發明之一實施例，處理半導體晶圓的射面示意圖。 •將半導體晶圓利用一膠層404放置於一承載板403上，以晶圓20b(或2〇a) __的主動面接近承載板403上的膠層404 ,以作為後續填充時的阻_满。 第二C圖為根據本發明之一實施例，處理半導體晶圓力剖面示意圖。 於切割道的位置上製作貫穿兩晶圓2〇a、2〇b之主動面的貫孔4〇5。第二D 圖為根據本發明之-實施例’於半導體中印刷黏著層的剖面示意圖。 _參照第二D圖，利用適當的方式，例如印刷或塗佈(dispense)的方式，將黏 者層406置人晶圓的每—貫孔4Q5中以作為後續黏著之用。於—實施例中， 黏著層406可以為-般的黏著材料，例如環氧材料(ep〇xy峨㈣其於 每-貫孔405中的份量並無_關，以後續製程中不會溢出至晶圓的表 面上為佳，其次膠層404則作為避免黏著層4〇6流至晶圓2〇a、2〇b之主 動面的阻擋結構之用。 第三A圖為根據本發明之一實施例，接合透明基板與半導體晶圓的剖 _面不意圖。參照第三八目，將透明基板1〇1的導電連接結構1〇5接近並置 入晶圓之貫孔405中接觸並陷入黏著層4〇6中，且導電墊2〇4a、2〇4b、 204c與導電墊104兩者彼此接觸控制透明基板1〇1與晶圓之間的間隙高 度再名，曰曰圓主動面上的輸入/輸出控制(l/Qc〇nt「〇l)可藉由導電塾2〇4a、 204b、204c與導餘1〇4的接觸以及導電連接結構1〇5傳送至晶圓的背 面。決定透明基板1〇1與晶圓的間隙後進行黏著層4〇6硬化(curing)處理後 移除膠層4〇4與承載板403。之後可以進行_微_步驟以暴露出導電連 接結構105的一側於下方晶圓20b的主動面上。 1298195 第三日@為根據本發明之—實施例，製作接合透明基板與半導體晶圓 之重佈線路層的剖面示意圖。一介電層5〇5覆蓋於遠離透明基板仙之晶 圓2〇b與暴露出的導電連接結構1〇5上，利用一般微影移除方式，移料曰 分介電層505,以暴露出導電連接結構1()5、晶圓咖之導電墊3⑽獅 與304c。之後，形成一導電層5〇6接觸暴露出的導電連接結構伽、晶圓 20b的導電墊204a、204b、2〇4c。於此實施例中介電層5〇5可以為苯 環丁稀(BCB)層或聚醯亞胺㈣，利用本身作為光阻進行微影，或是利用一 般形成光阻層(圖上未示)而後進行微影移除步驟4電層咖，例如利用賤 鍍金属層而後微刻的方式製作用以重佈的線路4需要多層重佈線路 層時’可以重複上述步驟依序再形成介電層5〇7與導電層5〇8。根據本發 明之-貫施例，精由導電連接結構1〇5與導電墊1〇4能夠將晶圓之一表面 的電訊號傳遞至晶圓另一側，並可藉重佈線路層㈣ist_0n丨ay啦^ 後續製程中的錫球上。 ’ 第二C圖為根據本發明之_實施例，接合透縣板與半導體晶圓並製 作錫球與進行切割的剖面示意圖。繼續形成介電層509與導電層51〇後， 首先-絕緣層512覆蓋於導電層咖與暴露出的介電層5的上，利用一般 的微影移除步驟，移除部份的絕緣層512以暴露_銲塾，即所有導電又 ㈣6、5〇8、510位於一由所有介電層507、509與絕緣層512所組成的 =結構中。之後’以—般形鱗稿_方式形成若干導電凸塊⑽於 暴露㈣導電㈣上。於—實施例中，絕緣層512，例如_阻銲綠漆⑽你 mas ’可作為光阻與保護之用，塗佈而後微影的方式製作出圖案化的 1298195 絕緣層512。導電凸塊513，例如以錫紹或無錯材料為主，利用一般植球的 方式形成。之後，取切割道中線5_be咖eMine)上進行晶圓切割(dje singulation)以形成堆疊晶粒的封裝結構。根據本發明之精神，導電連接結 構105位於切割道中線5的位置，並藉由導電層5〇6、5〇8與51〇電性連 接至導電凸塊513，增加設計元件的彈性。 … 根據上述，本發明之一實施例提供一種晶圓級堆疊封裝的方法，一基 板具有複數個導電連接結構突出於其上。兩晶圓，每—晶圓具有一主動面 與位於相反側的-背©，其中每—晶圓包含複數個晶片彼此相鄰接及複數 個導電塾配置於每-主動面上。固定兩晶圓，係以兩晶圓之兩背面互相連 接。移除部份兩晶圓藉以形成複數個貫孔，其巾每—貫孔位於任兩晶片之 間的-士刀割道上。填入一黏著層於每一個貫孔中。接合基板與兩晶圓，其 中每-導電連接結構係位於其相對應之每—貫孔的黏著層巾。—導電線路 層形成於遠離該基板之晶K的絲面上並接觸每—導電連接結構與遠離基 板之晶圓的主動面上之導電墊。一介電層形成於導電線路層之間且暴露出 心導電線路層。複數個導電凸塊形成於介電層上並_暴露出的導電線 路層。 ' 根據上述，兩晶粒以各自的背面固定，每一晶粒的主動面上配置複數 個導電墊’其中-晶粒的絲面面對—基板，且兩晶粒的尺寸相同。複數 個導電連接結構，個職固定於基板上與兩晶粒之邊緣，其中每一導電連 接結構從基板延伸至遠絲板的絲面上轉_導電連接結構暴露於遠離 基板的主動面上。-導電線路層位於遠離基板的主動面上並接觸每一導電 1298195 連接結構與遠離基板的主動面上複數個導電整…介電結構位於導電線路 • 層上並暴露出部分導電線路層。 _ 以上所述僅為本發明之較佳實施例，並非用以限定本發明之申請專利 範圍。在不脫離本發明之實質内容的範疇内仍可予以變化而加以貪施，此 等變化應仍屬本發明之範圍。因此，本發明之範疇係由下列申請專·利範圍< 所界定。 【圖式簡單說明】 第一圖為根據本發明之一實施例，提供透明基板的剖面示意圖。 第二A圖為根據本發明之一實施例，提供半導體晶圓的剖面示意圖。 第二B圖為根據本發明之一實施例，處理半導體晶圓的剖面示意圖。 第二C圖為根據本發明之一實施例，處理半導體晶圓的剖面示意圖。 第二D圖為根據本發明之一實施例，於半導體晶圓中印刷黏著層的到 面示意圖。 第二A圖為根據本發明之一實施例，接合透明基板與半導體晶圓的剖 面示意圖。 第二B圖為根據本發明之一實施例，製作接合透明基板與半導體晶圓 之重布層的剖面示意圖。 第三C圖為根據本發明之一實施例，接合透明基板與半導體晶圓並製 12 1298195 作錫球與切割的剖面示意圖。 【主要元件符號說明】 5切割道中線 _ 10基板 101 透明基板 102 中間結構 103 導電層 104 導電墊 _ 105導電連接結構 20a、20b 晶圓 201a、201b、201c 晶片 203 a、203b、203c 感測區域 204 a、204b、204c 導電墊 205 切割道 401黏著層 403承載板 404膠層 405貫孔 406黏著層 505、 507、509 介電層 506、 508、510 導電層 512 絕緣層 513 導電凸塊 131298195 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a "package structure of a particle" and a method of sealing the same, and more particularly to an integrated microelectromechanical (MEMS) and contact image sensor (c〇nta (1) alum CIS) stacking the same die riding structure and its packaging method. [Prior Art] The semiconductor process of the semiconductor makes the scale-component keel body element formation, such as contact image sensor (Qing Compared with the CCD image sensing tree, even if the CIS component is added with its package structure, it still has its advantages in volume and price. The shame image packaging product is pushed into a wide variety of products. A change in the existing product design considerations 'How to increase the design flexibility of the image sensing package is an important factor in the wide application of CIS components. In addition, when CIS is used in affordable products, how to reduce The process cost of CIS components is also an important issue. In addition, the integration of MEMS components and CIS components into a package component is also an important issue in today's miniaturized packaging. The components move relatively, so how to make a low-cost integrated package structure and method is a problem that needs to be solved urgently. [Invention] In view of the above-mentioned background towel, the integrated microelectromechanical component and the connection image sensor package design I 1298195 Elasticity, here provides a package structure of a stacked wafer and a method for forming the same, and the integrated structure of the wafer and the die is passed through the other side of the stacked wafer to increase the MEMS element and contact The flexibility of the image sensor package design. ^There is a desire to lose the butterfly & wheel _ butterfly Gangxian County, here to mention the integrated stack "chip package structure and its formation method, the substrate process to form a stackable wafer The structure 'can reduce the complexity of the wafer process and increase the yield of the wafer. Illustrate an embodiment of the present invention to provide a wafer level stacked package method, a substrate having a plurality of conductive connections. Two "each-pure one active surface and the opposite side-back side" each wafer contains a plurality of wafers adjacent to each other and a plurality of conductive Wei turn-sides ± Round, the back sides of her (four) are connected to each other. Part of the two crystals are removed to form a plurality of through holes, wherein each of the through holes is located on the -cutting path between any two wafers. The filling-adhesive layer is in each pass. The hole h is bonded to the substrate and the two wafers, wherein each of the conductive connection structures is located at each of the corresponding through holes, and is exposed to the active surface of the wafer that passes through the board. A conductive circuit layer is formed. a conductive surface on the active surface of the wafer remote from the substrate and contacting the active surface of the wafer and the wafer away from the substrate. The dielectric layer is formed between the conductive circuit layers and exposes a portion of the conductive circuit layer. A plurality of conductive bumps are formed on the dielectric layer and contact the exposed conductive circuit layer. According to the above, the two crystal grains are fixed on the respective back surfaces, and a plurality of conductive pads are disposed on the active surface of each of the crystal grains, wherein one crystal The active face of the granule faces a substrate, and the two dies are the same size. A plurality of conductive connection structures are separately fixed on the substrate and the edges of the two crystal grains, wherein each conductive connection 1298195 is extended from the substrate to the active surface away from the substrate and each conductive connection structure is exposed to the active substrate away from the substrate On the surface. A conductive circuit layer is located away from the active surface of the substrate and contacts each conductive connection structure and a plurality of conductive pads on the active surface of the substrate. A dielectric structure is on the isoelectric wiring layer and exposes a portion of the conductive wiring layer. [Embodiment] Some embodiments of the present invention will be described in detail below. However, the present invention may be widely practiced in other embodiments in addition to the detailed description. That is, the scope of the present invention is not limited by the embodiments which have been proposed, and the scope of the patent application proposed by the present invention shall prevail. Secondly, when the embodiments of the present invention illustrate that the elements or structures of the towel are described in a single-element or structure, this should not be taken as a limited cognition, that is, the following system is not special. The spirit and scope of the invention may be derived from the structure and method in which a plurality of elements or structures coexist. Furthermore, in the specification of the present specification, different parts of the components are not drawn in accordance with the dimensions. Certain scales have been exaggerated or simplified compared to other related scales to provide a clearer description and the rationale for the present invention. However, the current skills of this article are based on (4) the prior art, and only the key system is used here to assist in the description of the present invention. Fig. - is a schematic cross-sectional view showing a transparent substrate in accordance with an embodiment of the present invention. Referring to Fig. 1, the substrate 10 has a transparent substrate 101 and a plurality of conductive connecting structures protruding from the transparent substrate 101. In one embodiment, the transparent substrate 1〇1 is a glass substrate, and a plurality of depressions (not shown) are formed at appropriate positions of the transparent substrate in a suitable manner, for example, in a dry manner, and the intermediate structure is disposed. 1 〇 2, such as benzocyclobutene (Benz 〇 丨〇 丨〇 丨〇 的 ( 〇 〇 或 或 或 或 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 A conductive layer is formed on the intermediate structure 1〇2 and the conductive pads 1〇4 to form a conductive connection structure 105 to connect conductive traces on the transparent substrate 101 (not shown). Figure 2A is a schematic cross-sectional view of a semiconductor wafer in accordance with an embodiment of the present invention. Referring to the second A diagram, the wafer 20a has a plurality of wafers 201a, 201b and 201c adjacent to each other by a cutting lane 205. An active mask of each of the wafers 201a, 201b, and 201c has a sensing region 203a, 203b, 203c and a plurality of conductive pads 2A, 4a, 204b, 204c disposed around the sensing regions 2A, 3a, 203b, 203c. Next, an adhesive layer 401 is formed in an appropriate manner on a back surface on the opposite side of the active surface of the wafer 2A, and another identical wafer 2b is bonded, that is, the stacked wafers are bonded back to the back. In this embodiment, the wafers 20ia, 201b, and 201c are wafers of the same size, but the present invention can also apply wafers having wafers of different sizes. Secondly, the wafers 2〇1a, 2 are deuterated and converted into wafers related to the light sensing function, so the sensing regions 2〇3a, 2〇3b, 2〇3c are regions that receive φ rays. It is not limited to a wafer of such a function. Furthermore, the conductive pads 204a, 204b, 204c are formed in a suitable manner, such as a galvanic manner. Because of the conductive pad 2_, 2〇北, 204c and the transparent substrate, the 〇4 series can be used to control the gap between the substrate and the wafer, so the thickness of the V-electrode 204a 204b, 204c and the conductive 塾1〇4 Can be matched to each other to meet the needs of the ten. In another embodiment, the conductive 塾2〇4a, 2〇4b, 2〇4c and the conductive 塾1〇4 may alternatively be formed to a desired height, and the f-type is connected to the conductive connection structure. According to the spirit of the present invention, the joining of crystals having the same size at the corresponding positions can be made. 1298195 FIG. 2B is a schematic view of a facet of a semiconductor wafer processed in accordance with an embodiment of the present invention. • The semiconductor wafer is placed on a carrier 403 by using a glue layer 404, and the adhesive layer 404 on the carrier 403 is approached by the active surface of the wafer 20b (or 2〇a)__ as a resistance during subsequent filling. _full. Figure 2C is a schematic cross-sectional view of a process for processing a semiconductor wafer in accordance with an embodiment of the present invention. A through hole 4〇5 penetrating the active faces of the two wafers 2〇a, 2〇b is formed at the position of the dicing street. The second D is a schematic cross-sectional view showing the printing of an adhesive layer in a semiconductor according to an embodiment of the present invention. Referring to the second D diagram, the adhesive layer 406 is placed in each of the through holes 4Q5 of the wafer for use as a subsequent adhesive by a suitable means such as printing or dispensing. In an embodiment, the adhesive layer 406 may be a general adhesive material, such as an epoxy material (ep〇xy峨(4), and the amount of each of the adhesive layers 405 is not _off, so as not to overflow into the subsequent process. Preferably, the surface of the wafer is used as a barrier structure for preventing the adhesive layer 4〇6 from flowing to the active faces of the wafers 2〇a, 2〇b. The third A is a method according to the present invention. In the embodiment, the cross-section of the transparent substrate and the semiconductor wafer is not intended. Referring to the third and eighth objects, the conductive connection structure 1〇5 of the transparent substrate 1〇1 is placed close to the through hole 405 of the wafer and is caught. In the adhesive layer 4〇6, and the conductive pads 2〇4a, 2〇4b, 204c and the conductive pad 104 are in contact with each other to control the gap height between the transparent substrate 1〇1 and the wafer, the circular active surface The input/output control (l/Qc〇nt "〇l) can be transferred to the back side of the wafer by the contact of the conductive electrodes 2〇4a, 204b, 204c with the drain 1〇4 and the conductive connection structure 1〇5. After the gap between the transparent substrate 1〇1 and the wafer is performed, the adhesive layer 4〇6 is cured, and the adhesive layer 4〇4 and the carrier plate 403 are removed. A micro-step is performed to expose one side of the conductive connection structure 105 to the active surface of the lower wafer 20b. 1298195 The third day is a rewiring of the bonded transparent substrate and the semiconductor wafer according to the embodiment of the present invention. Schematic diagram of the cross-section of the road layer. A dielectric layer 5〇5 is covered on the transparent substrate 2〇b and the exposed conductive connection structure 1〇5, and the general lithography removal method is used. The electric layer 505 is exposed to expose the conductive connection structure 1 () 5, the conductive pad 3 (10) lion and 304c of the wafer coffee. Thereafter, a conductive layer 5 〇 6 is formed to contact the exposed conductive connection structure gamma, and the conductive pad of the wafer 20b 204a, 204b, 2〇4c. In this embodiment, the dielectric layer 5〇5 may be a benzene ring butyl (BCB) layer or a polyimide (IV), which is used for photolithography to perform lithography, or to generally form light. The resist layer (not shown) is then subjected to a lithography removal step 4, for example, by using a ruthenium-plated metal layer and then micro-engraving to form a wiring 4 for re-wiring, which requires multiple layers of redistributed wiring layers. The steps sequentially form the dielectric layer 5〇7 and the conductive layer 5〇8. In the case of the Ming-Cheng Shi, the conductive connection structure 1〇5 and the conductive pad 1〇4 can transfer the electrical signal on one surface of the wafer to the other side of the wafer, and can be transferred to the wiring layer (4) ist_0n丨ay啦 Follow On the solder ball in the process. 'Second C is a schematic cross-sectional view of bonding a plate and a semiconductor wafer and making a solder ball and cutting according to an embodiment of the present invention. The dielectric layer 509 and the conductive layer 51 are continuously formed. Thereafter, first, an insulating layer 512 is overlaid on the conductive layer 5 and the exposed dielectric layer 5, and a portion of the insulating layer 512 is removed by a general lithography removal step to expose the ITO, that is, all of the conductive layers. Further, (4) 6, 5 〇 8, 510 are located in a structure composed of all dielectric layers 507, 509 and insulating layer 512. Thereafter, a plurality of conductive bumps (10) are formed on the exposed (four) conductive (four) in a manner of a regular scale. In an embodiment, the insulating layer 512, such as _ solder resist green lacquer (10), can be used as a photoresist and protection for coating and then lithographically to form a patterned 1298195 insulating layer 512. The conductive bumps 513 are mainly made of tin-sand or error-free materials, and are formed by a general ball. Thereafter, wafer dicing is performed on the scribe line center line to form a package structure of the stacked dies. In accordance with the spirit of the present invention, the conductive connection structure 105 is located at the center line 5 of the scribe line and is electrically connected to the conductive bumps 513 by the conductive layers 5〇6, 5〇8 and 51〇, increasing the elasticity of the design element. According to the above, an embodiment of the present invention provides a method of wafer level stacked package, a substrate having a plurality of conductive connection structures protruding thereon. The two wafers each have an active surface and a back surface on the opposite side, wherein each wafer includes a plurality of wafers adjacent to each other and a plurality of conductive electrodes disposed on each of the active surfaces. The two wafers are fixed by connecting the back sides of the two wafers to each other. A portion of the two wafers are removed to form a plurality of through-holes, each of which is located on the - knife cut between any two wafers. Fill in an adhesive layer in each of the through holes. The substrate and the two wafers are bonded, wherein each of the conductive connection structures is located in the corresponding adhesive layer of each of the through holes. - A conductive trace layer is formed on the surface of the filaments away from the crystal K of the substrate and contacts the conductive pads of each of the conductive connection structures and the active surface of the wafer remote from the substrate. A dielectric layer is formed between the conductive wiring layers and exposes the core conductive wiring layer. A plurality of conductive bumps are formed on the dielectric layer and are exposed to the conductive wiring layer. According to the above, the two crystal grains are fixed on the respective back faces, and a plurality of conductive pads are disposed on the active faces of each of the crystal grains. Wherein the filament faces of the crystal grains face the substrate, and the two crystal grains have the same size. A plurality of conductive connection structures are fixed on the substrate and the edges of the two crystal grains, wherein each of the conductive connection structures extends from the substrate to the surface of the far wire plate. The conductive connection structure is exposed to the active surface away from the substrate. The conductive circuit layer is located away from the active surface of the substrate and contacts each of the conductive 1298195 connection structure and the active surface away from the substrate. The plurality of conductive structures are located on the conductive circuit layer and expose a portion of the conductive circuit layer. The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of the patent application of the present invention. Changes may be made without departing from the spirit and scope of the invention, and such changes are still within the scope of the invention. Accordingly, the scope of the invention is defined by the following claims. BRIEF DESCRIPTION OF THE DRAWINGS The first figure is a schematic cross-sectional view of a transparent substrate according to an embodiment of the present invention. Figure 2A is a schematic cross-sectional view of a semiconductor wafer in accordance with an embodiment of the present invention. Figure 2B is a schematic cross-sectional view of a semiconductor wafer processed in accordance with an embodiment of the present invention. Figure 2C is a cross-sectional view of a process for processing a semiconductor wafer in accordance with an embodiment of the present invention. The second D-figure is a schematic illustration of the printing of an adhesive layer in a semiconductor wafer in accordance with an embodiment of the present invention. Figure 2A is a cross-sectional view of a bonded transparent substrate and a semiconductor wafer in accordance with an embodiment of the present invention. Figure 2B is a cross-sectional view showing the fabrication of a redistribution layer that bonds a transparent substrate to a semiconductor wafer in accordance with an embodiment of the present invention. Figure 3C is a cross-sectional view showing the bonding of a transparent substrate to a semiconductor wafer and making 12 1298195 solder balls and cuts according to an embodiment of the present invention. [Main component symbol description] 5 scribe line center line _ 10 substrate 101 transparent substrate 102 intermediate structure 103 conductive layer 104 conductive pad _ 105 conductive connection structure 20a, 20b wafer 201a, 201b, 201c wafer 203 a, 203b, 203c sensing area 204 a, 204b, 204c conductive pad 205 cutting track 401 adhesive layer 403 carrier plate 404 adhesive layer 405 through hole 406 adhesive layer 505, 507, 509 dielectric layer 506, 508, 510 conductive layer 512 insulating layer 513 conductive bump 13