TWI478302B - 具堆疊功能之晶圓級半導體封裝件 - Google Patents

具堆疊功能之晶圓級半導體封裝件 Download PDF

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Publication number
TWI478302B
TWI478302B TW099123457A TW99123457A TWI478302B TW I478302 B TWI478302 B TW I478302B TW 099123457 A TW099123457 A TW 099123457A TW 99123457 A TW99123457 A TW 99123457A TW I478302 B TWI478302 B TW I478302B
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Taiwan
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semiconductor component
package
semiconductor
active surface
stacked
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TW099123457A
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English (en)
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TW201135889A (en
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Yi Chuan Ding
Chia Ching Chen
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Advanced Semiconductor Eng
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Description

具堆疊功能之晶圓級半導體封裝件
本發明是有關於一種半導體封裝件，且特別是有關於一種具有堆疊功能之晶圓級半導體封裝件。
半導體元件日趨複雜，使其至少需要在某種程度上縮小尺寸以及增強功能。然而在縮小尺寸以及增強功能得到好處的時候，半導體元件也同時產生出相應的問題。
在一般的晶圓級封裝，半導體元件係先封裝於晶圓中，在對晶圓作切割製程。如此，一般的晶圓級封裝會受限於一扇入結構(即電性接觸件)，而一完成的半導體封裝件之其他元件會被限制在由半導體元件周圍所定義之區域。任何設置於半導體元件周圍外之元件通常不被支援，且一般皆在切割製程中被移除。在元件持續微縮而元件功能持續增加的情況下，此一扇入結構之限制將形成挑戰。
電子產品通常必須在有限的空間中容置高密度的半導體元件。舉例來說，對於製造者、記憶體元件、及其他主動或被動元件來說，在手機、PDA、膝上型電腦、及其他可攜式消費產品中可用的空間是更進一步受到限制的。在半導體封裝件中的半導體封裝可在電子產品內產生額外新增的有用空間。如此，現有的強大的技術趨勢是傾向在一半導體封裝件所占有的一腳位區域(footprint)下增加半導體元件密度。不幸的是，一般傳統的晶圓級封裝對於處理此技術趨勢是不恰當的。
這和背景有所衝突，因而產生發展晶圓級半導體封裝件、相關的堆疊封裝組裝件及方法的需求。
根據本發明之一方面係提供一種具有堆疊功能之晶圓級半導體封裝件及相關堆疊封裝組裝件。在一實施例中，一半導體封裝件包括：(1)一重新分佈單元包括一上表面；(2)一組堆疊半導體元件包括：(a)一第一半導體元件設置鄰接於重新分佈單元，且包括一第一主動表面，此第一主動表面係面對重新分佈單元之上表面，以及(b)一第二半導體元件設置鄰接於該第一半導體元件，且包括一第二主動表面，此第二主動表面係背向於第一主動表面；(3)一組連接元件設置鄰接於堆疊半導體元件之一周圍，且皆由重新分佈單元之上表面向上延伸，此連接元件包括：(a)一第一連接元件包括一第一上底端，以及(b)一第二連接元件包括一第二上底端，第二上底端銲線接合至第二半導體元件之第二主動表面；以及(4)一封裝體設置鄰接於重新分佈單元之上表面，且覆蓋此堆疊半導體元件及連接元件，封裝體包括一中央上表面和一外圍上表面，封裝體之中央上表面係位於第二半導體元件之第二主動表面之上，第一連接元件之第一上底端係暴露鄰接於封裝體之外圍上表面。
根據本發明之另一方面，提出一種形成具有堆疊功能之晶圓級半導體封裝件之製造方法。在一實施例中，一製造方法包括：(1)提供一第一半導體元件及一第二半導體元件，第一半導體元件包括一第一主動表面，第二半導體元件包括一第二主動表面；(2)堆疊第一半導體元件及第二半導體元件，使第一主動表面及第二主動表面彼此相背；(3)施加一第一封膠材料形成封膠結構，以覆蓋第一半導體元件及第二半導體元件之邊緣，封膠結構包括一前表面及一相對之背表面，第一半導體元件之第一主動表面係至少部分暴露鄰接封膠結構之前表面，第二半導體元件之第二主動表面係至少部分暴露鄰接封膠結構之背表面；(4)形成一組通孔，此組通孔於封膠結構之前表面和背表面間作延伸，且環繞第一半導體元件及第二半導體元件；(5)施加一導電材料於通孔中以形成一組連接元件；(6)形成一重新分佈單元，此重新分佈單元鄰接於第一半導體元件之第一主動表面及封膠結構之前表面；(7)通過一組焊線，用以電性連接第二半導體元件之第二主動表面至連接元件中的至少其中之一；以及(8)施加一第二封膠材料，此第二封膠材料鄰接於第二半導體元件之第二主動表面及封膠結構之背表面，以形成一封膠體，此封膠體包括一中央部分及一外圍部分，中央部分有一中央厚度HP1 以覆蓋第二半導體元件之第二主動表面及焊線，外圍部分有一外圍厚度HP2 以至少部分暴露至少一組連接元件之一底端。
本發明之其他方面和實施例也都被仔細考慮。前述發明內容及相關特殊實施例的詳細描述並非用以限制本發明，僅用於說明本發明之部分實施例。
下列定義係本發明之某些實施例在某些觀點上之應用說明。這些定義同樣也可以與此之上作延伸。
除非內文中明確地指明，否則於此所用的單數項“a”、“an”以及“the”包含了數個指示對象。故舉例來說，除非內文中明確地指明，否則當提及一電性互連件時，此一電性互連件可包含數個電性互連件。
於此所用的項目“set”係表示一個或多個元件的集合。故舉例來說，一層組可以包含單一個層或多個層。一組之元件(components of a set)也可以視為是此組之一部份(members of the set)。一組之元件可以是相同或不同的。在某些例子中，一組之元件可以共用一個或多個共同的特徵。
於此所用的項目“adjacent”係表示鄰近或靠近。鄰近的數個元件可彼此相互分開或者是實質上彼此相互直接接觸。在某些例子中，鄰近的數個元件可以彼此相互連接或者是一體成形。
於此所用例如是“inner”、“interior”、“outer”、“exterior”、“top”、“bottom”、“front”、“back”、“upper”、“upwardly”、“lower”、“downwardly”、“vertical”、“vertically”、“lateral”、“laterally”、“above”以及“below”之相關項目係表示一元件組相對於另一元件組之方向，例如是如圖式所示，但此些元件在製造過程中或使用中並不需要侷限在特定的方向。
於此所用的項目“connect”、“connected”以及“connection”係表示操作上的耦合或連結。數個連接元件可以彼此相互直接耦合，或者是彼此相互間接耦合，彼此相互間接耦接例如藉由另一組之元件來達成。
於此所用的項目“substantially”以及“substantial”係表示一應考慮的等級程度或範圍。當上述之項目連同一個事件或情況一起使用時，上述之項目可以表示事件或情況準確地發生之實例，以及可以表示事件或情況在非常接近地狀況下發生之實例，例如像是在此說明之一般製造操作的容忍程度。
於此所用的項目“electrically conductive”以及“electrically conductivity”係表示一電流傳輸之能力。電性傳導材料通常是那些顯現出極小或者沒有反抗電流流通之材料。每公尺數個西門子(Siemens per meter，“S‧m-1 ”)係為導電性的一種度量單位。一般來說，一電性傳導材料係具有大於104 S‧m-1 之傳導性，例如是最少約為105 S‧m-1 或者最少約為106 S‧m-1 。一材料之導電性有時可以隨溫度而變化。除非另有明確說明，一材料之導電性是於室溫下所定義。
首先請參照第1A圖和第1B圖，第1A圖和第1B圖繪示依照本發明實施例之晶圓級半導體封裝件100的示意圖。其中第1A圖繪示封裝件100之示意圖，而第1B圖繪示乃第1A圖之封裝件100沿著第1A圖之A-A線的剖面圖。
請參照第1B圖，封裝件100包括複數個半導體元件，其中包括半導體元件102及半導體元件104，半導體元件104設置鄰接於半導體元件102。在此實施例，於封裝件100中，半導體元件102及104係被設置為一堆疊結構，元件彼此之間係為一安全的合適形式，比如利用一晶粒貼附薄膜或一黏著層。於封裝件100中，此半導體元件102及104之堆疊結構具有可在一給定之腳位區域之下，於封裝件100中達到一更高密度的半導體元件之優點。雖然第1B圖中繪示二個半導體元件102及104，在其他實施中，其中亦可以包括更多或更少之半導體元件來用以實現其他之應用。更特別的是，經由額外增加的半導體元件在封裝件100中，可以實現出具有更高密度之半導體元件。
如第1B圖所示，半導體元件102包括一上表面108和一下表面106，上表面108為半導體元件102之背表面，而下表面106為半導體元件102之一主動表面，下表面106上具有接觸墊114a和114b，接觸墊114a和114b係和下表面106鄰接設置。半導體元件104包括一下表面110和一上表面112，下表面110為半導體元件104之一背表面，上表面112為半導體元件104之一主動表面，上表面112上具有接觸墊116a和116b，接觸墊116a和116b係和上表面112鄰接設置。接觸墊114a和114b為半導體元件102提供輸入電性連接點和輸出電性連接點，而接觸墊116a和116b為半導體元件104提供輸入電性連接點和輸出電性連接點。在此實施例中，半導體元件102和104係為一背對背堆疊結構來設置，如此，半導體元件102和104的背表面係彼此面對，而半導體元件102和104的主動表面係為彼此背向。然而，可以推想得到的是，在其他實際應用情形中，半導體元件102和104之堆疊可以具有不同之結構。於此實施例中，雖然各半導體元件102和104係為一半導體晶片，然而一般來說，半導體元件102和104亦可以是任意之主動元件、任意之被動元件、或其中任意元件之組合。如第1B圖所示，相較於半導體元件104，半導體元件102有一較大的橫向延伸，然而半導體元件102也可以具有一較小之橫向延伸，或者半導體元件102和104具有一實質上相同之橫向延伸。
參照第1A圖和第1B圖，封裝件100也包括一重新分佈單元118，重新分佈單元118鄰接地設置於半導體元件102之下表面106。重新分佈單元118係電性連接於半導體元件102和104，其不但提供電性路徑，更提供機械穩定度及針對環境因素之保護。如第1A圖和第1B圖所示，重新分佈單元118包括一下表面120、一上表面122、以及側向表面124和126，側向表面124和126鄰接地設置於重新分佈單元118之周圍，且於下表面120和上表面122之間延伸。在此實施例中，各表面120、122、124、及126實質上為平面，側向表面124和126相對下表面120或上表面122實質上具有直角方向，然而在其他實施中，表面120、122、124、及126之形狀及方向可以有所改變。相對於半導體元件102和104，重新分佈單元118之周圍(由側向表面124和126所定義)具有較大之側向範圍，因此可使封裝件100以扇出結構來實現，即封裝件100之元件可設置於由半導體元件102或104周圍所定義的區域之內和之外。
在此實施例中，重新分佈單元118係於製造中形成一組重新分佈層，然而在其他實施中，重新分佈單元118可以包括一預先形成結構。參照第1B圖，重新分佈單元118係為多層的，且包含一對介電層128和130及導電層132，至少部分之導電層132係被夾於介電層128及130之間形成三明治結構。一般來說，各一介電層128和130可由一介電材料所形成，此介電材料可為聚合物或非聚合物。舉例來說，介電層128和130中至少有一者由聚亞醯胺(polyimide)、聚苯噁唑(polybenzoxazole)、苯環丁烯(benzocyclobutene)或以上材料之組合物所形成。介電層128和130可由相同的介電材料或不同的介電材料形成。就一個實例來說，介電層128和130中至少有一層可由光可成像或感光的介電材料來形成，如此可藉由利用微影製程製作圖案來減少製造成本與時間。雖然第1B圖中繪示二個介電層128和130，然而在其他實施中，其中亦可以包含更多或更少之介電層。
如第1B圖所示，介電層128具有一組開口，此開口係經過位置上之對準及尺寸上之調整，以至少可部分暴露出接觸墊114a和114b，且允許接觸墊114a和114b電性連接至導電層132，且另一組經過位置上之對準及尺寸上之調整之開口係至少部分暴露出導電層132，以鄰接至重新分佈單元118之上表面122及半導體元件102或104周圍的外圍。參照第1B圖，介電層130具有數個開口，此些開口係經由位置上之對準，使介電層130至少部分暴露出導電層132，以鄰接重新分佈單元118之下表面120，且此些開口係經過尺寸上之調整以容納電性接觸件132a、132b、132c、及132d。電性接觸件132a、132b、132c、及132d為封裝件100提供輸入電性連接點和輸出電性連接點，且電性接觸件132a、132b、132c、及132d之至少一個子集係通過導電層132電性連接至半導體元件102和104。於此實施例中，電性接觸件132a、132b、132c、及132d係為焊接凸塊，且依照封裝件100之扇出結構，電性接觸件132a、132b、132c、及132d係橫向地設置於半導體元件102或104周圍之外部。然而，一般來說，電性接觸件132a、132b、132c、及132d可以橫向地設置於半導體元件102或104周圍之內、半導體元件102或104周圍之外、或分佈於半導體元件102或104周圍之內外。據此，藉由降低對半導體元件102之接觸墊114a和114b的空間設置和間距的相依關係及降低對半導體元件104之接觸墊116a和116b的空間設置和間距的相依關係，可使得封裝件100之扇出結構可就電性接觸件132a、132b、132c、及132d的空間設置和間距之設計提供允許更大的彈性。
對於半導體元件102的接觸墊114a和114b以及半導體元件104的接觸墊116a和116b來說，導電層132係為一重新分佈網路，且依照封裝件100的扇出結構，導電層132係橫向地延伸於重新分佈單元118中以及半導體元件102或104周圍的內部跟外部。如第1B圖所示，導電層132包括一電性互連件134a、一電性互連件134b，以及一電性互連件134c，電性互連件134a電性連接至電性接觸件132a，且暴露並鄰接於重新分佈單元118之上表面122。電性互連件134b將電性接觸件114a和116a電性連接至電性接觸件132b，且暴露並鄰接於重新分佈單元118之上表面122。電性互連件134c將接觸墊114b和116b電性連接至電性接觸墊132c和132d，且暴露並鄰接於重新分佈單元118的上表面122。一般來說，各電性互連件134a、134b、及134c可由金屬、金屬合金、金屬或金屬合金分散於其中之材料、或另一合適的導電材料形成。舉例來說，電性互連件134a、134b、及134c中至少有一可被當作是一組孔洞及一組電性線路，該組孔洞及電性線路係由鋁、銅、鈦或其組合物所形成。電性互連件134a、134b、及134c可由相同的導電材料或不同的導電材料所形成。雖然第1B圖中繪示一個導電層132，然而在其他實施中，其亦可以包含有額外增加的導電層。
如第1B圖所示，封裝件100也包含了連接元件136a、136b、136c、及136d，連接元件136a、136b、136c、及136d設置於半導體元件102或104周圍的外部。連接元件136a、136b、136c、及136d自導電層132向上作延伸。連接元件136a係電性連接電性互連件134a，並且自電性互連件134a向上作延伸；連接元件136b係電性連接電性互連件134b，並且自電性互連件134b向上作延伸；連接元件136c及136d係電性連接電性互連件134c，並且自電性互連件134c向上作延伸。參照第1A圖和第1B圖，連接元件136a、136b、136c、及136d係以列的形式作分佈，其中每一列係沿著實質上為矩形圖案或為正方型圖案的四邊做延伸。此些列包括外部列和內部列，外部列包括連接元件136a和136d，而內部列包括連接元件136b和136c。在此實施例中，外部列的連接元件(如連接元件136a和136d)提供數個電性路徑，此些電性路徑位於封裝件100和另一在一堆疊封裝組裝件中之封裝件之間，而內部列的連接元件(如連接元件136b和136c)提供數個電性路徑，此些電性路徑位於封裝件100中，且位於半導體元件104和封裝件100的其他元件之間。然而，連接元件136a、136b、136c、及136d其中之一個或多個亦可結合跨封裝件(inter-package)和內封裝件(intra-package)電性路徑。藉由提供此些垂直延伸的電性路徑，連接元件136a、136b、136c、及136d可使此由導電層132所提供之重新分佈網路延伸為三維。據此，連接元件136a、136b、136c、及136d有助於半導體元件102和104在封裝件100中之堆疊，以及封裝件100和另一個(在堆疊封裝組裝件中之)封裝件間之堆疊，從而在一給定之腳位區域中實現出更高密度之半導體元件。雖然第1B圖繪示出兩列連接元件136a、136b、136c、及136d，然而在其他實施中，其中可以包含有更多或更少列的連接元件，且連接元件136a、136b、136c、及136d在一般情況下可以是任意一種一維圖案或二維圖案之分佈。
在此實施例中，連接元件136a、136b、136c、及136d係被作成伸長結構，更進一步的說，導電結構係被設置於其中，且至少部分填充其所形成之通孔，依照下述的製造操作。連接元件136a、136b、136c、及136d係由金屬、金屬合金、金屬或金屬合金分散於其中之材料、或另一合適的導電材料。舉例來說，連接元件136a、136b、136c、及136d中的至少一個由銅或銅合金所形成。如第1B圖所示，各連接元件136a、136b、136c、或136d的尺寸可以是依照連接元件136a、136b、136c、及136d之一高度HC (即是連接元件136a、136b、136c、或136d之垂直範圍)以及連接元件136a、136b、136c、或136d之寬度WC (即是連接元件136a、136b、136c、或136d之橫向範圍)來做明確指定。如果連接元件136a、136b、136c、及136d有一非均勻橫向範圍，舉例來說，該寬度WC 可依照一沿著一組直角方向的平均橫向範圍來指定。對一特殊的實施，每一連接元件136a、136b、136c、或136d的高度HC 可在大約100微米到700微米(μm)的範圍之間，例如大約150微米到650微米間，或200微米到600微米間，而連接元件136a、136b、136c、或136d的寬度WC 可在大約100微米到50微米的範圍之間，例如大約150微米到450微米間，或200微米到400微米間。
參照第1B圖，每一連接元件136a、136b、136c、或136d之上底端實質上對準半導體元件104的上表面112或與其為共平面，而每一連接元件136a、136b、136c、或136d之下底端係實質上對準半導體元件102的下表面106或與其為共平面。以另一種方式來說，每一連接元件136a、136b、136c、或136d之高度HC 實質上與半導體元件102和104之堆疊結構的垂直延伸總和相等。然而在其他實施中，連接元件136a、136b、136c、及136d的垂直範圍，以及連接元件136a、136b、136c、及136d與上表面112及下表面106的對準關係是可以有所變更的。如第1B圖所示，半導體元件104係通過一組焊線138銲線接合至連接元件136b和136c，此組焊線138將連接墊116a和116b分別電性連接至連接元件136b和136c的上底端(以及其他內部列連接元件)。焊線138係由金、銅、或其他合適的導電材料所形成。在一實例中，因為銅相較於金有更佳的導電性以及更低的成本，同時可允許焊線138以一減少的直徑來形成，故而焊線138中至少一個子集合係由銅所形成。焊線138可以一合適的金屬鍍膜來形成，如鈀，以保護不受氧化及外界環境影響。使用焊線接合係有益於幫助封裝件100的堆疊功能，包括不需形成另一重新分佈單元來提供電性路徑，即可於封裝件100內堆疊半導體元件102和104，所以可減少製造成本及時間。此外，使用焊線接合可以更容易地容納特定形式之半導體元件，如焊線接合特殊設計以用來焊線接合之晶片。
參照第1A圖和第1B圖，封裝件100包括一封裝體140，封裝體140設置鄰接於重新分佈單元118的上表面122。封裝體140連接重新分佈單元118，且實質上包覆或覆蓋半導體元件102和104、焊線138、以及連接元件136b和136c(及其他內部列連接元件)以提供結構剛性並且保護不受外界環境影響。此外，封裝體140延伸至重新分佈單元118的周邊，並且包覆或覆蓋連接元件136a和136d(及其他外部列連接元件)，至少部分暴露出連接元件136a和136d的上底端，以堆疊另一封裝件於封裝件100之上。
封裝體140係由封膠材料所形成，並且包括一中央上表面142、一外圍上表面144、以及側向表面146和148，側向表面146和148設置鄰接於封膠體140的周邊。在此實施例中，每一中央上表面142及外圍上表面144實質上為平面，且有實質上和重新分佈單元118之下表面120或上表面122平行之方向，然而在其他實施中，上表面142和144的形狀與方向可以有所變更。參照第1A圖和第1B圖，封裝體140於鄰接於封裝體140之一中央部分處有一較大的厚度，以實質上覆蓋半導體元件102和104、焊線138、以及連接元件136b和136c，而封裝體140於鄰接於封裝體140之外圍部分處有減少之厚度，以至少部分暴露出連接元件136a和136d，而連接元件136a和136d之上底端實質上和外圍上表面144對準或共平面。另外，封膠體140之中央厚度HP1 ，即垂直距離。此垂直距離係位於封膠體140之中央上表面142和重新分佈單元118之上表面122之間，此距離大於封膠體140之外圍厚度HP2 ，此厚度HP2 為一垂直距離。此垂直距離位於封膠體140之外圍上表面144和重新分佈單元118之上表面122之間，且實質上和各連接元件136a、136b、136c、或136d之高度HC 相同。更特別的，外圍厚度HP2 不大於中央厚度HP1 的9/10，例如約2/1到約9/10HP1 ，或者約2/3到約9/10HP1 。在一實例中，中央厚度HP1 可在約200微米到800微米的範圍之間，如約250微米到750微米或者約300微米到700微米，而外圍厚度HP2 可在約100微米到700微米的範圍之間，如約150微米到650微米或者約200微米到600微米。如圖所示之連接元件136a和136d之上底端為實質上對準外圍上表面144，連接元件136a和136d之上底端也可以向下凹或突出外圍上表面144。
參照第1A圖和第1B圖，封膠體140之側向表面146及148實質上係為平面，且和重新分佈單元118之下表面120或上表面122實質上有一直角方向，然而在其他實施中，側向表面146和148之形狀及方向可以有所變更。側向表面146及148實質上分別對準重新分佈單元118之側向表面124及126或者是共平面，使得側向表面146及148與側向表面124及126相連接，側向表面146及148定義出封裝件100之周邊。經由實行此表面對準操作可使得封膠體140有一側向範圍，此側向範圍實質上和重新分佈單元118的側向範圍相符，雖然此側向範圍在鄰接於封裝件100之周邊上會有一減少的厚度。對其他實施來說，第1A圖及第1B圖中所示之側向表面124、126、146、及148係可以有所變更的。
電性接觸件設置鄰接於封裝體140之外圍上表面144，包括電性接觸件150a及150b，電性接觸件150a及150b分別和連接元件136a及136d之上底端(及其他外部列連接元件)電性接觸且由連接元件136a及136d之上底端向上延伸。電性接觸件150a及150b當作預先焊接材料，用以堆疊另一封裝件於封裝件100之上，並且如同連接元件136a和136d，電性接觸件150a和150b以一列的形式沿著實質上為矩形圖案或實質上為方型圖案的四邊做延伸分佈。在實施例中，電性接觸件150a及150b係被形成作為焊接凸塊，且依照封裝件100之扇出結構，電性接觸件150a及150b係橫向分佈於半導體元件102或104之周圍外部，然而一般來說，電性接觸件150a及150b可以是橫向設置於周圍之內部、周圍之外部、或周圍之內外部。
接著請參照第2A圖和第2B圖，第2A圖和第2B圖係繪示出第1A圖和第1B圖之封裝件100之部分放大剖面圖，為簡單表示，故省略相關細節。且其中，第2A圖繪示一連接元件136b之一特殊實施，而第2B圖繪示另一連接元件136b之特殊實施。雖然下列特徵之描述係參照連接元件136b，然而這些特徵可以類似地應用於封裝件100之其他連接元件。
首先請參照第2A圖，連接元件136b係以固態伸長結構來做實施，且更特殊的是，例如是設置一導電柱或導電樁200於連接元件136b中，且實質上填充由封裝體140所定義出之通孔。導電柱200之上底端包括一連接表面，此連接表面和焊線138為電性連接。在製造中，此連接表面可由經過導電柱200之上底端至一組表面終止操作(surface finishing operation)而形成，此組表面終止操作產生一組組層以增強連接至焊線138的電性連接可靠度。以表面終止層包括那些以金為基底之例子，例如化學金、無電鍍鎳/化學金、以及非電鍍鎳/非電鍍鈀/化學金。
接著參照第2B圖，連接元件136b係以空心伸長結構來做實行，且更特殊的是，設置導電材料202於連接元件136b中，且部分填充由封裝體140定義出之通孔。參照第2B圖，用以形成封裝體140之封膠材料可填充部分之通孔，然而其他合適的填充材料也可以拿來使用。另外，通孔可以是至少部分為空心的。導電通道202之上底端有一較大之橫向範圍，且此橫向範圍係被用來實行成為一連接墊204，此連接墊204包含一連接表面，此連接表面係電性連接至焊線138。在製造中，此連接表面可以由通過接觸墊204至一組類似於第2A圖所述之表面終止操作而形成。
第3圖繪示依照本發明一實施例之堆疊封裝組裝件300之剖面圖，為簡單表示，故省略相關細節。其中，第3圖繪示組裝件300之特殊實施，此組裝件300係使用第1A圖到第2B圖之封裝件100所形成。
如第3圖所示，組裝件300包括一半導體封裝件302，此半導體封裝件302相當於一設置於封裝件100上之上封裝件，並且和相對於其下之封裝件100作電性連接。在此實施例中，封裝件302係以一球柵矩陣排列(ball grid array,BGA)封裝件來作實施，然而其他形式的封裝件也可拿來作使用，包括一接點柵格矩陣排列(land grid array,LGA)封裝件、一四方扁平無外引腳(quad flat no-lead,QFN)封裝件、一先進四方扁平無外引腳(advanced quad flat no-lead,aQFN)封裝件、以及其他形式的球柵矩陣排列封裝件，例如一窗型球柵矩陣排列封裝件。雖然第3圖繪示二個堆疊封裝件100和302，然而在其他實施中可包含有額外增加之封裝件。封裝件302之一特殊方面，可以用一和前述封裝件100類似的形式執行，故而不於此再作描述。
參照第3圖，封裝件302包括電性接觸件，電性接觸件包括電性接觸件304a和304b，電性接觸件304a和304b為封裝件302提供了輸入電性連接點和輸出電性連接點，且從封裝件302之一下表面向下延伸。在一實施例中，電性接觸件304a和304b係為焊接凸塊，且電性接觸件150a和150b亦為焊接凸塊，電性接觸件304a和304b係以一列狀分佈，且沿著一實質上為矩形圖案或為正方形圖案的四邊做延伸。在堆疊操作中，封裝件302之電性接觸件304a和304b係為回流的，並且金屬接線至封裝件100之電性接觸件150a和150b。其中，電性接觸件304a和304b和電性接觸件150a和150b的其中之一接合或融合，以提供封裝件100和302間的電性路徑。
第4A圖至第4H圖繪示依照本發明一實施例的一形成晶圓級半導體封裝件之製造流程。為簡單表示，下列製造操作係參照第1A圖至第2B圖之封裝件100作描述。然而，此製造操作可類似地執行以形成其他半導體封裝件。
首先請參照第4A圖，提供一載具400，多對半導體元件以一堆疊結構設置鄰接於載具400之上，包括半導體元件102和104。在此實施例中，半導體元件102和104係為一背對背堆疊結構，半導體元件104之主動表面112係面向載具400，而半導體元件102之主動表面106係背向載具400。
成對堆疊之半導體元件可以一陣列方式設置安排於載具400上，其中成對堆疊的半導體元件係以一二維形式作設置安排，或用一帶狀方式，其中成對堆疊之半導體元件係以一線性方式做連續設置安排。開始時，相對於鄰近的半導體元件，半導體元件102或104係被包含在一晶圓之一起始空間中，接著此晶圓經過切割製程，將半導體元件102或104和其相鄰之半導體元件分隔開。在此實施例中，相較於晶圓中之起始最近相鄰空間，安排設置成對堆疊之半導體元件，以得到相對於彼此之一最大的最近相鄰空間，如此有助於一完成封裝件的扇出結構。為簡單表示，下列製造操作主要對照半導體元件102和104及相關元件作描述，然而製造操作可以類似地執行於其他以平行方式或連續之成對堆疊半導體元件。
如第4B圖所示，施以一封膠材料402於載具400上，以覆蓋或包覆半導體元件102和104，而半導體元件102和104之主動表面106和112依然是至少部分暴露。由於半導體元件104之主動表面112係設置面向載具400，半導體元件104之周邊實質上係被封膠材料402所包覆，故而其主動表面112實質上不受封膠材料402包覆。藉由設置封膠盤或其他封膠結構，並使封膠盤或其他封膠結構鄰接於半導體元件102之主動表面106，半導體元件102之周邊實質上係被封膠材料402所包覆，半導體元件102之主動表面106實質上不受封膠材料402所包覆。
舉例來說，封膠材料402包括一酚醛基樹脂、一環氧基樹脂、一矽基樹脂、或其他適合的密封材料。合適的填充物可以包含在內，如粉末狀二氧化矽(SiO2 )。可以使用任意一種封膠技術來施加封膠材料402，例如壓縮封膠、射出成型封膠、或轉換封膠。一旦施以，封膠材料402即硬化或固化，例如降低溫度以使封膠材料402之熔點下降，因而形成封膠結構404。參照第4B圖，一完成之封膠結構404包括一前表面408，前表面408和半導體元件102之主動表面106為實質上地對準或共平面，且一和前表面408相對之背表面410和半導體元件104之主動表面112為實質上地對準或共平面。以另一方式說明，封膠結構404之厚度和堆疊之半導體元件102和104的垂直範圍總和實質上係為相同。封膠結構404沿著被覆蓋之半導體元件102和104，封膠結構404可以被視為是一重新組合晶圓。
接著請參照第4C圖，複數個通孔形成於封膠結構404之中，包括通孔406a、406b、406c、及406d，其以一外部列和一內部列之形式分佈，且環繞於半導體元件102和104周圍，每一列皆沿著實質上為矩形圖案或為正方形圖案之四邊作延伸。可以用任意一種方法形成通孔406a、406b、406c、及406d，例如化學蝕刻、雷射鑽孔、或機械鑽孔以形成開口。舉例來說，雷射鑽孔可以使用一綠光雷射、一紅外光雷射、一固態雷射、或一CO2 雷射來作實行，其應用係為一脈衝形式或連續波形式之一雷射光束。
在此實施例中，每一通孔406a、406b、406c、及406d有一側向邊界，其形狀為一圓柱狀，包括一實質上之圓剖面。然而，一般來說，406a、406b、406c、及406d之形狀可以是任意一種形狀，例如另一形式之圓柱狀，例如一橢圓柱狀、一方形柱狀、或一矩形柱狀、或一非柱狀，例如一圓錐、一漏斗狀、或另一錐狀。通孔406a,406b,406c,及406d之側向邊界也可以是曲線或粗糙紋理。
依然參照第4C圖，每一通孔406a、406b、406c、及406d係通過封膠結構404實質地全部厚度作垂直延伸，即實質上延伸一半導體元件102和104之主動表面106和112之間的垂直距離。然而，在其他實施方式中，通孔406a、406b、406c、及406d的垂直延伸可以有所改變。在雷射鑽孔的例子中，適當地選擇和控制雷射的操作參數，可控制通孔406a、406b、406c、及406d的尺寸大小和形狀。
接著，施加一導電材料418於通孔406a、406b、406c、及406d中，以至少部分填充通孔406a、406b、406c、及406d，從而形成第4D圖中所示之連接元件136a、136b、136c、及136d。導電材料418包括金屬、金屬合金、金屬或金屬合金分散於其中之材料、或其他合適的導電材料。舉例來說，導電材料418可以包括金屬，例如是銅，一焊接材料，例如是任意一種熔點位於約90℃到450℃範圍之間的易熔金屬合金，或者一導電附著物或糊狀物，例如是任意一種樹脂，此樹脂具有導電填充物散佈於其中。合適的焊接凸塊例子包括錫鉛合金、銅鋅合金、銅銀合金、錫銀銅合金、含鉍合金、含銦合金、及含銻合金，以及合適的附著物例子包括環氧基樹脂及具有銀填充物或碳填充物之矽基樹脂。可以任意一種方式施加導電材料418，例如無電電鍍沉積、電鍍沉積、或藉由使用一分配器施加導電材料418。
依然參照第4D圖，每一完成之連接元件136a、136b、136c、及136d包括一底端和一相對之底端，連接元件136a、136b、136c、及136d之底端和封膠結構404(且和半導體元件102之主動表面106)之前表面408為實質上地對準或共平面，連接元件136a、136b、136c、及136d之相對底端和封膠結構404(且和半導體元件104之主動表面112)之背表面410為實質上地對準或共平面。以另一方式說明，每一連接元件136a、136b、136c、及136d之高度HC 和封膠結構404之厚度實質上係相同。然而，在其他實施中，連接元件136a、136b、136c、及136d之垂直範圍以及其與表面408和410之對準可以有所變更。
接著形成一組重新分佈層，此組重新分佈層鄰接於封膠結構404之前表面408以及半導體元件102之主動表面106，因此形成第4E圖中之重新分佈單元118。重新分佈單元118包括一對介電層128和130、以及導電層132，至少部分之導電層132係被夾於介電層128及130之間形成三明治結構。使用任意一種鍍膜技術來施加一介電材料以形成每一介電層128和130，例如印刷、旋塗、或噴霧，接著圖案化，以形成合適大小之尺寸及位置上對準之開口。使用任意一種技術以類似地施加一導電材料，例如化學氣相沉積、無電電鍍沉積、電鍍沉積、印刷、旋塗、噴霧、濺鍍、或真空沉積，接著圖案化以形成導電層132。介電層128和130以及導電層132之圖案化可以任意一種方法實行，例如微影製程、化學蝕刻、雷射鑽孔、或機械鑽孔。當形成重新分佈單元118後，接著形成電性連接件12a,132b,132c,及132d，例如是施加一焊接材料並且回流及固化，使焊接材料形成焊接凸塊，並且容納於由介電層130定義出之開口中。
接著，沿著不同被覆蓋元件的封膠結構404自載具400上分隔開，並且再轉換至一直立方向，如第4F圖所示。半導體元件104接著通過焊線138，焊線接合至連接元件136b和136c(以及其他內部列連接元件)。可如前述一樣實行或連接一組表面終止操作，焊線接合可增強電性連接件之可靠性。如前所述，焊線接合的使用提供了電性路徑可允許半導體元件102和104之堆疊，而不需去形成另一重新分佈單元以鄰接至封膠結構404之背表面410以及半導體元件104之主動表面112。
如第4F圖和第4G圖所示，接著，選擇性地施加封膠材料412於一封膠結構404之中央部分，以實質上覆蓋或包覆半導體元件104之主動表面112、焊線138、以及連接元件136b和136c之上底端(以及其他內部列連接元件)。對照於第4B圖，封膠材料412和前述之封膠材料402可以是相同的或不同的，且可以任意一封膠技術施加，例如壓縮封膠、射出成型封膠、或轉換封膠。一旦施加，封膠材料412即硬化或固化，例如降低溫度以使封膠材料412之熔點下降，而形成封膠體140。
參照第4G圖，位於鄰接於封裝體140邊緣的地方，封裝體140有一減少之厚度，封裝體140鄰接於連接元件136a和136d上底端之處係為暴露的。封裝體140亦可藉由施加封膠材料412來形成，以得到一實質上均勻之厚度，之後接續一厚度縮減操作，例如化學蝕刻、雷射鑽孔、機械切割、鑽孔、佈線、或研磨、或其他移除技術以產生不同的厚度外型。
接著，如第4H圖所示，形成電性連接件150a和150b，且電性連接件150a和150b設置鄰接於連接元件136a和136d之上底端，例如施加一焊接材料並且回流和固化，使焊接材料形成焊接凸塊，從而形成封裝件100。依照此特殊實施，執行一系列之切割操作將封裝件100分隔為相鄰之封裝件。
本發明已參照較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。此外，在不脫本發明之範圍和精神下，為適應一特殊環境可針對材料、事件組成、方法、或製程上做更多的修改。所有的修改皆在本專利範圍所界定的範圍內。更特別的，於此所揭露之方法係參照一特殊之操作，在不脫離本發明之教導下，該些操作可以被合併、分開、或重新排列組合以形成一等同之方法。除了於此特別指出，該些組合與操作並非用以限定本發明。本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100．．．封裝件
102、104．．．半導體元件
106、110、120．．．下表面
108、112、122．．．上表面
114a、114b、116a、116b、204．．．接觸墊
118．．．重新分佈單元
124、126、146、148．．．側向表面
128、130．．．介電層
132．．．導電層
132a、132b、132c、132d、150a、150b、304a、304b．．．電性接觸件
134a、134b、134c．．．電性互連件
136a、136b、136c、136d．．．連接元件
138．．．焊線
140．．．封裝體
142．．．中央上表面
144．．．外圍上表面
200．．．導電柱
202．．．導電通道
300．．．堆疊封裝組裝件
302．．．半導體封裝件
400．．．載具
402、412．．．封膠材料
404．．．封膠結構
406a、406b、406c、406d．．．通孔
408．．．前表面
410．．．背表面
418．．．導電材料
HP1 ．．．中央厚度
HP2 ．．．外圍厚度
HC ．．．高度
WC ．．．寬度
第1A圖繪示依照本發明一較佳實施例的晶圓級半導體封裝件之示意圖。
第1B圖繪示一第1A圖中之線A-A之封裝件之剖面圖。
第2A～2B圖繪示於第1A圖及第1B圖中利用封裝形成之一拉長、堆疊封裝組裝件剖面圖。
第3圖繪示一於第1A圖及第1B圖中利用封裝形成之一堆疊封裝組裝件剖面圖。
第4A～4H圖繪示形成第1A圖及第1B圖中之封裝件的製造方法。
100．．．封裝件
102、104．．．半導體元件
106、110、120．．．下表面
108、112、122．．．上表面
114a、114b、116a、116b．．．接觸墊
118．．．重新分佈單元
124、126、146、148．．．側向表面
128、130．．．介電層
132．．．導電層
132a、132b、132c、132d、150a、150b．．．電性接觸件
134a、134b、134c．．．電性互連件
136a、136b、136c、136d．．．連接元件
138．．．焊線
140．．．封裝體
142．．．中央上表面
144．．．外圍上表面
HP1 ．．．中央厚度
HP2 ．．．外圍厚度
HC ．．．高度
WC ．．．寬度

Claims (20)

  1. 一種堆疊封裝組裝件，包括：一第一半導體封裝件包括：一重新分佈單元，包括一上表面；一組堆疊半導體元件，包括：(a)　一第一半導體元件，設置鄰接於該重新分佈單元，該第一半導體元件包括一第一主動表面，該第一主動表面係面對該重新分佈單元之該上表面：以及(b)　一第二半導體元件，設置鄰接於該第一半導體元件，該第二半導體元件包括一第二主動表面，該第二主動表面係背向該第一主動表面；一組連接元件，設置鄰接於該組堆疊半導體元件之一周圍，且各該組連接元件皆由該重新分佈單元之該上表面向上延伸，該組連接元件包括：(a)　一第一連接元件，包括一第一上底端；及(b)　一第二連接元件，包括一第二上底端，該第二上底端銲線接合至該第二半導體元件之該第二主動表面；以及一封裝體，設置鄰接於該重新分佈單元之該上表面，該封裝體包覆該組堆疊半導體元件及該組連接元件，該封裝體包括一中央上表面及一外圍上表面，該中央上表面係位於該第二半導體元件之該第二主動表面上，該第一連接元件之該第一上底端係暴露鄰接於該封裝體之該外圍上表面。
  2. 如申請專利範圍第1項所述之該堆疊封裝組裝件，其中該第二半導體元件之該第二主動表面實質上對準至少與該第一連接元件之該第一上底端及該第二連接元件之該第二上底端其中之一對準。
  3. 如申請專利範圍第2項所述之該堆疊封裝組裝件，其中該第二半導體元件之該第二主動表面實質上對準該封裝體之該外圍上表面。
  4. 如申請專利範圍第3項所述之該堆疊封裝組裝件，其中該第一連接元件之該第一上底端實質上對準該封裝體之該外圍上表面。
  5. 如申請專利範圍第1項所述之該堆疊封裝組裝件，其中該封裝體有一中央厚度HP1 和該中央上表面相對應，以及一外圍厚度HP2 和外圍上表面相對應，且該第一中央厚度HP1 係大於該外圍厚度HP2 。
  6. 如申請專利範圍第5項所述之該堆疊封裝組裝件，其中該外圍厚度HP2 係介於1/2該中央厚度HP1 到9/10該中央厚度HP1 的範圍之間。
  7. 如申請專利範圍第5項所述之該堆疊封裝組裝件，其中該第一連接元件及該第二連接元件其中之至少一者有一高度HC ，且該高度HC 實質上等同於該外圍厚度HP2 。
  8. 如申請專利範圍第1項所述之該堆疊封裝組裝件，其中該第一連接元件及該第二連接元件其中之至少一者對應至一固體連續延伸結構。
  9. 如申請專利範圍第1項所述之該堆疊封裝組裝件，其中該第一連接元件及該第二連接元件其中之至少一者對應至一中空延伸之結構。
  10. 如申請專利範圍第9項所述之該堆疊封裝組裝件，其中該第二連接元件之該第二上底端對應至一接觸墊，該接觸墊係銲線接合至該第二半導體元件之該第二主動表面。
  11. 如申請專利範圍第1項所述之該堆疊封裝組裝件，其中該重新分佈單元包括複數個側向表面，與該重新分佈單元之一周圍相鄰，該封裝體包括複數個側向表面與該封裝體之一周圍相鄰，該封裝體之該些側向表面實質上分別對準該重新分佈單元之該些側向表面。
  12. 如申請專利範圍第1項所述之該堆疊封裝組裝件，更包括：一第二半導體封裝件設置鄰接於該第一半導體封裝件之該封裝體，該第二半導體封裝件係電性連接於該第一連接元件之該第一上底端。
  13. 如申請專利範圍第12項所述之該堆疊封裝組裝件，其中該第二半導體封裝件係經由一組焊接凸塊電性連接至該第一連接元件之該第一上底端。
  14. 一製造方法，包括：提供一第一半導體元件及一第二半導體元件，該第一半導體元件包括一第一主動表面，該第二半導體元件包括一第二主動表面；堆疊該第一半導體元件及該第二半導體元件，使得該第一主動表面及該第二主動表面彼此為背向；施加一第一封膠材料以形成一封膠結構，覆蓋該第一半導體元件之邊緣及該第二半導體元件之邊緣，該封膠結構包括一前表面及一相對之背表面，該第一半導體元件之該第一主動表面係至少部分暴露鄰接於該封膠結構之該前表面，該第二半導體元件之該第二主動表面係至少部分暴露鄰接於該封膠結構之該背表面；形成一組通孔，從該組通孔於該封膠結構之該前表面延伸至該封膠結構之該背表面，並圍繞該第一半導體元件及該第二半導體元件；施加一導電材料至該組通孔，以形成一組連接元件；形成一重新分佈單元鄰接該第一半導體元件之該第一主動表面及該封膠結構之該前表面；通過一組焊線，電性連接該第二半導體元件之該第二主動表面至該組連接元件中的至少其中之一；以及施加一第二封膠材料，該第二封膠材料鄰接於該第二半導體元件之該第二主動表面及該封膠結構之該背表面，以形成一封裝體，該封裝體包括一中央部分及一外圍部分，該中央部分有一中央厚度HP1 ，並覆蓋該第二半導體元件之該第二主動表面及該組焊線，該外圍部分有一外圍厚度HP2 ，以使該組連接元件中之至少一個連接元件之一底端部分暴露。
  15. 如申請專利範圍第14項所述之該製造方法，其中係使用雷射鑽孔以形成該組通孔。
  16. 如申請專利範圍第14項所述之該製造方法，其中係經由形成該組通孔之步驟來形成一第一組通孔及一第二組通孔，該第一組通孔分佈於一外部列上，該外部列環繞該第一半導體元件及該第二半導體元件，該第二組通孔分佈於一內部列上，該內部列環繞該第一半導體元件及該第二半導體元件。
  17. 如申請專利範圍第14項所述之該製造方法，其中至少使用一化學電鍍及一電解電鍍其中至少一者，以施加該導電材料。
  18. 如申請專利範圍第14項所述之該製造方法，其中提供一焊料及一導電黏著劑其中至少一者，以施加該導電材料。
  19. 如申請專利範圍第14項所述之該製造方法，其中中央厚度HP1 係大於外圍厚度HP2 。
  20. 如申請專利範圍第14項所述之該製造方法，其中外圍厚度HP2 係介於2/3中央厚度HP1 到9/10中央厚度HP1 的範圍之間。
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