CN101454882B - 具有集成肖特基二极管的高密度沟槽fet及制造方法 - Google Patents

具有集成肖特基二极管的高密度沟槽fet及制造方法 Download PDF

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CN101454882B
CN101454882B CN2007800190574A CN200780019057A CN101454882B CN 101454882 B CN101454882 B CN 101454882B CN 2007800190574 A CN2007800190574 A CN 2007800190574A CN 200780019057 A CN200780019057 A CN 200780019057A CN 101454882 B CN101454882 B CN 101454882B
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保尔·托鲁普
阿肖克·沙拉
布鲁斯·道格拉斯·马钱特
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Abstract

本发明提供了一种单块集成的沟槽FET及肖特基二极管,其包括终止于第一导电型的第一硅区中的一对沟槽。由第一导电型的第二硅区隔开的第二导电型的两个本体区位于这对沟槽之间。第一导电型的源极区位于每个本体区上方。接触开口在这对沟槽之间延伸至该源极区下方一定深度。互连层填充了该接触开口,从而电接触源极区及第二硅区。在互连层电接触第二硅区的地方形成了肖特基接触。

Description

具有集成肖特基二极管的高密度沟槽FET及制造方法
相关申请交叉参考
本申请涉及2004年12月29日提交的第11/026,276号共同转让的美国申请,其全部公开内容结合于此作为参考。
技术领域
本发明大体上涉及半导体功率器件技术,且具体地涉及用于形成单块集成的沟槽栅极场效应晶体管(FET)及肖特基二极管的结构及方法。
背景技术
在当今的电子器件中,经常可以发现使用多重供电的领域。例如,在一些应用中,中央处理单元被设计成在特定时刻依据计算负载而具有不同供给电压的方式来工作。因此,直流/直流变流器在电子工业中激增,以满足电路的宽范围供电需求。普通直流/直流变流器采用典型地通过功率MOSFET(金属氧化物半导体场效应晶体管)实现的高效开关。该电源开关受控制,以利用诸如脉宽调制(PWM)方法将调节后的能量总量传递至负载。
图1示出了传统直流/直流变流器的电路示意图。PWM控制器100驱动功率MOSFET对Q1及Q2的栅极端子,以便对将电荷传递至负载进行调节。MOSFET开关Q2作为同步整流器用在电路中。为了避免急通(shoot-through)电流,在其中一个开关接通之前,两个开关必须同时断开。在该“死时间”(dead time)期间,每个MOSFET开关的内部二极管(通常被称为主体二极管)能够传导电流。不利地,该主体二极管具有相对高的正向电压并且能量被消耗。为了提高电路的转换效率,通常从外部添加肖特基二极管102使之与MOSFET(Q2)主体二极管并联。由于肖特基二极管具有比主体二极管低的正向电压,故肖特基二极管102有效地替代了MOSFET主体二极管。肖特基二极管的较低正向电压实现了改善的功耗。
多年来,肖特基二极管在MOSFET开关包装之外被实施。新近,一些制造商已提出将分离的肖特基二极管与分离的功率MOSFET器件共同封装的产品。还存在将功率MOSFET与肖特基二极管形成整体的实施方式。图2中示出了传统的单块集成的沟槽MOSFET及肖特基二极管的实例。肖特基二极管210形成在两个沟槽200-3与200-4之间,这两个沟槽在任一侧上被沟槽MOSFET单元围绕。N-型衬底202形成肖特基二极管210的阴极端子以及沟槽MOSFET的漏极端子。导电层218提供了二极管阳极端子并且也作为用于MOSFET单元的源极互连层。沟槽200-1、200-2、200-3、200-4及200-5中的栅电极在第三维度上连接到一起,因此被类似地驱动。沟槽MOSFET单元还包括本体区208,该本体区中具有源极区212和重本体区(heavy body region)214。
图2中的肖特基二极管介于沟槽MOSFET单元之间。因此,肖特基二极管消耗掉活性区域的绝大部分,这导致更低的电流速率或大的管芯(die)尺寸。因此,需要具有良好性能特性的单块且密集集成的肖特基二极管及沟槽栅FET。
发明内容
根据本发明的实施例,单块集成的沟槽FET及肖特基二极管包括终止于第一导电型(conductivity type)的第一硅区中的一对沟槽。由第一导电型的第二硅区隔开的第二导电型的两个本体区位于这对沟槽之间。第一导电型的源极区位于每个本体区上方。接触开口在这对沟槽之间延伸至该源极区下方一定深度。互连层填充了该接触开口,从而电接触源极区及第二硅区。在互连层电接触第二硅区的地方形成了肖特基接触。
在一个实施例中,该第一硅区具有比第二硅区高的掺杂浓度。
在另一实施例中,每个本体区在相应的源极区与第一硅区之间垂直地延伸,并且互连层沿本体区的下半部在一定深度处电接触第二硅区。
在另一实施例中,两个本体区中的每个均具有基本均匀的掺杂浓度。
在另一实施例中,在这对沟槽之间形成有第二导电型的重本体区,从而重本体区电接触两个本体区中的每个和第二硅区。
在另一实施例中,两个本体区、源极区、以及重本体区均与这对沟槽自动对准。
在另一实施例中,两个本体区及第二硅区具有基本相同的深度。
根据本发明的另一实施例,形成单块集成的沟槽FET及肖特基二极管的过程如下所述。形成延伸穿过上硅层且终止于下硅层中的两个沟槽。该上硅层及下硅层为第一导电型,且上硅层在下硅层上延伸。在上硅层中且在这对沟槽之间形成第二导电型的第一及第二硅区。形成第一导电型的第三硅区,该第三硅区在这对沟槽之间延伸到第一及第二硅区中,从而使第一及第二硅区的剩余下部形成两个本体区,这两个本体区被上硅层的一部分隔开。进行硅蚀刻,以形成延伸穿过第一硅区的接触开口,从而保留第一硅区的外部。第一硅区的外部形成源极区。形成填充接触开口的互连层,从而电接触源极区及上硅层的一部分。在互连层电接触第二硅区的地方形成肖特基接触。
在一个实施例中,下硅层具有比上硅层高的掺杂浓度。
在另一实施例中,互连层与上硅层的一部分之间的电接触在源极区下方一定深度处形成。
在另一实施例中,第一及第二区中的每个均具有基本均匀的掺杂浓度。
在另一实施例中,在这对沟槽之间形成有第二导电型的重本体区。该重本体区在两个本体区中且在上硅层的一部分中延伸。
在又一实施例中,两个本体区、源极区、以及重本体区均与这对沟槽自动对准。
参照说明书的剩余部分及附图可以实现对在此所公开的本发明的特性及优点的进一步理解。
附图说明
图1是关于采用具有肖特基二极管的功率MOSFET的传统直流/直流变流器的电路示意图;
图2示出了传统的单块集成的沟槽MOSFET及肖特基二极管的横截面图;
图3是长条状单元阵列的一部分的示例性简化等视轴图,每个长条状单元中均集成有根据本发明实施例的沟槽MOSFET及肖特基二极管;
图4示出了沿图3中的重本体区326的横截面图;
图5是示出了根据本发明实施例的、图3及图4中所示重本体区的可替换实施方式的简化横截面图;
图6A-图6F是示出了根据本发明实施例的、用于形成图3中所示的单块集成的沟槽MOSFET及肖特基二极管的示例性处理步骤的简化横截面图;
图7A-图7F示出了对于单块集成式沟槽MOSFET及肖特基二极管结构中的三种不同微坑(dimple)深度的模拟雪崩电流线。
具体实施方式
根据本发明的实施例,肖特基二极管最好与沟槽MOSFET集成在单个单元中,在这种单元阵列中重复多次。小到没有活性区域用于集成肖特基二极管,然而总的肖特基二极管区域大到足以处理100%的二极管正向传导。因此,MOSFET本体二极管从未接通,这消除了反向恢复损耗。此外,由于相比较于MOSFET本体二极管的正向压降,肖特基二极管具有较低的正向压降,故降低了功耗。
此外,肖特基二极管与MOSFET集成,从而在MOSFET源极区下方形成肖特基接触。这有利地远离源极区朝向肖特基区转移雪崩电流,故阻止了寄生双极晶体管接通。因此,改进了该器件的耐用性。本发明的该特征还在极大程度上消除了对重本体区的需求,典型地,在现有技术结构的每个MOSFET单元中需要该重本体区来阻止寄生双极晶体管接通。替代地,重本体区的岛(island)间歇地且彼此相隔很远地结合,仅仅为了确保源极金属与本体区的良好接触。实质上,现有技术沟槽MOSFET中所需的重本体区大多被肖特基二极管替代。因此,没有额外的硅区分配给肖特基二极管。
图3是长条状单元阵列的一部分的示例性简化等视轴图,每个长条状单元中均集成有根据本发明实施例的沟槽MOSFET及肖特基二极管。重掺杂N-型(N+)区302覆在N-型硅衬底(未示出)上面,该N-型硅衬底具有比N+区302甚至更高的掺杂浓度(N++)。多个沟槽304延伸至N+区302内的预定深度。在每个沟槽304中嵌入有保护电极305和上覆的栅电极308。在一个实施例中,保护电极305和栅电极308包含多晶硅。极间绝缘体310使栅电极与保护电极彼此绝缘。每个沟槽304的下侧壁及底部填充有保护绝缘层312,并且使保护电极305与周围的N+区302绝缘。沟槽304的上侧壁填充有比保护绝缘层312薄的栅极绝缘层316。每个栅电极308上方延伸有绝缘盖314。在一个实施例中,保护电极305沿第三维度电连接至源极区,因此在工作期间被偏压至与源极区相同的电势。在另一实施例中,保护电极305沿第三维度电连接至栅电极308,或者被允许浮动。
在每两个相邻的沟槽304之间设置有由轻掺杂N-型(N-)区320隔开的两个P-型本体区318。每个本体区318沿一个沟槽侧壁延伸。在图中所示且在此所述的各实施例中,本体区318及N-区320具有基本相同的深度,然而,在对该器件的工作不产生任何明显影响的前提下,本体区318可以略浅于或深于N-区320,反之亦然。每个本体区318上直接设置有重掺杂N-型源极区322。源极区322与栅电极308垂直相交,并且由于形成接触开口的微坑324的存在而具有圆形的外轮廓。每个微坑324在相应的每两个相邻沟槽之间的源极区322下方延伸。如所示的,源极区322及本体区318一起形成微坑324的圆形侧壁,并且N-区320沿微坑324的底部延伸。在一个实施例中,N+区302是N+外延层,而N-区320是其中形成有本体区318及源极区322的N-外延层的一部分。当MOSFET300接通时,在每个本体区318中且在每个源极区322与重掺杂区302之间沿沟槽侧壁形成有垂直的通道。
回到图3,被剥落以露出下面的区的肖特基隔离金属330填充微坑324且在绝缘盖314上方延伸。肖特基隔离金属330沿微坑324的底部电接触N-区320,进而形成肖特基接触。肖特基隔离金属330还用作顶面的源极互连,以便源极区322与重本体区326电连接。
在反向偏压期间,形成在每个本体/N-接合处的耗尽区有利地合并到N-区320中,进而完全耗尽肖特基接触下方的N-区320。这消除了肖特基泄漏电流,这又允许使用具有较低逸出功的隔离金属。因此,对于肖特基二极管,获得了甚至更低的正向电压。
沿单元长条间歇地形成有重本体区326的岛,如所示的。重本体区326穿过N-区320延伸。这更清楚地在图4中示出,图4是穿过图3中结构的重本体区326的横截面图。图4中的横截面图大多类似于沿图3中的等视轴图的正面的截面图,除了在图4中每两个相邻沟槽之间的两个源极区由穿过N-区320延伸的一个邻近重本体区326替代之外。重本体区326在源极金属330与本体区318之间提供了欧姆接触。由于重本体区326延伸穿过N-区320,故在这些区中没有形成肖特基二极管。由于不存在源极区,故在这些区中也没有MOSFET电流流过。
图5是示出了根据本发明另一实施例的、图3及图4中的重本体区的可替换实施方式的简化横截面图。在图5中,重本体区526仅沿每个微坑524的底部延伸,从而使源极区522保持完整。因此,MOSFET电流在这些区中流过,但重本体区526阻止了肖特基隔离金属430接触N-区310,进而在这些区中没有形成肖特基二极管。
回来参照图3,重本体区326的间歇设置与如现有技术图2的结构的、其中重本体区在两个相邻源极区之间且沿单元长条的整个长度延伸的传统实施方式不同。由于是肖特基二极管与沟槽MOSFET集成的方式,故在图3的结构中无需连续的重本体区。如在图3中可以看到的,通过使微坑324在源极区322下方适当地延伸,肖特基接触类似地在源极区322下方适当地形成。如以下进一步结合图7A-图7C更充分地描述的,当肖特基接触被置于源极区322下方适当位置时,则雪崩电流远离源极区322转向肖特基区,进而阻止了寄生双极晶体管接通。这消除了对现有技术结构中通常所需的沿单元长条的连续重本体区的需求。替代地,重本体区326的岛沿单元长条间歇地且彼此相隔很远地结合,以确保源极金属330与本体区318的良好接触。当连续的重本体区大多由肖特基区替代时,无需为肖特基二极管分配额外的硅区。因此,没有硅区用于集成肖特基二极管。
在一些实施例中,由器件开关需求(switching requirement)来控制沿长条设置重本体区326的频率。为了更快地开关器件,沿长条更频繁地设置重本体区。对于这些器件,可能需要为肖特基二极管分配额外的硅区(例如,通过增大单元间距)。为了更慢地开关器件,沿长条需要较少的重本体区。对于这些器件,在长条的每端设置一个重本体区可能就足够了,因此使肖特基二极管区最大化。
图6A-图6F是示出了根据本发明实施例的、用于形成图3中的集成式MOSFET-肖特基结构的示例性处理步骤的简化横截面图。在图6A中,利用传统技术在硅衬底(未示出)上方形成两个外延层602及620。外延层620(轻掺杂N-型层(N-))在外延层620(重掺杂N-型层(N+))上方延伸。形成、图案化并蚀刻硬掩模,以在N-外延层620上形成硬掩模岛601。因此,N-外延层620的表面积通过由硬掩模岛601限定的开口606露出。在一个实施例中,限定沟槽宽度的每个开口606是约0.3μm,而每个硬掩模岛601的宽度在0.4-0.8μm的范围内。这些尺寸限定了其中形成有MOSFET及肖特基二极管的单元间距。影响这些尺寸的因素包括光刻设备的能力和设计及性能目标。
在图6B中,利用传统的硅蚀刻技术穿过开口606蚀刻硅而形成终止于N-外延层620内的沟槽603。在一个实施例中,沟槽603具有的深度约为1μm。此后,利用传统的有选择外延生长(SEG)处理在每个沟槽603内产生高掺杂P-型(P+)硅区618A。在一个实施例中,P+硅区618A具有的掺杂浓度约为5×1017cm-3。在另一实施例中,在形成P+区618之前,形成填充沟槽608的侧壁及底部的高质量薄硅层。该薄硅层用作适于P+硅生成的无损的硅表面。
在图6C中,进行扩散处理,以使P-型掺杂剂扩散到N-外延层620内的P+区618A中。因此,形成在硬掩模岛601下方横向地延伸且向下到N-外延层620内的外扩的P+区618B。可以执行多个热循环以实现期望的向外扩散。图6C中的虚线示出了沟槽603的轮廓。该扩散处理以及该处理中的其他热循环使得N+外延层602向上扩散。对于选择N-外延层620的厚度,需考虑N+外延层602的这些向上扩散。
在图6D中,利用硬掩模岛601进行深沟槽蚀刻处理以形成沟槽604,该沟槽延伸穿过P+区618B及N-外延层620并终止于N+外延层602。在一个实施例中,沟槽604具有的深度约为2μm。沟槽蚀刻处理穿过并去除每个P+硅区618B的中心部分,留下沿沟槽侧壁延伸的垂直的外P+长条618C。
在本发明的另一实施例中,利用双道(two-pass)成角度注入而不是图6B-图6D中所示的有选择外延生长技术来形成P+长条618C,如下所述。在图6B中,在穿过掩模开口606形成沟槽603之后,利用传统的双道成角度注入技术将P-型掺杂剂(诸如硼)注入到相对的沟槽侧壁中。硬掩模岛604在注入处理期间用作阻挡结构,以阻止注入离子进入台面(mesa)区并将注入的离子的位置限制在N+外延层620中期望的区域。为了得到图6D中所示的结构,在双道成角度注入之后,进行第二沟槽蚀刻,以使沟槽603的深度延伸到N+外延层602中。在可替换实施例中,仅进行如下的一个沟槽蚀刻(而不是两个)。在图6B中,利用硬掩模岛601进行蚀刻,以形成延伸到N+外延层602中大约与图6D中的沟槽604相同深度的沟槽。此后,进行双道成角度注入,以将P-型掺杂剂注入到相对的沟槽侧壁中。调节注入角及硬掩模岛601的厚度,以限定接收注入离子的上沟槽侧壁区。
在图6E中,利用已知技术在沟槽604中形成保护栅极结构。形成填充沟槽604的下侧壁及底部的保护绝缘体612。此后,形成填充沟槽604的下部的保护电极605。此后,在保护电极605上形成电极间绝缘层610。此后,形成填充上沟槽侧壁的栅极绝缘体616。在一个实施例中,在该处理的较早阶段中形成栅极绝缘体616。绝缘盖区614在栅电极608上延伸并填充沟槽604的剩余部分。
接着,将N-型掺杂剂注入到所有外露的硅区中并紧接着执行处理中的驱动(drive),进而形成N+区622A。在形成N+区622A时在活性区中没有使用掩模。如图6E中所示,与形成保护栅极结构及N+区622A有关的各种热循环使得P-型区618C向外扩散,进而形成较宽且较高的本体区618D。如上面所指出的,这些热循环还使得N+外延层602向上扩散,如图6E中所示。确保在完成制造处理时每两个相邻沟槽之间的两个本体区保持隔开且没有合并是非常重要的,否则肖特基二极管被切断。设计本处理时的另一目标是确保在完成该处理之后N-外延层620与本体区618D具有基本相同的深度,尽管略微不同的深度不会对本器件的工作产生严重的影响。可以通过调整多个处理步骤及参数,包括热循环、第一沟槽凹陷处(图6B)的深度、以及各区(包括本体区、N-外延层区及N+外延层区)的掺杂浓度来实现这些目标。
在图6F中,在活性区中没有使用掩模的情况下进行微坑蚀刻处理,以穿过N+区622A蚀刻,从而保留N+区622A的外部622B。保留的外部622A形成源极区。因此,在每两个相邻的沟槽之间形成微坑624。微坑624形成了在源极区622B下方延伸至N-区620中的接触开口。本公开中所使用的“微坑蚀刻”是指导致形成如图6F中的源极区622B的具有倾斜的、圆形外轮廓的硅区的硅蚀刻技术。在一个实施例中,微坑延伸至本体区618D的下半部内的一定深度。如前所述,较深的微坑导致在源极区下方形成肖特基接触。这有助于使反向雪崩电流远离源极,进而阻止了寄生双极晶体管接通。尽管上述微坑蚀刻在活性区中无需掩模,但在可替换实施例中使用掩模来限定N+区622A的中心部分,该中心部分被蚀刻至期望深度。因此,保留了在这一掩模下延伸的N+区622A的外部。这些外部形成源极区。
利用掩模层,沿每个长条将P-型掺杂剂间歇地注入到微坑区中。因此,在每两个相邻的沟槽之间形成重本体区的岛(未示出)。如果期望实现图4中的重本体区,在重本体注入期间需要使用足够高剂量的P-型掺杂剂,以便反掺杂(count-dope)源极区的待形成重本体区的那些部分。如果期望实现图5中的重本体区,在注入期间需要使用较低剂量的P-型掺杂剂,从而使源极区不被反掺杂,进而保持完整。
在图6F中,可以使用传统技术在该结构上形成肖特基隔离金属630。肖特基隔离金属630填充微坑624,并且在金属630与N-区620电接触的地方形成肖特基二极管。金属层630还接触源极区622B及重本体区。
在图6A-图6F所示的处理步骤中,临界对准无需使用这两个掩模。因此,集成的MOSFET-肖特基结构具有许多垂直及水平的自对准特征。此外,上述处理的实施例使得通道长度减小。传统处理利用注入及驱动技术来形成本体区。该技术导致通道区的锥形掺杂轮廓,这要求较长的通道长度。相反地,上述用于形成本体区的有选择外延生长及双道成角度注入的可替换技术在通道区中提供了一致掺杂轮廓,进而允许使用较短的通道长度。因此,提高了器件的导通电阻。
此外,使用双外延层结构来提供了在保持对MOSFET阈电压(Vth)的严密控制的同时使击穿电压及导通电阻最优化的设计灵活性。通过在N-外延层618中形成本体区618来实现对Vth的严密控制,与N+外延层602相比,该N-外延层618表现出更一致且可断定(predictable)的掺杂浓度。在具有可断定的掺杂浓度的背景区(background region)中形成本体区允许对阈电压的更严密控制。另一方面,对于相同的击穿电压,延伸到N+外延层602中的保护电极605允许在N+外延层602中使用较高的掺杂浓度。因此,对于相同的击穿电压,获得了较低的导通电阻,并且不会对MOSFET阈电压的控制产生不利影响。
图7A-图7F示出了对于集成的沟槽MOSFET-肖特基二极管结构中的三种不同微坑深度的模拟雪崩电流线。在图7A的结构中,微坑729A延伸至源极区722下方仅一定深度。在图7B的结构中,微坑729B更深地延伸至约本体区718高度的一半。在图7C的结构中,微坑729C甚至更深地延伸至恰好位于本体区718的底部上方。在图7A-图7C中,在顶部金属730中出现间隙。包括该间隙仅用于模拟的目的,而事实上,在顶部金属中不存在这一间隙,这从本公开的其他附图中是显而易见的。
如在图7A中所看出的,雪崩电流线732A紧邻源极区722。然而,由于在图7B中微坑深度增加且在图7C中甚至更深,雪崩电流线732B及732C进一步远离源极区722朝向肖特基区移动。远离源极区转移雪崩电流有助于阻止寄生双极晶体管接通,进而提高了器件的耐用性。本质上,肖特基区的作用就像聚集雪崩电流的重本体区,进而消除了对用于目的的重本体区的需求。仍会需要重本体区来获得与本体区的良好接触,但与传统的MOSFET结构相比,该重本体区的频率及尺寸可显著减小。这释放了分配给肖特基区二极管的较大硅区。因此,对于图7A-图7C中的示例性模拟结构,延伸至本体区718的下半部内的一定深度的微坑提供了最佳结果。
尽管已利用保护栅极沟槽MOSFET实施例描述了本发明,但对于本领域技术人员而言,鉴于本公开,以其他保护栅极MOSFET结构和具有较厚底部绝缘体的沟槽栅极MOSFET以及其他类型的功率器件来实现本发明将是显而易见的。例如,上述用于集成肖特基二极管与MOSFET的技术可以类似地实施到以上所参考的2004年12月29日提交的美国专利申请第11/026,276号中所公开的各功率器件中,具体地,实施到例如图1、图2A、图3A、图3B、图4A、图4C、图5C、图9B、图9C、图10-图12、及图24中所示的沟槽栅极、保护栅极、及电荷平衡器件中。
尽管以上示出并描述了多个特定实施例,但本发明的实施例并不限于此。例如,尽管利用开放式单元结构描述了本发明的一些实施例,但对于本领域技术人员而言,鉴于本公开,利用各种几何形状(诸如多边形、圆形、及矩形)的封闭式单元结构来实现本发明将是显而易见的。此外,尽管利用n-通道器件描述了本发明的实施例,但可以颠倒这些实施例中的硅区的导电型以获得p-通道器件。因此,本发明的范围不应参照以上说明书来确定,而是参照所附权利要求及其等效物的全部范围来确定。

Claims (45)

1.一种包括单块集成的沟槽FET及肖特基二极管的结构,所述单块集成的沟槽FET及肖特基二极管包括:
终止于第一导电型的第一硅区中的一对沟槽;
所述这对沟槽之间的第二导电型的两个本体区,所述两个本体区由所述第一导电型的第二硅区隔开;
每个本体区上的第一导电型的源极区;
在所述这对沟槽之间延伸至所述源极区下方一定深度的接触开口;以及
填充所述接触开口的互连层,从而电接触所述源极区及所述第二硅区,所述互连层与所述第二硅区形成肖特基接触。
2.根据权利要求1所述的结构,其中,所述第一硅区具有比所述第二硅区高的掺杂浓度。
3.根据权利要求1所述的结构,其中,每个本体区在相应的源极区与所述第一硅区之间垂直地延伸,并且所述互连层沿所述本体区的下半部在一定深度处电接触所述第二硅区。
4.根据权利要求1所述的结构,其中,所述两个本体区中的每个均具有基本均匀的掺杂浓度。
5.根据权利要求1所述的结构,其中,所述第一硅区是第一外延层,并且所述第二硅区是第二外延层,所述第一外延层在第一导电型的衬底上延伸,所述衬底具有比所述第一外延层高的掺杂浓度,并且所述第一外延层具有比所述第二外延层高的掺杂浓度。
6.根据权利要求1所述的结构,其中,所述两个本体区和相应的源极区均与所述这对沟槽自动对准。
7.根据权利要求1所述的结构,还包括形成在所述这对沟槽之间的第二导电型的重本体区,从而所述重本体区电接触所述两个本体区中的每个和所述第二硅区,所述重本体区具有比所述两个本体区高的掺杂浓度。
8.根据权利要求7所述的结构,其中,所述两个本体区、所述源极区、及所述重本体区均与所述这对沟槽自动对准。
9.根据权利要求1所述的结构,其中,所述两个本体区及所述第二硅区具有基本相同的深度。
10.根据权利要求1所述的结构,还包括:
每个沟槽中凹入的栅电极;以及
使每个栅电极与所述互连层绝缘的绝缘盖。
11.根据权利要求10所述的结构,还包括:
在每个沟槽中所述凹入的栅电极下方的保护电极;以及
使所述保护电极与所述第一硅区绝缘的保护绝缘体。
12.根据权利要求10所述的结构,还包括:
直接位于所述凹入的栅电极下方、沿每个沟槽的底部延伸的厚底部绝缘体。
13.根据权利要求1所述的结构,还包括直流/直流同步反向变流器,其中所述单块集成的沟槽FET及肖特基二极管作为低压侧开关接合至负载。
14.根据权利要求1所述的结构,其中,所述互连层是肖特基隔离金属层。
15.一种包括单块集成的沟槽MOSFET及肖特基二极管的结构,所述单块集成的沟槽MOSFET及肖特基二极管包括:
第一导电型的第一外延层;
所述第一外延层上方的第一导电型的第二外延层,所述第一外延层具有比所述第二外延层高的掺杂浓度;
穿过所述第二外延层延伸并且终止于所述第一外延层中的多个沟槽;
每两个相邻沟槽之间的第二导电型的两个本体区,所述两个本体区由所述第二外延层的一部分隔开;
每个本体区上方的第一导电型的源极区;
在每两个相邻沟槽之间延伸至所述源极区下方一定深度的接触开口;以及
填充所述接触开口的肖特基隔离金属层,从而电接触所述源极区和所述第二外延层的所述部分,所述肖特基隔离金属层与所述第二外延层的一部分形成肖特基接触。
16.根据权利要求15所述的结构,其中,每个本体区在相应的源极区与所述第一外延层之间垂直地延伸,并且所述肖特基隔离金属层沿所述本体区的下半部在一定深度处电接触所述第二外延层的所述部分。
17.根据权利要求15所述的结构,其中,所述两个本体区中的每个均具有基本均匀的掺杂浓度。
18.根据权利要求15所述的结构,其中,所述第一外延层在第一导电型的衬底上延伸,所述衬底具有比所述第一外延层高的掺杂浓度。
19.根据权利要求15所述的结构,其中,所述两个本体区和所述相应的源极区均与所述两个相邻沟槽自动对准,所述两个本体区和所述相应源极区位于所述两个相邻沟槽之间。
20.根据权利要求15所述的结构,还包括形成在每两个相邻沟槽之间的第二导电型的多个重本体区,从而使每个重本体区电接触位于所述两个相邻沟槽之间的所述两个本体区和所述第二外延层的所述部分。
21.根据权利要求20所述的结构,其中,所述两个本体区、所述对应源极区、以及所述多个重本体区均与所述两个相邻沟槽自动对准,所述两个本体区、所述对应源极区、以及所述多个重本体区位于所述两个相邻沟槽之间。
22.根据权利要求15所述的结构,其中,所述两个本体区和所述第二外延层具有基本相同的深度。
23.根据权利要求15所述的结构,还包括:
每个沟槽中的凹入的栅电极;以及
使每个栅电极与所述肖特基隔离金属层绝缘的绝缘盖。
24.根据权利要求23所述的结构,还包括:
在每个沟槽中所述凹入的栅电极下方的保护电极;以及
使所述保护电极与所述第一外延层绝缘的保护绝缘体。
25.根据权利要求23所述的结构,还包括:
直接位于所述凹入的栅电极下方、沿每个沟槽的底部延伸的厚底部绝缘体。
26.根据权利要求15所述的结构,还包括直流/直流同步反向变流器,其中所述单块集成的沟槽MOSFET及肖特基二极管作为低压侧开关接合至负载。
27.一种形成单块集成的沟槽FET及肖特基二极管的方法,所述方法包括:
形成延伸穿过上硅层且终止于下硅层中的一对沟槽,所述上硅层及所述下硅层为第一导电型,所述上硅层在所述下硅层上延伸;
在所述上硅层中且在所述这对沟槽之间形成第二导电型的第一及第二硅区;
形成第一导电型的第三硅区,所述第三硅区在所述这对沟槽之间延伸到所述第一及第二硅区中,从而使所述第一及第二硅区的剩余下部形成两个本体区,所述两个本体区被所述上硅层的一部分隔开;
进行硅蚀刻,以形成延伸穿过所述第三硅区的接触开口,从而保留所述第三硅区的外部,所述第三硅区的外部形成源极区;以及
形成填充所述接触开口的互连层,从而电接触所述源极区及所述上硅层的所述部分,所述互连层与所述上硅层的所述部分形成肖特基接触。
28.根据权利要求27所述的方法,其中,所述下硅层具有比所述上硅层高的掺杂浓度。
29.根据权利要求27所述的方法,其中,所述互连层与所述上硅层的所述部分之间的电接触形成在所述源极区下方的一定深度处。
30.根据权利要求27所述的方法,其中,所述互连层与所述上硅层的所述部分之间的电接触形成在沿所述本体区的下半部的一定深度处。
31.根据权利要求27所述的方法,其中,所述第一及第二硅区中的每个均具有基本均匀的掺杂浓度。
32.根据权利要求27所述的方法,其中,所述下硅层外延地形成在第一导电型的衬底上,并且所述上硅层外延地形成在所述下硅层上,其中,所述衬底具有比所述下硅层高的掺杂浓度,而所述下硅层具有比所述上硅层高的掺杂浓度。
33.根据权利要求27所述的方法,其中,所述两个本体区和所述源极区均与所述这对沟槽自动对准。
34.根据权利要求27所述的方法,还包括:
在所述这对沟槽之间形成第二导电型的重本体区,所述重本体区延伸到所述两个本体区中并且延伸到所述上硅层的所述部分中,所述重本体区具有比所述两个本体区高的掺杂浓度。
35.根据权利要求34所述的方法,其中,所述两个本体区、所述源极区、以及所述重本体区均与所述这对沟槽自动对准。
36.根据权利要求27所述的方法,其中,所述两个本体区和所述上硅层具有基本相同的深度。
37.根据权利要求27所述的方法,还包括:
在每个沟槽中形成凹入的栅电极;以及
形成使每个栅电极与所述互连层绝缘的绝缘盖。
38.根据权利要求37所述的方法,还包括:
在形成所述凹入的栅电极之前,在每个沟槽的底部中形成保护电极。
39.根据权利要求37所述的方法,还包括:
在形成所述凹入的栅电极之前,形成沿每个沟槽的底部延伸的厚底部绝缘体。
40.根据权利要求27所述的方法,其中,所述互连层是肖特基隔离金属层。
41.一种形成单块集成的沟槽MOSFET及肖特基二极管的方法,所述方法包括:
利用掩模形成延伸到且终止于上硅层中的第一多个沟槽,所述上硅层在下硅层上延伸,所述上硅层和所述下硅层为第一导电型;
用第二导电型的硅材料填充所述第一多个沟槽;
进行热循环,以将所述硅材料向外扩散到所述上硅层中及所述掩模下方;
利用掩模形成延伸穿过所述硅材料、所述上硅层、且终止于所述下硅层中的第二多个沟槽,从而在相应沟槽的每侧保留所述硅材料的位于所述掩模下方的向外扩散部分;
形成延伸到所述向外扩散部分中的第一导电型的第一硅区,从而使每两个相邻沟槽之间的所述向外扩散部分的保留的下部形成两个本体区,所述两个本体区被所述上硅层的一部分隔开;
进行硅蚀刻,以形成延伸穿过所述第一硅区的接触开口,从而保留所述第一硅区的外部,所述第一硅区的外部形成源极区;以及
形成填充所述接触开口的互连层,从而电接触所述源极区及所述上硅层的所述部分,所述互连层与所述上硅层的所述部分形成肖特基接触。
42.一种形成单块集成的沟槽MOSFET及肖特基二极管的方法,所述方法包括:
利用掩模形成延伸穿过上硅层且终止于下硅层中的多个沟槽,所述上硅层和所述下硅层为第一导电型,所述上硅层在下硅层上延伸;
进行双道成角度注入,以在所述上硅层中沿每个沟槽的上侧壁形成第二导电型的第一硅区;
形成第一导电型的第二硅区,所述第二硅区在每两个相邻沟槽之间延伸到所述第一硅区中,从而使所述第一硅区的剩余下部在每两个相邻沟槽之间形成两个本体区,所述两个本体区被所述上硅层的一部分隔开;
进行硅蚀刻,以形成延伸穿过所述第二硅区的接触开口,从而在每两个相邻沟槽之间保留所述第二硅区的外部,所述第二硅区的外部形成源极区;以及
形成填充所述接触开口的互连层,从而电接触所述源极区及所述上硅层的所述部分,所述互连层与所述上硅层的所述部分形成肖特基接触。
43.根据权利要求42所述的方法,其中,所述上硅层的在所述双道成角度注入期间接收掺杂剂的区域由注入角和所述掩模的厚度来限定。
44.一种形成单块集成的沟槽MOSFET及肖特基二极管的方法,所述方法包括:
利用掩模形成延伸到且终止于上硅层内的第一深度处的第一多个沟槽,所述上硅层在下硅层上延伸,所述上硅层和所述下硅层为第一导电型;
进行双道成角度注入,以在所述上硅层中沿每个沟槽的侧壁形成第二导电型的第一硅区;
利用所述掩模使所述多个沟槽更深地延伸至所述下硅层内的第二深度;
形成第一导电型的第二硅区,所述第二硅区在每两个相邻沟槽之间延伸到所述第一硅区中,从而使所述第一硅区的剩余下部在每两个相邻沟槽之间形成两个本体区,所述两个本体区被所述上硅层的一部分隔开;
进行硅蚀刻,以形成延伸穿过所述第二硅区的接触开口,从而在每两个相邻沟槽之间保留所述第二硅区的外部,所述第二硅区的外部形成源极区;以及
形成填充所述接触开口的互连层,从而电接触所述源极区及所述上硅层的所述部分,所述互连层与所述上硅层的所述部分形成肖特基接触。
45.根据权利要求44所述的方法,其中,所述上硅层的在所述双道成角度注入期间接收掺杂剂的区域由所述多个沟槽的所述第一深度、所述掩模的厚度、以及注入角来限定。
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US7713822B2 (en) 2010-05-11
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