WO2011049230A1 - Voltage regulator circuit - Google Patents

Voltage regulator circuit Download PDF

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Publication number
WO2011049230A1
WO2011049230A1 PCT/JP2010/068787 JP2010068787W WO2011049230A1 WO 2011049230 A1 WO2011049230 A1 WO 2011049230A1 JP 2010068787 W JP2010068787 W JP 2010068787W WO 2011049230 A1 WO2011049230 A1 WO 2011049230A1
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WIPO (PCT)
Prior art keywords
layer
transistor
oxide semiconductor
film
voltage
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Ceased
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PCT/JP2010/068787
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English (en)
French (fr)
Inventor
Shunpei Yamazaki
Hiroyuki Miyake
Masashi Tsubuku
Kosei Noda
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to KR1020177017124A priority Critical patent/KR101819644B1/ko
Priority to KR1020127012272A priority patent/KR101751908B1/ko
Publication of WO2011049230A1 publication Critical patent/WO2011049230A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • An embodiment of the present invention relates to a voltage regulator circuit including a transistor which includes an oxide semiconductor.
  • a technique for forming a thin film transistor (TFT) by using a thin semiconductor film formed over a substrate having an insulating surface has attracted attention.
  • a thin film transistor is used for a display device typified by a liquid crystal television.
  • a silicon-based semiconductor material is known as a material for a thin semiconductor film applicable to a thin film transistor.
  • an oxide semiconductor has attracted attention.
  • oxide semiconductor As a material for the oxide semiconductor, zinc oxide and a material containing zinc oxide as its component are known. Further, a thin film transistor formed using an amorphous oxide (oxide semiconductor) having an electron carrier concentration of less than 10 18 /cm 3 is disclosed (Patent Documents 1 to 3).
  • Patent Document 1 Japanese Published Patent Application No. 2006-165527
  • Patent Document 2 Japanese Published Patent Application No. 2006-165528
  • Patent Document 3 Japanese Published Patent Application No. 2006-165529 DISCLOSURE OF INVENTION
  • a difference from the stoichiometric composition in the oxide semiconductor arises in a thin film formation process.
  • electrical conductivity of the oxide semiconductor changes due to the excess or deficiency of oxygen.
  • hydrogen that enters the thin oxide semiconductor film during the formation of the thin film forms an oxygen (O)-hydrogen (H) bond and serves as an electron donor, which is a factor of changing electrical conductivity.
  • O-H bond is a polar molecule, it serves as a factor of varying the characteristics of an active device such as a thin film transistor manufactured using an oxide semiconductor.
  • an oxide semiconductor is a substantially n-type oxide semiconductor. Therefore, the on-off ratio of the thin film transistors disclosed in Patent Documents 1 to 3 is only the order of 10 3 . Such a low on-off ratio of the thin film transistor is due to large off current.
  • a voltage regulator circuit such as a step-up circuit or a step-down circuit is formed with the use of a transistor including an oxide semiconductor as a channel formation layer.
  • the oxide semiconductor has a lager energy gap than a silicon semiconductor and is an intrinsic or a substantially intrinsic semiconductor that is highly purified through removal of an impurity serving as an electron donor.
  • the concentration of hydrogen contained in the oxide semiconductor is less than or equal to 5 x 10 19 /cm 3 , preferably less than or equal to 5 x 10 18 /cm 3 , more preferably less than or equal to 5 x 10 17 /cm 3 .
  • hydrogen or an O-H bond contained in the oxide semiconductor is removed.
  • the carrier concentration is less than or equal to 5 x 10 14 /cm 3 , preferably less than or equal to 5 x 10 12 /cm 3 .
  • the energy gap is set to greater than or equal to 2 eV, preferably greater than or equal to 2.5 eV, more preferably greater than or equal to 3 eV to reduce as much impurities (e.g., hydrogen), which form donors, as possible.
  • the carrier concentration is set to less than or equal to 1 x 10 14 /cm 3 , preferably less than or equal to 1 x 10 12 /cm 3 .
  • an off current for a channel width of 1 ⁇ can be very small compared to a conventional transistor including silicon; for example, the off current can be less than or equal to 10 aA/ ⁇ (1
  • the off current for a channel width of 1 ⁇ can be very small compared to a conventional transistor including silicon; for example, the off current can be less than or equal to 100 ⁇ / ⁇ , preferably less than or equal to 10 ⁇ / ⁇ .
  • a voltage regulator circuit With the use of a transistor including an oxide semiconductor layer which is highly purified by sufficiently reducing the hydrogen concentration, a voltage regulator circuit can be achieved in which power consumption due to leakage current is low compared to the case of using a conventional transistor including silicon.
  • a voltage regulator circuit includes a transistor and a capacitor.
  • the transistor includes a gate, a source, and a drain, the gate is electrically connected to the source or the drain, a first signal is input to one of the source and the drain, an oxide semiconductor layer is used for a channel formation layer, and an off current is less than or equal to 100 ⁇ / ⁇ .
  • the capacitor includes a first electrode and a second electrode, the first electrode is electrically connected to the other of the source and the drain of the transistor, and a second signal which is a clock signal is input to the second electrode. A voltage of the first signal is stepped up or down to obtain a third signal, and the third signal which has a voltage obtained by stepping up or down the voltage of the first signal is output as an output signal through the other of the source and the drain of the transistor.
  • a voltage regulator circuit includes n stages ( « is a natural number of greater than or equal to 2) of unit step-up circuits which are electrically connected to each other in series.
  • a unit step-up circuit of a (2 -l)-th stage (M is any one of 1 to n/2, and 2M is a natural number) includes a first transistor and a first capacitor.
  • the first transistor includes a gate, a source, and a drain, wherein the gate is electrically connected to one of the source and the drain, an oxide semiconductor layer is used for a channel formation layer, and an off current is less than or equal to 100 ⁇ / ⁇ .
  • the first capacitor includes a first electrode and a second electrode, wherein the first electrode is electrically connected to the other of the source and the drain of the first transistor, and a clock signal is input to the second electrode.
  • a unit step-up circuit of a 2 -th stage includes a second transistor and a second capacitor.
  • the second transistor includes a gate, a source, and a drain, wherein the gate is electrically connected to one of the source and the drain, an oxide semiconductor layer is used for a channel formation layer, and an off current is less than or equal to 100 ⁇ / ⁇ .
  • the second capacitor includes a first electrode and a second electrode, wherein the first electrode is electrically connected to the other of the source and the drain of the second transistor, and an inverted clock signal is input to the second electrode.
  • a voltage regulator circuit includes n stages (n is a natural number of greater than or equal to 2) of unit step-down circuits which are electrically connected to each other in series.
  • a unit step-down circuit of a (2M-l)-th stage (M is any one of 1 to n/2, and 2M is a natural number) includes a first transistor and a first capacitor.
  • the first transistor includes a gate, a source, and a drain, wherein an oxide semiconductor layer is used for a channel formation layer, and an off current is less than or equal to 100 ⁇ / ⁇ .
  • the first capacitor includes a first electrode and a second electrode, wherein the first electrode is electrically connected to the gate the first transistor, and a clock signal is input to the second electrode.
  • a unit step-down circuit of a 2 -th stage includes a second transistor and a second capacitor.
  • the second transistor includes a gate, a source, and a drain, wherein one of the source and the drain is electrically connected to the gate and the source or the drain of the first transistor, an oxide semiconductor layer is used for a channel formation layer, and an off current is less than or equal to 100 ⁇ / ⁇ .
  • the second capacitor includes a first electrode and a second electrode, wherein the first electrode is electrically connected to the gate and the other of the source and the drain of the second transistor, and an inverted clock signal is input to the second electrode.
  • leakage current of a transistor can be reduced, and a drop in voltage of an output signal can be reduced, whereby conversion efficiency to obtain a desired voltage can be improved.
  • FIG 1 is a circuit diagram illustrating an example of a structure of a voltage regulator circuit.
  • FIG 2 is a timing chart for explaining an example of an operation of a voltage regulator circuit illustrated in FIG 1.
  • FIG 3 is a circuit diagram illustrating an example of a structure of a voltage regulator circuit.
  • FIG 4 is a circuit diagram illustrating an example of a structure of a voltage regulator circuit.
  • FIGS. 5 A and 5 B are a top view and a cross-sectional view illustrating a transistor.
  • FIGS. 6 A to 6E are cross-sectional views illustrating a method for manufacturing a transistor.
  • FIGS. 7 A and 7B are a top view and a cross-sectional view illustrating a transistor.
  • FIGS. 8 A to 8E are cross-sectional views illustrating a method for manufacturing a transistor.
  • FIGS. 9 A and 9B are cross-sectional views each illustrating a transistor.
  • FIGS. 10A to 10E are cross-sectional views illustrating a method for manufacturing a transistor.
  • FIG 11 is a cross-sectional view of an inverted staggered thin film transistor which includes an oxide semiconductor.
  • FIGS. 12A and 12B are each an energy band diagram (schematic diagram) of a cross section along A- A' in FIG. 11.
  • FIG 13A is an energy band diagram illustrating a state in which positive potential (+VG) is applied to a gate electrode 1001
  • FIG. 13B is an energy band diagram illustrating a state in which negative potential (-VG) is applied to a gate electrode 1001.
  • FIG. 14 is an energy band diagram illustrating the relationship between the vacuum level and the work function of a metal ( ⁇ ) and between the vacuum level and the electron affinity ( ⁇ ) of an oxide semiconductor.
  • FIG 15 is a circuit diagram for evaluating the characteristics of a transistor which includes an oxide semiconductor.
  • FIG 16 is a timing chart for evaluating the characteristics of a transistor which includes an oxide semiconductor.
  • FIG 17 is a graph showing the characteristics of a transistor which includes an oxide semiconductor.
  • FIG 18 is a graph showing the characteristics of a transistor which includes an oxide semiconductor. y
  • FIG 19 is a graph showing the characteristics of a transistor which includes an oxide semiconductor.
  • FIGS. 20A to 20E are cross-sectional views illustrating a method for manufacturing a transistor.
  • FIGS. 21A to 21D are cross-sectional views illustrating a method for manufacturing a transistor.
  • FIGS. 22 A to 22D are cross-sectional views illustrating a method for manufacturing a transistor.
  • FIG 23 is a cross-sectional view illustrating a transistor.
  • FIGS. 24A and 24B are external views each illustrating an electronic device.
  • An example of a structure of a voltage regulator circuit described in this embodiment has a function of inputting a signal SI and a signal S2 as input signals, stepping up or stepping down the voltage of the input signal SI, and thereby outputting as an output signal a signal S3 which has a voltage obtained by stepping up or stepping down the voltage of the signal SI.
  • An example of the structure of the voltage regulator circuit in this embodiment is further described with reference to FIG. 1.
  • FIG 1 is a circuit diagram illustrating an example of the structure of the voltage regulator circuit of this embodiment.
  • the voltage regulator circuit illustrated in FIG 1 includes a transistor 101 and a capacitor 102.
  • a field-effect transistor can be used as the transistor.
  • the field-effect transistor has at least a gate, a source, and a drain.
  • a thin film transistor also referred to as a TFT
  • the field-effect transistor can have, for example, a top-gate structure or a bottom-gate structure.
  • the field-effect transistor can have n-type conductivity.
  • the gate means entire gate electrode and gate wiring or part thereof.
  • the gate wiring is a wiring for electrically connecting a gate electrode of at least one transistor to a different electrode or a different wiring.
  • the source means entire source region, source electrode, and source wiring or part thereof.
  • the source region is a region whose resistance is lower than that of a channel formation layer in a semiconductor layer.
  • the source electrode means part of a conductive layer, which is connected to the source region.
  • the source wiring is a wiring for electrically connecting a source electrode of at least one transistor to a different electrode or a different wiring.
  • the drain means entire drain region, drain electrode, and drain wiring or part thereof.
  • the drain region is a region whose resistance is lower than that of a channel formation layer in a semiconductor layer.
  • the drain electrode means part of a conductive layer, which is connected to the drain region.
  • the drain wiring is a wiring for electrically connecting a drain electrode of at least one transistor to a different electrode or a different wiring.
  • a source and a drain of a transistor may interchange with each other depending on the structure, the operating condition, and the like of the transistor; therefore, it is difficult to define which is a source or a drain. Therefore, in this document (the specification, the claims, the drawings, and the like), one of them is referred to as one of the source and the drain, and the other is referred to as the other of the source and the drain.
  • the field-effect transistor in this specification is a transistor which includes an oxide semiconductor layer having a function as a channel formation layer.
  • the hydrogen concentration in the channel formation layer is less than or equal to 5 x 10 19 atoms/cm 3 , preferably less than or equal to 5 x 10 18 atoms/cm 3 , more preferably less than or equal to 5 x 10 atoms/cm .
  • the hydrogen concentration is measured using secondary ion mass spectroscopy (SIMS).
  • SIMS secondary ion mass spectroscopy
  • the carrier concentration of the transistor is less than or equal to 1 x 10 14 /cm 3 , preferably less than or equal to 1 x 10 12 /cm 3 .
  • a capacitor which includes a first electrode, a second electrode, and a dielectric can be used, for example.
  • the signal SI or the signal S3 is input to a gate of the transistor 101.
  • the signal SI is input to one of a source and a drain of the transistor 101.
  • the voltage of the other of the source and the drain of the transistor 101 is equal to the voltage of the signal S3.
  • the voltage regulator circuit illustrated in FIG. 1 outputs the signal S3 through the other of the source and the drain of the transistor 101.
  • voltage regulation operation is performed differently, depending on which of the signals SI and S3 is input to the gate.
  • the voltage of the signal S3 can be higher than the voltage of the signal SI.
  • the voltage of the signal S3 can be lower than the voltage of the signal SI.
  • Step-up means that the voltage of the signal S3 is increased to be higher than the voltage of the signal SI
  • step-down means that the voltage of the signal S3 is decreased to be lower than the voltage of the signal SI.
  • a voltage refers to a difference between potentials of two points (also referred to as a potential difference).
  • both the value of voltage and the value of a potential are represented by volts (V) in a circuit diagram or the like in some cases; therefore, it is difficult to distinguish them.
  • V volts
  • an analog signal or a digital signal which uses voltage or the like can be used, for example.
  • a signal which uses voltage also referred to as a voltage signal
  • a digital signal which has a high-level voltage state as the first voltage state and a low-level voltage state as the second voltage state can be used, for example.
  • a high-level voltage is also referred to as VH and a low-level voltage is also referred to as VL.
  • the voltage in the first voltage state and the voltage in the second voltage sate have variation in some cases, which depends on signals.
  • the voltage in the first voltage state and the voltage in the second voltage state do not necessarily have a fixed value and may have a value within a predetermined range.
  • a first electrode of the capacitor 102 is electrically connected to the other of the source and the drain of the transistor 101, and the signal S2 is input to a second electrode of the capacitor 102.
  • a region where the first electrode of the capacitor 102 and the other of the source and the drain of the transistor 101 are connected to each other is also referred to as a node Nlll.
  • the signal SI serves as a first input signal (also referred to as a signal INvci) of the voltage regulator circuit.
  • the signal S2 serves as a second input signal (also referred to as a signal 1NVC2) of the voltage regulator circuit.
  • a clock signal can be used as the signal S2, for example.
  • the clock signal is a signal in which the first voltage state and the second voltage state are periodically repeated. Values of the first voltage state and the second voltage state of the clock signal can be set as appropriate.
  • the signal S3 serves as an output signal (also referred to as a signal OUTvc) of the voltage regulator circuit.
  • FIG. 2 is a timing chart for explaining an example of the operation of the voltage regulator circuit illustrated in FIG 1, and illustrates the waveforms of the voltages of the signal SI, the signal S2, and the signal S3.
  • the signal SI is a binary digital signal having a high level and a low level
  • the signal S2 is a clock signal in which a high level and a low level are periodically repeated
  • the transistor 101 is an n-channel transistor
  • the signal SI is input to the gate of the transistor 101.
  • the operation of the voltage regulator circuit illustrated in FIG 1 can be described by being divided into a plurality of periods. The operation in each period is described below.
  • the signal SI is set to a high level and the signal S2 is set to a low level.
  • the source and the drain of the transistor 101 are placed in a conduction state, so that the voltage at the node Nlll begins to increase.
  • the voltage at the node Nlll is increased to VI.
  • VI is VH-V t hioi (threshold voltage of the transistor 101).
  • the source and the drain of the transistor 101 are placed in a non-conduction state, which brings the node Nlll in a floating state.
  • a voltage VI- VL is applied between the first electrode and the second electrode of the capacitor 102, and the voltage of the signal S3 becomes VI.
  • the signal SI is kept at a high level and the signal S2 is set to a high level.
  • the transistor 101 is in a non-conduction state, and the node Nlll is in a floating state. Since the voltage applied to the second electrode of the capacitor 102 is changed from the voltage VL to the voltage VH, also the voltage of the first electrode of the capacitor 102 begins to change, in accordance with the voltage of the second electrode of the capacitor 102. The voltage at the node Nlll is increased to a value which is higher than the voltage VI, that is, V2. The voltage V2 is V H -V th ioi+V H . At this time, a voltage V2-VH is applied between the first electrode and the second electrode of the capacitor 102, and the voltage of the signal S3 is V2. In this manner, in the period 152, the voltage of the signal S3 which is an output signal of the voltage regulator circuit corresponds to a value obtained by stepping up the voltage of the signal SI that is input to the voltage regulator circuit.
  • a voltage signal which is input is changed and a signal with a voltage that is higher or lower than that of the input voltage signal can be output; therefore, power consumption can be reduced.
  • a transistor in the voltage regulator circuit according to this embodiment, includes an oxide semiconductor layer serving as a channel formation layer.
  • the hydrogen concentration is less than or equal to 5 x 10 19 atoms/cm 3 , preferably less than or equal to 5 x 10 18 atoms/cm 3 , more preferably less than or equal to 5 x 10 atoms/cm
  • the carrier concentration is less than or equal to 1 x 10 14 /cm 3 , preferably less than or equal to 1 x 10 12 /cm 3 . Since leakage current is small in the transistor, leakage of electric charge stored in a capacitor can be reduced compared to a conventional transistor; thus, a speed at which a desired voltage is achieved can be significantly increased.
  • the capacitor and the transistor can be formed through the same manufacturing steps, which can reduce the number of manufacturing steps.
  • a step-up circuit will be described as an example of a voltage regulator circuit which is an embodiment of the present invention.
  • FIG 3 is a circuit diagram illustrating an example of the circuit structure of a voltage regulator circuit according to this embodiment.
  • the voltage regulator circuit illustrated in FIG 3 includes a unit step-up circuit 211 1 to a unit step-up circuit 211_n (n is a natural number of greater than or equal to 2) and is formed with n stages of unit step-up circuits obtained by electrically connecting the unit step-up circuit 211 1 to the unit step-up circuit 211_ « in series.
  • the transistor 201 a transistor which includes an oxide semiconductor layer serving as a channel formation layer can be used.
  • the hydrogen concentration in the channel formation layer is less than or equal to 5 x 10 19 atoms/cm 3 , preferably less than or equal to 5 x 10 18 atoms/cm 3 , more preferably less than or equal to 5 x 10 17 atoms/cm 3 .
  • the hydrogen concentration is measured by secondary ion mass spectroscopy (SIMS).
  • the carrier concentration of the transistor 201 is less than or equal to 1 x 10 14 /cm 3 , preferably less than or equal to 1 x 10 12 /cm 3 .
  • a gate of the transistor 201 is electrically connected to one of a source and a drain of the transistor 201. That is, the transistor 201 is diode-connected.
  • a first electrode of the capacitor 202 is electrically connected to the other of the source and the drain of the transistor 201.
  • a source and a drain of the transistor 201 is electrically connected to the other of a source and a drain of the transistor 201 in a unit step-up circuit in a ( C-l)-th stage.
  • a portion where the other of the source and the drain of the transistor 201 in the unit step-up circuit in the K-l)-tii stage and one of the source and the drain of the transistor 201 in the unit step-up circuit in the K-th stage are connected to each other is denoted by a node N1_M (M is any one of 1 to nil).
  • a second electrode of the capacitor 202 is electrically connected to a clock signal line 221.
  • a second electrode of the capacitor 202 is electrically connected to a clock signal line 222.
  • a clock signal CKl is input to the clock signal line 221.
  • a clock signal CKB1 is input to the clock signal line 222.
  • the clock signal CKl and the clock signal CKBl have opposite phases. For example, when the clock signal CKl is a high-level signal, the clock signal CKBl is a low-level signal.
  • the clock signal CKBl for example, a signal obtained by inversion of the clock signal CKl can be used.
  • the clock signal CKBl can be generated by inversion of the voltage state of the clock signal CKl with a NOT circuit such as an inverter, for example.
  • a NOT circuit such as an inverter
  • values of a voltage such as a high level and a low level can be determined as appropriate.
  • the clock signal CKl can be generated with the use of a buffer circuit and an oscillator circuit such as a ring oscillator, for example.
  • not only the clock signal CKl and the clock signal CKBl, but also a clock signal having three or more phases can be used.
  • a signal INI is input to one of a source and a drain of the transistor 201.
  • the voltage of the other of a source and a drain of the transistor 201 is the voltage of a signal OUT1 which is an output signal of the voltage regulator circuit.
  • Voltage V cl is applied to a second electrode of the capacitor 202 in the unit step-up circuit 211 _n.
  • the voltage V cl can be any voltage.
  • voltage which has the same value as voltage VH or voltage VL can be used.
  • the capacitance of the capacitor 202 in the unit step-up circuit 211_n is preferably larger than that of the capacitors 202 in the other unit step-up circuits.
  • the capacitance of the capacitor 202 in the unit step-up circuit 211_ « is large, the voltage state of the output signal of the unit step-up circuit 211 /1, that is, the signal OUT1 which is the output signal of the voltage regulator circuit can be further stabilized.
  • each unit step-up circuit includes a diode-connected transistor and a capacitor.
  • the diode-connected transistor a transistor which includes a highly purified oxide semiconductor layer as a channel formation layer is used.
  • the voltage of each node can be held for a longer time, it takes a shorter time to obtain a desired voltage, and voltage conversion efficiency can be improved.
  • FIG 3 is described.
  • the operation of the voltage regulator circuit illustrated in FIG 3 can be described by being divided into a plurality of periods. The operation in each period is described below. Note that in a example of the operation of the voltage regulator circuit illustrated in FIG 3, which is described here, a high-level signal is input as the signal INI; a clock signal whose level is periodically changed between a high level and a low level is used as the clock signal CKl; a clock signal obtained by inversion of the clock signal CK is used as the clock signal CKBl; the transistor 201 in each unit step-up circuit is an n-channel transistor; and the threshold voltages of the transistors 201 in the unit step-up circuits are the same.
  • the clock signal CKl is set to a low level, and the clock signal CKBl is set to a high level.
  • the diode-connected transistor 201 in the unit step-up circuit 211 1 is placed in a non-conduction state, so that the node Ni l is made to be in a floating state.
  • the clock signal CKl is set to a high level
  • the clock signal CKBl is set to a low level.
  • the transistor 201 is kept in a non-conduction state, the node Ni l is in a floating state, and voltage applied to a second electrode of the capacitor 202 in the unit step-up circuit 211_1 is changed into VH.
  • the voltage of the first electrode of the capacitor 202 begins to change in accordance with the change in the voltage of the second electrode of the capacitor 202.
  • the voltage of the node Ni l is increased to V ⁇ i - V t h 2 oi + VH.
  • voltage applied between the first electrode and the second electrode of the capacitor 202 is VIN - V t h 2 oi-
  • the voltage of the node Ni l is voltage obtained by stepping up the voltage of the node Ni l in the first period.
  • the diode-connected transistor 201 is placed in a conduction state, so that the voltage of a node N1 2 begins to increase.
  • the voltage of the node JV1 2 (also referred to as voltage VN 2 ) is increased to V I - V t h 2 oi-
  • VN 2 voltage
  • the diode-connected transistor 201 in the unit step-up circuit 211_2 is placed in a non-conduction state, so that the node iVl_2 is made to be in a floating state.
  • the clock signal CK1 is set to a low level, and the clock signal CKB1 is set to a high level.
  • the transistor 201 in the unit step-up circuit 211 2, the transistor 201 is kept in a non-conduction state, the node N1 2 is in a floating state, and voltage applied to a second electrode of the capacitor 202 in the unit step-up circuit 211 2 is changed from V L into V H .
  • the voltage of the first electrode of the capacitor 202 begins to change in accordance with the change in the voltage of the second electrode of the capacitor 202.
  • the voltage of the node N1 2 is increased to V I - V t h 2 oi + VH.
  • voltage applied between the first electrode and the second electrode of the capacitor 202 is VNI - V t h 2 oi-
  • the voltage of the node N1 2 is voltage obtained by stepping up the voltage of the node JV1_2 in the second period.
  • the diode-connected transistor 201 is placed in a conduction state, so that the voltage of a node N1 3 starts to increase.
  • the voltage of the node N1 3 (also referred to as voltage VN 3 ) is increased to V 2 - V ⁇ O L
  • the diode-connected transistor 201 in the unit step-up circuit 211 3 is placed in a non-conduction state, so that the node Nl_3 is made to be in a floating state.
  • each unit step-up circuit in a third or subsequent stage operations which are similar to those of the above unit step-up circuits are sequentially performed in accordance with a periodical change of the clock signal CKl and the clock signal CKBl between a high level and a low level, and a voltage of each node N1_ is stepped up gradually every time the clock signal CKl or the clock signal CKBl is changed periodically between a high level and a low level and stepped up to Vn ⁇ + M (VH - V th2 oi) at a maximum.
  • the voltage of the signal OUT1 is stepped up gradually every time the clock signal CKl or the clock signal CKBl is changed periodically between a high level and a low level and stepped up to Vim + n (VH - V t h2oi) at a maximum.
  • the voltage of the signal INI is stepped up, and the signal OUT1 having the stepped up voltage is output as an output signal.
  • a signal whose voltage is higher than the voltage of an input signal can be output as an output signal.
  • the diode-connected transistor in each unit step-up circuit is a transistor which includes a highly purified oxide semiconductor layer as a channel formation layer.
  • the leakage current of the transistor can be reduced, conversion efficiency to obtain a desired voltage can be improved, the voltage of each node can be held for a longer time, and it takes a shorter time to obtain a desired voltage by step-up operation.
  • a step-down circuit will be described as another example of a voltage regulator circuit which is an embodiment of the present invention. Note that in this embodiment, the description in Embodiment 2 is employed as appropriate for the same portions as the voltage regulator circuit in Embodiment 2.
  • FIG. 4 is a circuit diagram illustrating an example of the circuit structure of a voltage regulator circuit in this embodiment.
  • the voltage regulator circuit illustrated in FIG 4 includes a unit step-down circuit 511_1 to a unit step-down circuit 511_ « (n is a natural number of greater than or equal to 2) and is formed with n stages of unit step-down circuits obtained by electrically connecting the unit step-down circuit 511 1 to the unit step-down circuit 511 /1 in series.
  • the unit step-down circuits 511 1 to 51 I n each include a transistor 501 and a capacitor 502.
  • the transistor 501 a transistor which includes an oxide semiconductor layer serving as a channel formation layer can be used.
  • the hydrogen concentration in the channel formation layer is less than or equal to 5 x 10 19 atoms/cm 3 , preferably less than or equal to 5 x 10 atoms/cm , more preferably less than or equal to 5 x 10 17 atoms/cm 3 .
  • the hydrogen concentration is measured by secondary ion mass spectroscopy (SIMS).
  • the carrier concentration of the transistor 501 is less than or equal to 1 x 10 14 /cm 3 , preferably less than or equal to 1 x 10 12 /cm 3 .
  • a source and a drain of the transistor 501 is electrically connected to the other of a source and a drain of the transistor 501 in a unit step-down circuit in a (K-l)-th stage.
  • a portion where the other of the source and the drain of the transistor 501 in the unit step-down circuit in the (X-l)-th stage and one of the source and the drain of the transistor 501 in the unit step-down circuit in the K-t stage are connected to each other is denoted by a node N2_M.
  • a gate of the transistor 501 is electrically connected to the other of a source and a drain of the transistor 501. That is, the transistor 501 is diode-connected.
  • a first electrode of the capacitor 502 is electrically connected to the other of the source and the drain of the transistor 501. That is, although the transistor 201 in the voltage regulator circuit illustrated in FIG 3 has a structure in which the gate is electrically connected to one of the source and the drain, the transistor 501 in the voltage regulator circuit illustrated in FIG 4 has a structure in which the gate is electrically connected to the other of the source and the drain.
  • a first electrode of the capacitor 502 is electrically connected to the gate of the transistor 501, and a second electrode of the capacitor 502 is electrically connected to a clock signal line 521.
  • one of the source and the drain of the transistor 501 is electrically connected to the gate and the source or the drain of the transistor 501 in the (2 -l)-th stage, a first electrode of the capacitor 502 is electrically connected to the gate and the other of the source and the drain of the transistor 501, and a second electrode of the capacitor 502 is electrically connected to a clock signal line 522.
  • a clock signal CK2 is input to the clock signal line 521.
  • a clock signal CKB2 is input to the clock signal line 522.
  • the clock signal CK2 and the clock signal CKB2 have opposite phases. For example, when the clock signal CK2 is a high-level signal, the clock signal CKB2 is a low-level signal.
  • the clock signal C B2 for example, a signal obtained by inversion of the clock signal CK2 can be used.
  • the clock signal CKB2 can be generated by inversion of the voltage state of the clock signal CK2 with a NOT circuit such as an inverter, for example.
  • values of a voltage such as a high level and a low level can be determined as appropriate.
  • the clock signal CK2 can be generated with the use of a buffer circuit and an oscillator circuit such as a ring oscillator, for example. Further, not only the clock signal C 2 and the clock signal CKB2, but also a clock signal having three or more phases can be used.
  • a signal IN2 is input to one of a source and a drain of the transistor 501.
  • the voltage of the other of the source and the drain of the transistor 501 is the voltage of a signal OUT2 which is an output signal of the voltage regulator circuit.
  • Voltage V C 2 is applied to a second electrode of the capacitor 502 in the unit step-down circuit 511_ «.
  • the voltage V c2 can be any voltage.
  • voltage which has the same value as voltage VH or voltage VL can be used.
  • the capacitance of the capacitor 502 in the unit step-down circuit 511_n is preferably larger than that of the capacitors 502 in the other unit step-down circuits.
  • the capacitance of the capacitor 502 in the unit step-down circuit 511_n is large, the voltage state of the output signal of the unit step-down circuit 511_n, that is, the signal OUT2 which is the output signal of the voltage regulator circuit can be further stabilized.
  • each unit step-down circuit includes a diode-connected transistor and a capacitor.
  • the diode-connected transistor a transistor including as a channel formation layer an oxide semiconductor layer in which the hydrogen concentration is reduced and off current is reduced is used.
  • the voltage of each node can be held for a longer time, it takes a shorter time to obtain a desired voltage, and voltage conversion efficiency can be improved.
  • the operation of the voltage regulator circuit illustrated in FIG 4 can be described by being divided into a plurality of periods. The operation in each period is described below. Note that in an example of the operation of the voltage regulator circuit illustrated in FIG. 4, which is described here, a low-level signal is input as the signal IN2; a clock signal whose level is periodically changed between a high level and a low level is used as the clock signal CK2; a clock signal obtained by inversion of the clock signal CK2 is used as the clock signal CKB2; the transistor 501 in each unit step-down circuit is an n-channel transistor; and the threshold voltages of the transistors 501 in the unit step-down circuits are the same.
  • the clock signal CK2 is set to a high level, and the clock signal CKB2 is set to a low level.
  • the diode-connected transistor 501 is placed in a conduction state, so that the voltage of a node N2_l begins to decrease.
  • the voltage of the node JV2 1 (also referred to as voltage VN 2 ) is decreased to Vnv[ 2 (the voltage of the signal IN2) + F th soi (the threshold voltage of the transistor 501).
  • the diode-connected transistor 501 in the unit step-down circuit 511_1 is placed in a non-conduction state, so that the node N2 1 is made to be in a floating state.
  • the clock signal C 2 is set to a low level, and the clock signal CKB2 is set to a high level.
  • the transistor 501 is kept in a non-conduction state, the node N2_ l is in a floating state, and voltage applied to a second electrode of the capacitor 502 in the unit step-down circuit 511_1 is changed into VL.
  • the voltage of the first electrode of the capacitor 502 begins to change in accordance with the change in the voltage of the second electrode of the capacitor 502.
  • the voltage of the node N2_l is decreased to VIN 2 + V t hsoi - VH.
  • voltage applied between the first electrode and the second electrode of the capacitor 502 is VIN 2 + V th soi-
  • the voltage of the node N2 1 is voltage obtained by stepping down the voltage of the node JV2 1 in the first period.
  • the diode-connected transistor 501 is placed in a conduction state, so that the voltage of a node JV2 2 begins to decrease.
  • the voltage of the node N2_2 (also referred to as voltage V N2 ) is decreased to VN 2 + Vthsoi-
  • the diode-connected transistor 501 in the unit step-down circuit 511_2 is placed in a non-conduction state, so that the node N2 2 is made to be in a floating state.
  • the clock signal CK2 is set to a high level, and the clock signal CKB2 is set to a low level.
  • the transistor 501 is kept in a non-conduction state, the node N2_2 is in a floating state, and voltage applied to a second electrode of the capacitor 502 in the unit step-down circuit 511 2 is changed into V L .
  • the voltage of the first electrode of the capacitor 502 begins to change in accordance with the change in the voltage of the second electrode of the capacitor 502.
  • the voltage of the node N2 2 is decreased to VN 2 + V t h 5 oi - V H .
  • voltage applied between the first electrode and the second electrode of the capacitor 502 is V 2 + thsoi-
  • the voltage of the node N2 2 is voltage obtained by stepping down the voltage of the node N2 2 in the second period.
  • the diode-connected transistor 501 is placed in a conduction state, so that the voltage of a node N2 3 begins to decrease.
  • the voltage of the node N2_3 (also referred to as voltage KN 3 ) is decreased to Vm + ⁇ thsoi-
  • tne diode-connected transistor 501 in the unit step-down circuit 511 3 is placed in a non-conduction state, so that the node N2 3 is made to be in a floating state.
  • each unit step-down circuit in a third or subsequent stage operations which are similar to those of the above unit step-down circuits are sequentially performed in accordance with a periodical change of the clock signal CK2 and the clock signal CKB2 between a high level and a low level, and a voltage of each node N2_ is stepped down gradually every time the clock signal CK2 or the clock signal CKB2 is changed periodically between a high level and a low level and stepped down to VJ 2 - M (VH + V t h5oi) at a minimum.
  • the voltage of the signal OUT2 is stepped down gradually every time the clock signal CK2 or the clock signal CKB2 is changed periodically between a high level and a low level and stepped down to V 1N2 - n (V H + Vthsoi) at a minimum.
  • the voltage of the signal IN2 is stepped down, and the signal OUT2 having the stepped down voltage is output as an output signal.
  • a signal whose voltage is lower than the voltage of an input signal can be output as an output signal.
  • the diode-connected transistor in each unit step-down circuit is a transistor which includes a highly purified oxide semiconductor layer as a channel formation layer.
  • the leakage current of the transistor can be reduced, conversion efficiency to obtain a desired voltage can be improved, the voltage of each node can be held for a longer time, and it takes a shorter time to obtain a desired voltage by step-down operation.
  • FIGS. 5A and 5B and FIGS. 6Ato 6E One embodiment of a thin film transistor and a manufacturing method of the thin film transistor of this embodiment is described with reference to FIGS. 5A and 5B and FIGS. 6Ato 6E.
  • FIGS. 5A and 5B illustrate an example of a planar structure and an example of a cross-sectional structure of a transistor.
  • a thin film transistor 410 illustrated in FIGS. 5A and 5B is one of top gate thin film transistors.
  • FIG 5A is a plan view of the thin film transistor 410 having a top-gate structure and FIG. 5B is a cross-sectional view taken along C1-C2 in FIG 5 A.
  • the thin film transistor 410 includes, over a substrate 400 having an insulating surface, an insulating layer 407, an oxide semiconductor layer 412, a source or drain electrode layer 415a, a source or drain electrode layer 415b, a gate insulating layer 402, and a gate electrode layer 411.
  • a wiring layer 414a and a wiring layer 414b are provided so as to be in contact with and electrically connected to the source or drain electrode layer 415a and the source or drain electrode layer 415b, respectively.
  • the thin film transistor 410 is described using a single-gate thin film transistor; a multi-gate thin film transistor including a plurality of channel formation regions can be formed when needed.
  • a process of manufacturing the thin film transistor 410 over the substrate 400 is described below with reference to FIGS. 6A to 6E.
  • a substrate which can be used as the substrate 400 having an insulating surface it is necessary that the substrate have at least a heat resistance high enough to withstand heat treatment to be performed later.
  • a glass substrate formed of barium borosilicate glass, aluminoborosilicate glass, or the like can be used.
  • a glass substrate whose strain point is greater than or equal to 730 °C is preferably used.
  • a glass substrate a glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass is used, for example. Note that by containing a larger amount of barium oxide (BaO) than boron oxide, a glass substrate is heat-resistant and of more practical use. Therefore, a glass substrate containing a larger amount of BaO than B 2 0 3 is preferably used.
  • a substrate formed of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used.
  • crystallized glass or the like may be used.
  • a plastic substrate or the like can be used as appropriate.
  • a semiconductor substrate of silicon or the like can be used as the substrate.
  • the insulating layer 407 which serves as a base film is formed over the substrate 400 having an insulating surface.
  • an oxide insulating layer such as a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or an aluminum oxynitride layer is preferably used.
  • a plasma CVD method, a sputtering method, or the like can be employed as a method for forming the insulating layer 407
  • the insulating layer 407 is preferably formed by a sputtering method so that hydrogen is contained in the insulating layer 407 as little as possible.
  • a silicon oxide layer is formed as the insulating layer 407 by a sputtering method.
  • the substrate 400 is transferred to a treatment chamber and a high-purity sputtering gas from which hydrogen and moisture are removed and which contains oxygen is introduced, and a silicon oxide layer is formed as the insulating layer 407 over the substrate 400 with the use of a silicon semiconductor target.
  • the substrate 400 may be at a room temperature or may be heated.
  • a silicon oxide film is formed by an RF sputtering method under the following condition: quartz (preferably, synthetic quartz) is used as a target; the substrate temperature is 108 °C; the distance between the substrate and the target (the T-S distance) is 60 mm; the pressure is 0.4 Pa; the high frequency power is 1.5 kW; and the atmosphere is an atmosphere containing oxygen and argon (the flow ratio of oxygen to argon is 1:1 (each flow rate is 25 seem).
  • the thickness of the silicon oxide film is 100 nm.
  • quartz preferably, synthetic quartz
  • a silicon target can be used as a target used when the silicon oxide film is formed.
  • oxygen or a mixed gas of oxygen and argon is used.
  • the insulating layer 407 is preferably formed removing moisture remaining in the treatment chamber. This is for preventing hydrogen, a hydroxyl group, or moisture from being contained in the insulating layer 407.
  • an entrapment vacuum pump is preferably used.
  • a cryopump, an ion pump, or a titanium sublimation pump is preferably used.
  • an evacuation unit may be a turbo pump provided with a cold trap.
  • a hydrogen atom, a compound containing a hydrogen atom, such as water (H 2 0), or the like is removed, whereby the concentration of an impurity in the insulating layer 407 formed in the deposition chamber can be reduced.
  • a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed to a concentration of several ppm or a concentration of several ppb, as a sputtering gas when the insulating layer 407 is formed.
  • Examples of a sputtering method include an RF sputtering method in which a high-frequency power source is used as a sputtering power source, a DC sputtering method in which a direct current source is used, a pulsed DC sputtering method in which a bias is applied in a pulsed manner, and the like.
  • An RF sputtering method is mainly used in the case where an insulating film is formed, and a DC sputtering method is mainly used in the case where a metal film is formed.
  • multi-source sputtering apparatus in which a plurality of targets of different materials can be set.
  • films of different materials can be formed to be stacked in the same chamber, or a film of plural kinds of materials can be formed by electric discharge at the same time in the same chamber.
  • a sputtering apparatus provided with a magnet system inside the chamber and used for a magnetron sputtering method, or a sputtering apparatus used for an ECR sputtering method in which plasma generated with the use of microwaves is used without using glow discharge can be used.
  • a deposition method using a sputtering method a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted with each other during deposition to form a thin compound film thereof, or a bias sputtering method in which a voltage is also applied to a substrate during deposition can be used.
  • the insulating layer 407 may have a layered structure in which for example, a nitride insulating layer such as a silicon nitride layer, a silicon nitride oxide layer, an aluminum nitride layer, or an aluminum nitride oxide layer and the oxide insulating layer are stacked in this order from the substrate 400 side.
  • a nitride insulating layer such as a silicon nitride layer, a silicon nitride oxide layer, an aluminum nitride layer, or an aluminum nitride oxide layer and the oxide insulating layer are stacked in this order from the substrate 400 side.
  • a high-purity sputtering gas from which hydrogen and moisture are removed and which contains nitrogen is introduced and a silicon target is used, whereby a silicon nitride layer is formed between a silicon oxide layer and a substrate.
  • the silicon nitride layer is preferably formed removing moisture remaining in a treatment chamber, similarly to the silicon oxide layer.
  • the substrate may be heated also at the time of the film deposition of the silicon nitride layer.
  • the silicon nitride layer and the silicon oxide layer can be formed in the same chamber with the same silicon target.
  • a sputtering gas containing nitrogen is introduced and a silicon target placed inside the treatment chamber is used to form the silicon nitride layer, and then, the sputtering gas is switched to a sputtering gas containing oxygen and the same silicon target is used to form the silicon oxide layer. Since the silicon nitride layer and the silicon oxide layer can be formed in succession without exposure to the air, an impurity such as hydrogen or moisture can be prevented from being adsorbed on a surface of the silicon nitride layer.
  • an oxide semiconductor film is formed to a thickness of 2 nm to 200 nm inclusive over the insulating layer 407.
  • the oxide semiconductor film In order for the oxide semiconductor film not to contain an impurity such as hydrogen, a hydroxyl group, or moisture as much as possible, it is preferable to preheat the substrate 400 provided with the insulating layer 407 in a preheating chamber of the sputtering apparatus before the film formation so that an impurity such as hydrogen or moisture adsorbed on the substrate 400 is eliminated, and perform exhaustion.
  • a cryopump As an exhaustion unit provided in the preheating chamber, a cryopump is preferable.
  • This preheating step is not necessarily performed. Further, this preheating may be similarly performed on the substrate 400 over which the gate insulating layer 402 has not been formed or the substrate 400 over which layers up to the source or drain electrode layer 415a and the source or drain electrode layer 415b have been formed.
  • dust attached to a surface of the insulating layer 407 is preferably removed by reverse sputtering in which an argon gas is introduced and plasma is generated.
  • the reverse sputtering refers to a method in which, without application of a voltage to a target side, a high-frequency power source is used for application of a voltage to a substrate side in an argon atmosphere to generate plasma and modify a surface.
  • a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, or the like may be used instead of an argon atmosphere.
  • the oxide semiconductor film is formed by a sputtering method. Any of the following oxide semiconductor films is used as the oxide semiconductor film: an In-Ga-Zn-O-based oxide semiconductor film, an In-Sn-Zn-O-based oxide semiconductor film, an In-Al-Zn-O-based oxide semiconductor film, a Sn-Ga-Zn-O-based oxide semiconductor film, an Al-Ga-Zn-O-based oxide semiconductor film, a Sn-Al-Zn-O-based oxide semiconductor film, an In-Zn-O-based oxide semiconductor film, a Sn-Zn-O-based oxide semiconductor film, an Al-Zn-O-based oxide semiconductor film, an In-O-based oxide semiconductor film, an In-Sn-O-based oxide semiconductor film, a Sn-O-based oxide semiconductor film, and a Zn-O-based oxide semiconductor film.
  • the oxide semiconductor film is formed by a sputtering method with the use of an In-Ga-Zn-O-based metal oxide target.
  • the oxide semiconductor film can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or an atmosphere of a rare gas (typically argon) and oxygen.
  • a target containing Si0 2 at 2 wt% to 10 wt% inclusive may be used for forming a film.
  • a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed to a concentration of several ppm or a concentration of several ppb be used as the sputtering gas for the deposition of the oxide semiconductor film.
  • a metal oxide target containing zinc oxide as its main component As a target for forming the oxide semiconductor film by a sputtering method, a metal oxide target containing zinc oxide as its main component can be used.
  • the proportion of the volume of a portion except for an area occupied by a space and the like with respect to the total volume of the metal oxide target (also referred to as the fill rate) is 90 % to 100 % inclusive, preferably, 95 % to 99.9 % inclusive.
  • the substrate is held in a treatment chamber kept under reduced pressure, a sputtering gas from which hydrogen and moisture are removed is introduced into the treatment chamber from which remaining moisture is being removed, and the oxide semiconductor film is formed over the substrate 400 with the use of a metal oxide as a target.
  • an entrapment vacuum pump is preferably used.
  • a cryopump, an ion pump, or a titanium sublimation pump is preferably used.
  • an evacuation unit may be a turbo pump provided with a cold trap.
  • a hydrogen atom, a compound containing a hydrogen atom, such as water (H 2 0), (more preferably, also a compound containing a carbon atom), and the like are removed, whereby the concentration of an impurity in the oxide semiconductor film formed in the deposition chamber can be reduced.
  • the substrate may be heated when the oxide semiconductor film is formed.
  • the oxide semiconductor film preferably has a thickness of 5 nm to 30 nm inclusive. Note that the appropriate thickness depends on an oxide semiconductor material used and the thickness may be selected as appropriate in accordance with a material.
  • a resist mask for forming the island-shaped oxide semiconductor layer 412 may be formed by an ink-jet method. Formation of the resist mask by an ink-jet method needs no photomask; thus, manufacturing cost can be reduced.
  • the etching of the oxide semiconductor film may be dry etching, wet etching, or both dry etching and wet etching.
  • etching gas for dry etching a gas containing chlorine (chlorine-based gas such as chlorine (Cl 2 ), boron chloride (BC1 3 ), silicon chloride (SiCl 4 ), or carbon tetrachloride (CC1 4 )) is preferably used.
  • a gas containing fluorine fluorine-based gas such as carbon tetrafluoride (CF ), sulfur fluoride (SF 6 ), nitrogen fluoride (NF 3 ), or trifluoromethane (CHF 3 )); hydrogen bromide (HBr); oxygen (0 2 ); any of these gases to which a rare gas such as helium (He) or argon (Ar) is added; or the like can be used.
  • fluorine-based gas such as carbon tetrafluoride (CF ), sulfur fluoride (SF 6 ), nitrogen fluoride (NF 3 ), or trifluoromethane (CHF 3 )
  • hydrogen bromide HBr
  • oxygen (0 2 ); any of these gases to which a rare gas such as helium (He) or argon (Ar) is added; or the like can be used.
  • a dry etching method a parallel plate RIE (reactive ion etching) method or an ICP (inductively coupled plasma) etching method can be used.
  • the etching condition the amount of electric power applied to a coil-shaped electrode, the amount of electric power applied to an electrode on a substrate side, the temperature of the electrode on the substrate side, or the like.
  • a mixed solution of phosphoric acid, acetic acid, and nitric acid, or the like can be used.
  • ITO07N produced by KANTO CHEMICAL CO., INC.
  • KANTO CHEMICAL CO., INC. may be used.
  • the etchant after the wet etching is removed together with the material etched off by cleaning.
  • the waste liquid including the etchant and the material etched off may be purified and the material may be reused.
  • a material such as indium contained in the oxide semiconductor layer is collected from the waste liquid after the etching and reused, the resources can be efficiently used and the cost can be reduced.
  • the etching condition (such as an etchant, etching time, temperature, or the like) is appropriately adjusted depending on the material so that the material can be etched into a desired shape.
  • the oxide semiconductor film is processed into the island-shaped oxide semiconductor layer 412 by a wet etching method with a mixed solution of phosphoric acid, acetic acid, and nitric acid as an etchant.
  • the oxide semiconductor layer 412 is subjected to first heat treatment.
  • the temperature of the first heat treatment is greater than or equal to 400 °C and less than or equal to 750 °C, preferably greater than or equal to 400 °C and less than the strain point of the substrate.
  • the substrate is introduced into an electric furnace which is one of heat treatment apparatuses, heat treatment is performed on the oxide semiconductor layer in a nitrogen atmosphere at 450 °C for one hour, and then, entry of water and hydrogen into the oxide semiconductor layer is prevented; thus, the oxide semiconductor layer is obtained.
  • dehydration or dehydrogenation of the oxide semiconductor layer 412 can be conducted.
  • the heat treatment apparatus is not limited to an electric furnace, and a device for heating an object to be processed by thermal conduction or thermal radiation from a heating element such as a resistance heating element may be used.
  • a heating element such as a resistance heating element
  • an RTA (rapid thermal anneal) apparatus such as a GRTA (gas rapid thermal anneal) apparatus or an LRTA (lamp rapid thermal anneal) apparatus
  • An LRTA apparatus is an apparatus for heating an object to be processed by radiation of light (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp.
  • a GRTA apparatus is an apparatus with which heat treatment is performed using a high-temperature gas.
  • the gas an inert gas which does not react with an object to be processed by heat treatment, like nitrogen or a rare gas such as argon is used.
  • GRTA may be performed as follows.
  • the substrate is transferred and put in an inert gas which has been heated to a high temperature of 650 °C to 700 °C, heated for several minutes, and transferred and taken out of the inert gas which has been heated to a high temperature.
  • GRTA enables a high-temperature heat treatment for a short time.
  • the purity of nitrogen or a rare gas such as helium, neon, or argon which is introduced into the heat treatment apparatus is preferably greater than or equal to 6 N (99.9999 %), more preferably greater than or equal to 7 N (99.99999 ) (i.e., the impurity concentration is preferably less than or equal to 1 ppm, more preferably less than or equal to 0.1 ppm).
  • the oxide semiconductor layer 412 may be crystallized to be a microcrystalline film or a polycrystalline film depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer.
  • the oxide semiconductor layer 412 may be crystallized to be a microcrystalline oxide semiconductor film having a degree of crystallinity of greater than or equal to 90 %, or greater than or equal to 80 %.
  • the oxide semiconductor layer 412 may be an amorphous oxide semiconductor film containing no crystalline component.
  • the oxide semiconductor layer 412 may become an oxide semiconductor film in which a microcrystalline portion (with a grain diameter of 1 nm to 20 nm inclusive, typically 2 nm to 4 nm inclusive) is mixed into an amorphous oxide semiconductor.
  • the first heat treatment can be performed on the oxide semiconductor film before being processed into the island-shaped oxide semiconductor layer 412.
  • the substrate is taken out of the heat treatment apparatus after the first heat treatment, and then a photolithography step is performed.
  • the heat treatment having an effect of dehydration or dehydrogenation with respect to the oxide semiconductor layer may be performed at any of the following timings: after the oxide semiconductor layer is formed; after a source electrode layer and a drain electrode layer are formed over the oxide semiconductor layer; and after a gate insulating layer is formed over the source electrode layer and the drain electrode layer.
  • the conductive film is formed by, for example, a sputtering method or a vacuum evaporation method.
  • a material of the conductive film an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W; an alloy containing any of these elements as its component; an alloy film containing any of these elements in combination; and the like can be given.
  • one or more materials selected from manganese, magnesium, zirconium, beryllium, and yttrium may be used.
  • the conductive film may have a single-layer structure or a layered structure of two or more layers.
  • a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked over an aluminum film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order, and the like can be given.
  • a film of one or a plurality of elements selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc) combined with Al, an alloy film containing a plurality of the above elements, or a nitride film thereof may be used.
  • a second photolithography step is performed.
  • a resist mask is formed over the conductive film and selective etching is performed, so that the source or drain electrode layer 415a and the source or drain electrode layer 415b are formed. Then, the resist mask is removed (see FIG 6B). Note that the source electrode layer and the drain electrode layer preferably have tapered shapes because coverage with the gate insulating layer stacked thereover can be improved.
  • a titanium film is formed to a thickness of 150 nm by a sputtering method for the source or drain electrode layer 415a and the source or drain electrode layer 415b.
  • a titanium film is used as the conductive film
  • an In-Ga-Zn-O-based oxide semiconductor is used as the oxide semiconductor layer 412
  • an ammonia hydrogen peroxide solution (a mixture of ammonia, water, and a hydrogen peroxide solution) is used as an etchant.
  • the resist mask for forming the source or drain electrode layer 415a and the source or drain electrode layer 415b may be formed by an ink-jet method. Formation of the resist mask by an ink-jet method needs no photomask; thus, manufacturing cost can be reduced.
  • a channel length L of the thin film transistor to be formed later depends on a width of a distance between a bottom portion of the source electrode layer and a bottom portion of the drain electrode layer which are adjacent to each other over the oxide semiconductor layer 412. Note that when light exposure is performed in the case where the channel length L is shorter than 25 nm, extreme ultraviolet with extremely short wavelengths of several nanometers to several tens of nanometers is used for light exposure for forming the resist mask in the second photolithography step. Light exposure with extreme ultraviolet leads to a high resolution and a large depth of focus.
  • the channel length L of the thin film transistor to be formed later can be set to 10 nm to 1000 nm inclusive.
  • the operation speed of a circuit can be increased, and further, an off current can be significantly small so that low power consumption can be achieved.
  • the gate insulating layer 402 is formed over the insulating layer 407, the oxide semiconductor layer 412, the source or drain electrode layer 415a, and the source or drain electrode layer 415b (see FIG 6C).
  • the gate insulating layer 402 can be formed with a single-layer structure or a layered structure using any of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, and an aluminum oxide layer by a plasma CVD method, a sputtering method, or the like.
  • the gate insulating layer 402 is preferably formed by a sputtering method so that the gate insulating layer 402 avoids containing much hydrogen.
  • a silicon oxide film is formed by a sputtering method
  • a silicon target or a quartz target is used as a target and a mixed gas of oxygen and argon is used as a sputtering gas.
  • the gate insulating layer 402 may have a structure where a silicon oxide layer and a silicon nitride layer are stacked from the side of the source or drain electrode layer 415a and the source or drain electrode layer 415b.
  • a silicon oxide layer SiO t (x > 0)
  • SiN ⁇ (y > 0) silicon nitride layer with a thickness of 50 nm to 200 nm inclusive
  • the gate insulating layer with a thickness of 100 nm may be formed.
  • a silicon oxide layer is formed to a thickness of 100 nm by an RF sputtering method under the following condition: the pressure is 0.4 Pa; the high frequency power is 1.5 kW; and the atmosphere is an atmosphere containing oxygen and argon (the flow ratio of oxygen to argon is 1:1 (each flow rate is 25 seem)).
  • a third photolithography step is performed to form a resist mask, and etching is selectively performed to remove part of the gate insulating layer 402, so that openings 421a and 421b reaching the source or drain electrode layer 415a and the source or drain electrode layer 415b are formed (see FIG 6D).
  • a resist mask may be formed by an ink-jet method. Formation of the resist mask by an ink-jet method needs no photomask; thus, manufacturing cost can be reduced.
  • the conductive film for forming the gate electrode layer 411 and the wiring layers 414a and 414b can be formed with a single-layer structure or a layered structure using any of metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium, and an alloy material containing any of these materials as its main component.
  • metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium, and an alloy material containing any of these materials as its main component.
  • a two-layer structure in which a molybdenum layer is stacked over an aluminum layer As a two-layer structure of each of the gate electrode layer 411 and the wiring layers 414a and 414b, a two-layer structure in which a molybdenum layer is stacked over an aluminum layer, a two-layer structure in which a molybdenum layer is stacked over a copper layer, a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is stacked over a copper layer, or a two-layer structure in which a titanium nitride layer and a molybdenum layer are stacked is preferable.
  • the gate electrode layer can be formed from a light-transmitting conductive film.
  • a material of the light-transmitting conductive film a light-transmitting conductive oxide or the like can be given.
  • a titanium film is formed to a thickness of 150 nm by a sputtering method for the gate electrode layer 411 and the wiring layers 414a and 414b.
  • second heat treatment (preferably 200 °C to 400 °C inclusive, for example, from 250 °C to 350 °C inclusive) is performed in an inert gas atmosphere or an oxygen gas atmosphere.
  • the second heat treatment is performed in a nitrogen atmosphere at 250 °C for one hour.
  • the second heat treatment may be performed after a protective insulating layer or a planarization insulating layer is formed over the thin film transistor 410.
  • heat treatment may be performed at 100 °C to 200 °C inclusive for one hour to 30 hours inclusive in the air.
  • This heat treatment may be performed at a fixed heating temperature.
  • the following change in the heating temperature may be conducted plural times repeatedly: the heating temperature is increased from a room temperature to a temperature of 100 °C to 200 °C inclusive and then decreased to a room temperature.
  • this heat treatment may be performed under a reduced pressure. When the heat treatment is performed under a reduced pressure, the heating time can be shortened.
  • the thin film transistor 410 including the oxide semiconductor layer 412 in which the concentration of hydrogen, moisture, hydride, or hydroxide is reduced can be formed (see FIG 6E).
  • a protective insulating layer or a planarization insulating layer for planarization may be provided over the thin film transistor 410.
  • the protective insulating layer may be formed with a single-layer structure or a layered structure using any of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, and an aluminum oxide layer.
  • the planarization insulating layer can be formed using an organic material having heat resistance, such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy. Other than such organic materials, it is also possible to use a low-dielectric constant material (a low-k material), a siloxane-based resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), or the like.
  • the planarization insulating layer may be formed by stacking a plurality of insulating films formed of these materials.
  • the siloxane-based resin corresponds to a resin including a Si-O-Si bond formed using a siloxane-based material as a starting material.
  • the siloxane-based resin may include as a substituent an organic group (e.g., an alkyl group or an aryl group) or a fluoro group.
  • the organic group may include a fluoro group.
  • planarization insulating layer can be formed, depending on the material, by a method such as a sputtering method, an SOG method, spin coating, dip coating, spray coating, or a droplet discharge method (such as an ink-jet method, screen printing, offset printing, or the like), or a tool (equipment) such as a doctor knife, a roll coater, a curtain coater, or a knife coater.
  • a method such as a sputtering method, an SOG method, spin coating, dip coating, spray coating, or a droplet discharge method (such as an ink-jet method, screen printing, offset printing, or the like), or a tool (equipment) such as a doctor knife, a roll coater, a curtain coater, or a knife coater.
  • the oxide semiconductor film can be stable.
  • the capacitor in the voltage regulator circuit according to an embodiment of the present invention can be formed through the same manufacturing steps as the transistor in this embodiment.
  • the number of manufacturing steps can be reduced.
  • the transistor can have stable electric characteristics and high reliability. Since leakage current is small in the transistor, by forming the voltage regulator circuit according to an embodiment of the present invention with the use of the transistor, a speed at which a desired voltage is achieved can be significantly increased. Further, by forming the voltage regulator circuit according to an embodiment of the present invention with the use of the transistor, the voltage regulator circuit can have stable electric characteristics and high reliability.
  • FIGS. 7A and 7B and FIGS. 8A to 8E One embodiment of a transistor and a manufacturing method of the transistor of this embodiment is described with reference to FIGS. 7A and 7B and FIGS. 8A to 8E.
  • FIG 7A and 7B illustrate an example of a planar structure and an example of a cross-sectional structure of a transistor.
  • a thin film transistor 460 illustrated in FIGS. 7A and 7B is one of top gate thin film transistors.
  • FIG. 7A is a plan view of the thin film transistor 460 having a top-gate structure and FIG. 7B is a cross-sectional view taken along D1-D2 in FIG. 7 A.
  • the thin film transistor 460 includes, over a substrate 450 having an insulating surface, an insulating layer 457, a source or drain electrode layer 465a (465al and 465a2), an oxide semiconductor layer 462, a source or drain electrode layer 465b, a wiring layer 468, a gate insulating layer 452, and a gate electrode layer 461 (461a and 461b).
  • the source or drain electrode layer 465a (465al and 465a2) is electrically connected to a wiring layer 464 through the wiring layer 468.
  • the source or drain electrode layer 465b is electrically connected to a different wiring layer through an opening formed in the gate insulating layer 452.
  • the insulating layer 457 which serves as a base film is formed over the substrate 450 having an insulating surface.
  • a silicon oxide layer is formed as the insulating layer 457 by a sputtering method.
  • the substrate 450 is transferred to a treatment chamber and a high-purity sputtering gas from which hydrogen and moisture are removed and which contains oxygen is introduced, and a silicon oxide layer is formed as the insulating layer 457 over the substrate 450 with the use of a silicon target or a quartz (preferably synthetic quartz).
  • a sputtering gas oxygen or a mixed gas of oxygen and argon is used.
  • a silicon oxide film is formed by an RF sputtering method under the following condition: quartz (preferably, synthetic quartz) with a purity of 6N is used as a target; the substrate temperature is 108 °C; the distance between the substrate and the target (the T-S distance) is 60 mm; the pressure is 0.4 Pa; the high frequency power is 1.5 kW; and the atmosphere is an atmosphere containing oxygen and argon (the flow ratio of oxygen to argon is 1:1 (each flow rate is 25 seem).
  • the thickness of the silicon oxide film is 100 nm.
  • quartz preferably, synthetic quartz
  • a silicon target can be used as a target when the silicon oxide film is formed.
  • the insulating layer 457 is preferably formed removing moisture remaining in the treatment chamber. This is for preventing hydrogen, a hydroxyl group, or moisture from being contained in the insulating layer 457.
  • a hydrogen atom, a compound containing a hydrogen atom, such as water (H 2 0), or the like is removed, whereby the concentration of an impurity in the insulating layer 457 formed in the deposition chamber can be reduced.
  • a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed to a concentration of several ppm or a concentration of several ppb, as a sputtering gas when the insulating layer 457 is formed.
  • the insulating layer 457 may have a layered structure in which for example, a nitride insulating layer such as a silicon nitride layer, a silicon nitride oxide layer, an aluminum nitride layer, or an aluminum nitride oxide layer and the oxide insulating layer are stacked in this order from the substrate 450 side.
  • a nitride insulating layer such as a silicon nitride layer, a silicon nitride oxide layer, an aluminum nitride layer, or an aluminum nitride oxide layer and the oxide insulating layer are stacked in this order from the substrate 450 side.
  • a high-purity sputtering gas from which hydrogen and moisture are removed and which contains nitrogen is introduced and a silicon target is used, whereby a silicon nitride layer is formed between a silicon oxide layer and a substrate.
  • the silicon nitride layer is preferably formed removing remaining moisture in a treatment chamber, similarly to the silicon oxide layer.
  • a conductive film is formed over the insulating layer 457 and a first photolithography step is performed.
  • a resist mask is formed over the conductive film and selective etching is performed, so that the source or drain electrode layer 465al and 465a2 is formed.
  • the resist mask is removed (see FIG. 8A). It seems in cross section as if the source or drain electrode layer 465al and 465a2 is divided; however, the source or drain electrode layer 465al and 465a2 is a continuous layer. Note that the source electrode layer and the drain electrode layer preferably have tapered shapes because coverage with the gate insulating layer stacked thereover can be improved.
  • the material of the source or drain electrode layer 465al and 465a2 there are an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, an alloy containing any of these elements as its component, an alloy containing any of these elements in combination, and the like. Further, one or more materials selected from manganese, magnesium, zirconium, beryllium, and yttrium may be used. Further, the conductive film may have a single-layer structure or a layered structure of two or more layers.
  • a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked over an aluminum film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order, and the like can be given.
  • a film of one or a plurality of elements selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc) combined with Al, an alloy film containing a plurality of the above elements, or a nitride film thereof may be used.
  • a titanium film is formed to a thickness of 150 nm by a sputtering method for the source or drain electrode layer 465al and 465a2.
  • an oxide semiconductor film is formed to a thickness of 2 nm to 200 nm inclusive over the insulating layer 457.
  • the oxide semiconductor film is processed in a second photolithography step into an island-shaped oxide semiconductor layer 462 (see FIG 8B).
  • the oxide semiconductor film is formed by a sputtering method with the use of an In-Ga-Zn-O-based metal oxide target.
  • the substrate is held in a treatment chamber kept under reduced pressure, a sputtering gas from which hydrogen and moisture are removed is introduced into the treatment chamber from which remaining moisture is being removed, and the oxide semiconductor film is deposited over the substrate 450 with the use of a metal oxide as a target.
  • an entrapment vacuum pump is preferably used.
  • a cryopump, an ion pump, or a titanium sublimation pump is preferably used.
  • an evacuation unit may be a turbo pump provided with a cold trap.
  • a hydrogen atom, a compound containing a hydrogen atom, such as water (H 2 0), (more preferably, also a compound containing a carbon atom), and the like are removed, whereby the concentration of an impurity in the oxide semiconductor film formed in the deposition chamber can be reduced.
  • the substrate may be heated when the oxide semiconductor film is formed.
  • a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed to a concentration of several ppm or a concentration of several ppb, as a sputtering gas when the oxide semiconductor film is formed.
  • the oxide semiconductor film preferably has a thickness of 5 nm to 30 nm inclusive. Note that the appropriate thickness depends on an oxide semiconductor material used and the thickness may be selected as appropriate in accordance with a material.
  • the oxide semiconductor film is processed into the island-shaped oxide semiconductor layer 462 by a wet etching method with a mixed solution of phosphoric acid, acetic acid, and nitric acid as an etchant.
  • the oxide semiconductor layer 462 is subjected to first heat treatment.
  • the temperature of the first heat treatment is greater than or equal to 400 °C and less than or equal to 750 °C, preferably greater than or equal to 400 °C and less than the strain point of the substrate.
  • the substrate is introduced into an electric furnace which is one of heat treatment apparatuses, heat treatment is performed on the oxide semiconductor layer in a nitrogen atmosphere at 450 °C for one hour, and then, entry of water and hydrogen into the oxide semiconductor layer is prevented; thus, the oxide semiconductor layer is obtained.
  • dehydration or dehydrogenation of the oxide semiconductor layer 462 can be conducted.
  • the heat treatment apparatus is not limited to an electric furnace, and may have a device for heating an object to be processed by thermal conduction or thermal radiation from a heating element such as a resistance heating element.
  • a heating element such as a resistance heating element.
  • an RTA (rapid thermal anneal) apparatus such as a GRTA (gas rapid thermal anneal) apparatus, or an LRTA (lamp rapid thermal anneal) apparatus can be used.
  • GRTA may be performed as follows. The substrate is transferred and put in an inert gas which has been heated to a high temperature of 650 °C to 700 °C, heated for several minutes, and transferred and taken out of the inert gas which has been heated to a high temperature.
  • GRTA enables a high-temperature heat treatment for a short time.
  • the purity of nitrogen or a rare gas such as helium, neon, or argon which is introduced into the heat treatment apparatus is greater than or equal to 6 N (99.9999 %), preferably greater than or equal to 7 N (99.99999 %) (i.e., the impurity concentration is less than or equal to 1 ppm, preferably less than or equal to 0.1 ppm).
  • the oxide semiconductor layer 462 may be crystallized to be a microcrystalline film or a polycrystalline film depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer.
  • the first heat treatment can be performed on the oxide semiconductor film before being processed into the island-shaped oxide semiconductor layer 462.
  • the substrate is taken out of the heat treatment apparatus after the first heat treatment, and then a photolithography step is performed.
  • the heat treatment having an effect of dehydration or dehydrogenation with respect to the oxide semiconductor layer may be performed at any of the following timings: after the oxide semiconductor layer is formed; after a source electrode and a drain electrode are formed over the oxide semiconductor layer; and after a gate insulating layer is formed over the source electrode and the drain electrode.
  • a conductive film is formed over the insulating layer 457 and the oxide semiconductor layer 462 and a third photolithography step is performed.
  • a resist mask is formed over the conductive film and selective etching is performed, so that the source or drain electrode layer 465b and the wiring layer 468 are formed. Then, the resist mask is removed (see FIG 8C).
  • the source or drain electrode layer 465b and the wiring layer 468 may be formed using a material and steps similar to those of the source or drain electrode layer 465al and 465a2.
  • a titanium film is formed to a thickness of 150 nm by a sputtering method for the source or drain electrode layer 465b and the wiring layer 468.
  • the same titanium film is used for the source or drain electrode layer 465al and 465a2 and the source or drain electrode layer 465b, so that the etching rate of the source or drain electrode layer 465al and 465a2 is the same or substantially the same as that of the source or drain electrode layer 465b. Therefore, the wiring layer 468 is provided over a portion of the source or drain electrode layer 465a2, which is not covered with the oxide semiconductor layer 462, to prevent the source or drain electrode layer 465al and 465a2 from being etched when the source or drain electrode layer 465b is etched.
  • the wiring layer 468 which protects the source or drain electrode layer 465a2 in etching is not necessarily provided.
  • the material and the etching conditions are adjusted as appropriate so that the oxide conductive layer 462 is not removed by etching of the conductive film.
  • a titanium film is used as the conductive film
  • an In-Ga-Zn-0 based oxide semiconductor is used as the oxide semiconductor layer 462
  • an ammonia hydrogen peroxide solution (a mixture of ammonia, water, and a hydrogen peroxide solution) is used as an etchant.
  • the oxide semiconductor layer 462 may be etched off, whereby an oxide semiconductor layer having a groove (a depressed portion) may be formed.
  • a resist mask used for forming the source or drain electrode layer 465b and the wiring layer 468 may be formed by an ink-jet method. Formation of the resist mask by an ink-jet method needs no photomask; thus, manufacturing cost can be reduced.
  • the gate insulating layer 452 is formed over the insulating layer 457, the oxide semiconductor layer 462, the source or drain electrode layer 465al and 465a2, the source or drain electrode layer 465b, and the wiring layer 468.
  • the gate insulating layer 452 can be formed with a single-layer structure or a layered structure using any of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, and an aluminum oxide layer by a plasma CVD method, a sputtering method, or the like. Note that the gate insulating layer 452 is preferably formed by a sputtering method so that the gate insulating layer 452 avoids containing much hydrogen. In the case where a silicon oxide film is formed by a sputtering method, a silicon target or a quartz target is used as a target and a mixed gas of oxygen and argon is used as a sputtering gas.
  • the gate insulating layer 452 may have a structure where a silicon oxide layer and a silicon nitride layer are stacked from the side of the source or drain electrode layer 465al and 465a2 and the source or drain electrode layer 465b.
  • a silicon oxide layer is formed to a thickness of 100 nm by an RF sputtering method under the following condition: the pressure is 0.4 Pa; the high frequency power is 1.5 kW; and the atmosphere is an atmosphere containing oxygen and argon (the flow ratio of oxygen to argon is 1:1 (each flow rate is 25 seem).
  • a fourth photolithography step is performed.
  • a resist mask is formed and selective etching is performed to remove part of the gate insulating layer 452, so that an opening 423 reaching the wiring layer 468 is formed (see FIG 8D).
  • an opening reaching the source or drain electrode layer 465b may be formed.
  • the opening reaching the source or drain electrode layer 465b is formed after an interlayer insulating layer is further stacked, and a wiring layer for electrical connection is formed in the opening.
  • a conductive film is formed over the gate insulating layer 452 and in the opening 423, the gate electrode layer 461 (461a and 461b) and the wiring layer 464 are formed in a fifth photolithography step.
  • a resist mask may be formed by an ink-jet method. When the resist mask is formed by an ink-jet method, a photomask is not used; therefore, manufacturing costs can be reduced.
  • the conductive film for forming the gate electrode layer 461 (461a and 461b) and the wiring layer 464 can be formed with a single layer or stacked layers using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material containing any of these materials as its main component.
  • a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material containing any of these materials as its main component.
  • a titanium film is formed to a thickness of 150 nm by a sputtering method for the gate electrode layer 461 (461a and 461b) and the wiring layer 464.
  • second heat treatment (preferably 200 °C to 400 °C inclusive, for example, from 250 °C to 350 °C inclusive) is performed in an inert gas atmosphere or an oxygen gas atmosphere.
  • the second heat treatment is performed in a nitrogen atmosphere at 250 °C for one hour.
  • the second heat treatment may be performed after a protective insulating layer or a planarization insulating layer is formed over the thin film transistor 460.
  • heat treatment may be performed at 100 °C to 200 °C inclusive for one hour to 30 hours inclusive in the air.
  • This heat treatment may be performed at a fixed heating temperature.
  • the following change in the heating temperature may be conducted plural times repeatedly: the heating temperature is increased from a room temperature to a temperature of 100 °C to 200 °C inclusive and then decreased to a room temperature.
  • this heat treatment may be performed under a reduced pressure. When the heat treatment is performed under a reduced pressure, the heating time can be shortened.
  • the thin film transistor 460 including the oxide semiconductor layer 462 in which the concentration of hydrogen, moisture, hydride, or hydroxide is reduced can be formed (see FIG 8E).
  • a protective insulating layer or a planarization insulating layer for planarization may be provided over the thin film transistor 460.
  • an opening reaching the source or drain electrode layer 465b is formed in the gate insulating layer 452 and the protective insulating layer and/or the planarization insulating layer, and a wiring layer which is electrically connected to the source or drain electrode layer 465b is formed in the opening.
  • the oxide semiconductor film can be stable.
  • the capacitor in the voltage regulator circuit according to an embodiment of the present invention can be formed through the same manufacturing steps as the transistor in this embodiment.
  • the number of manufacturing steps can be reduced.
  • the transistor can have stable electric characteristics and high reliability. Since leakage current is small in the transistor, by forming the voltage regulator circuit according to an embodiment of the present invention with the use of the transistor, a speed at which a desired voltage is achieved can be significantly increased. Further, when the voltage regulator circuit according to an embodiment of the present invention is formed with the use of the transistor, the voltage regulator circuit can have stable electric characteristics and high reliability.
  • the thin film transistors of this embodiment are described with reference to FIGS. 9A and 9B.
  • FIGS. 9 A and 9B illustrate examples of cross-sectional structures of the thin film transistors.
  • the thin film transistors 425 and 426 in FIGS. 9A and 9B are each one of thin film transistors where an oxide semiconductor layer is sandwiched between a conductive layer and a gate electrode layer.
  • a silicon substrate is used as a substrate and each of the thin film transistors 425 and 426 is provided over an insulating layer 422 which is formed over a silicon substrate 420.
  • a conductive layer 427 is formed between the insulating layer 422 and an insulating layer 407 over the silicon substrate 420 so as to overlap with at least the whole oxide semiconductor layer 412.
  • FIG 9B illustrates an example where the conductive layer between the insulating layer 422 and the insulating layer 407 is processed like a conductive layer 424 by etching and overlaps with part of the oxide semiconductor layer 412, which includes at least a channel formation region.
  • the conductive layers 427 and 424 may each be formed using a metal material which can resist temperature for heat treatment to be performed later: an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), an alloy containing any of these elements as its component, an alloy containing a combination of any of these elements, a nitride containing any of the above elements as its component, or the like.
  • a metal material which can resist temperature for heat treatment to be performed later: an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), an alloy containing any of these elements as its component, an alloy containing a combination of any of these elements, a nitride containing any of the above elements as its component, or the like.
  • the conductive layers 427 and 424 may each have either a single-layer structure or a layered structure, and for example, a single layer of a tungsten layer or a stack of a tungsten nitride layer and a tungsten layer can be used.
  • a potential of the conductive layers 427 and 424 may be the same as or different from that of the gate electrode layer 411 of the thin film transistors 425 and 426.
  • the conductive layers 427 and 424 can each also function as a second gate electrode layer.
  • the potential of the conductive layers 427 and 424 may be a fixed potential such as GND or 0 V.
  • Electric characteristics of the thin film transistors 425 and 426 can be controlled by the conductive layers 427 and 424.
  • This embodiment is not limited to the structure in which the second gate electrode layer is formed by providing the conductive layer.
  • the substrate is subjected to thermal oxidation to form a region in the substrate, and the region can also function as the second gate electrode layer.
  • the capacitor in the voltage regulator circuit according to an embodiment of the present invention can be formed through the same manufacturing steps as the transistor in this embodiment.
  • the number of manufacturing steps can be reduced.
  • the transistor can have stable electric characteristics and high reliability. Since leakage current is small in the transistor, by forming the voltage regulator circuit according to an embodiment of the present invention with the use of the transistor, a speed at which a desired voltage is achieved can be significantly increased. Further, when the voltage regulator circuit according to an embodiment of the present invention is formed with the use of the transistor, the voltage regulator circuit can have stable electric characteristics and high reliability.
  • FIGS. 10A to 10E One embodiment of a thin film transistor and a manufacturing method of the thin film transistor of this embodiment is described with reference to FIGS. 10A to 10E.
  • FIGS. 10A to 10E illustrate an example of a manufacturing method of a thin film transistor.
  • a thin film transistor 390 illustrated in FIGS. 10A to 10E is one of bottom gate thin film transistors and is also referred to as an inverted staggered thin film transistor.
  • the thin film transistor 390 is described using a single-gate thin film transistor; a multi-gate thin film transistor including a plurality of channel formation regions can be formed when needed.
  • a process of manufacturing the thin film transistor 390 over a substrate 394 is described below with reference to FIGS. 10A to 10E.
  • a gate electrode layer 391 is formed in a first photolithography step.
  • the gate electrode layer preferably has a tapered shape because coverage with a gate insulating layer stacked thereover can be improved.
  • a resist mask may be formed by an ink-jet method. Formation of the resist mask by an ink-jet method needs no photomask; thus, manufacturing cost can be reduced.
  • a substrate that can be used as the substrate 394 having an insulating surface as long as it has at least heat resistance to withstand heat treatment performed later.
  • a glass substrate formed using barium borosilicate glass, aluminoborosilicate glass, or the like can be used.
  • a glass substrate whose strain point is greater than or equal to 730 °C is preferably used.
  • a glass substrate a glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass is used, for example. Note that by containing a larger amount of barium oxide (BaO) than boron oxide (B 2 0 3 ), more practical heat-resistant glass can be obtained. Therefore, a glass substrate containing a larger amount of BaO than B 2 0 3 is preferably used.
  • a substrate formed using an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used.
  • a crystallized glass substrate or the like may be used.
  • a plastic substrate or the like can be used as appropriate.
  • a semiconductor substrate of silicon or the like can be used as the substrate.
  • An insulating film serving as a base film may be provided between the substrate 394 and the gate electrode layer 391.
  • the base film has a function of preventing diffusion of an impurity element from the substrate 394, and can be formed with a single-layer structure or a layered structure using one or more of a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film.
  • the conductive film for forming the gate electrode layer 391 can be formed with a single layer or stacked layers using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material which contains any of these materials as its main component.
  • a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material which contains any of these materials as its main component.
  • a two-layer structure of the gate electrode layer 391 for example, a two-layer structure in which a molybdenum layer is stacked over an aluminum layer, a two-layer structure in which a molybdenum layer is stacked over a copper layer, a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is stacked over a copper layer, a two-layer structure in which a titanium nitride layer and a molybdenum layer are stacked, or a two-layer structure in which a tungsten nitride layer and a tungsten layer are stacked is preferable.
  • the gate electrode layer may be formed using a light-transmitting conductive film.
  • a light-transmitting conductive oxide can be given as an example of the light-transmitting conductive film.
  • a gate insulating layer 397 is formed over the gate electrode layer 391.
  • An oxide semiconductor (a highly purified oxide semiconductor) which is made to be i-type or substantially i-type by removal of an impurity is highly sensitive to an interface state and interface electric charge; thus, an interface between the oxide semiconductor and a gate insulating layer is important. Therefore, the gate insulating layer (GI) which is in contact with the highly purified oxide semiconductor needs high quality.
  • GI gate insulating layer
  • high-density plasma CVD using microwaves (2.45 GHz) is preferable because a dense high-quality insulating film having high withstanding voltage can be formed. This is because when the highly purified oxide semiconductor is closely in contact with the high-quality gate insulating film, the interface state can be reduced and interface properties can be favorable.
  • a high-density plasma apparatus an apparatus which can realize a plasma density of greater than or equal to 1 x 10 n /cm 3 can be used.
  • plasma is generated by applying a microwave power of 3 kW to 6 kW, and the insulating film is formed.
  • a monosilane gas (S1H 4 ), nitrous oxide (N 2 0), and a rare gas are introduced into a chamber as a source gas to generate high-density plasma at a pressure of 10 Pa to 30 Pa, and the insulating film is formed over a substrate having an insulating surface, such as a glass substrate.
  • the supply of a monosilane gas is stopped, and nitrous oxide (N 2 0) and a rare gas are introduced without exposure to the air, and plasma treatment may be performed on a surface of the insulating film.
  • the plasma treatment performed on the surface of the insulating film by introducing nitrous oxide (N 2 0) and a rare gas is performed at least after the insulating film is formed.
  • the flow ratio of a monosilane gas (SiH 4 ) to nitrous oxide (N 2 0) which are introduced into the chamber is in the range of 1:10 to 1:200.
  • a rare gas which is introduced into the chamber helium, argon, krypton, xenon, or the like can be used.
  • argon which is inexpensive, is preferably used.
  • any insulating film can be used as long as film quality and properties of an interface with an oxide semiconductor of the gate insulating film are modified by heat treatment performed after deposition.
  • any insulating film can be used as long as film quality as a gate insulating film is high, interface state density with an oxide semiconductor is decreased, and a favorable interface can be formed.
  • BT test gate-bias thermal stress test
  • the impurity in the oxide semiconductor especially, hydrogen, water, or the like is removed as much as possible so that the properties of an interface with the gate insulating layer are favorable as described above. Accordingly, it is possible to obtain a thin film transistor which is stable with respect to the BT test.
  • a single layer or stacked layer can be formed using one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer (also referred to as SiO x N y , x > y > 0), a silicon nitride oxide layer (also referred to as SiNjO y , x > y > 0), and an aluminum oxide layer.
  • the gate insulating layer 397 can have a structure in which a silicon oxide layer and a silicon nitride layer are stacked.
  • a silicon oxynitride layer with a thickness of 100 nm is formed by a high-density plasma CVD method with a pressure of 30 Pa and a microwave power of 6 kW.
  • the flow ratio of a monosilane gas (SiH 4 ) to nitrous oxide (N 2 0) which are introduced into the chamber is 1:10.
  • the substrate 394 over which the gate electrode layer 391 is formed or the substrate 394 over which layers up to the gate insulating layer 397 are formed be preheated in a preheating chamber of a sputtering apparatus as pretreatment for film formation so that impurities such as hydrogen and moisture adsorbed to the substrate 394 are eliminated and exhaustion is performed.
  • the temperature for the preheating is 100 °C to 400 °C inclusive, preferably 150 °C to 300 °C inclusive.
  • a cryopump is preferable as an evacuation unit provided in the preheating chamber.
  • this preheating treatment may be omitted. Further, this preheating may be similarly performed on the substrate 394 over which layers up to a source or drain electrode layer 395a and a source or drain electrode layer 395b have been formed, before formation of the oxide insulating layer 396.
  • an oxide semiconductor film 393 is formed to a thickness of 2 nm to 200 nm inclusive over the gate insulating layer 397 (see FIG 10A).
  • the oxide semiconductor film 393 is formed by a sputtering method
  • dust attached to a surface of the gate insulating layer 397 is preferably removed by reverse sputtering in which an argon gas is introduced and plasma is generated.
  • the reverse sputtering refers to a method in which, without application of a voltage to a target side, an RF power source is used for application of a voltage to a substrate side in an argon atmosphere to generate plasma in the vicinity of the substrate and modify a surface.
  • an argon atmosphere instead of an argon atmosphere, a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, or the like may be used.
  • the oxide semiconductor film 393 is formed by a sputtering method.
  • the oxide semiconductor film 393 is formed using an In-Ga-Zn-O-based oxide semiconductor film, an In-Sn-Zn-O-based oxide semiconductor film, an In-Al-Zn-O-based oxide semiconductor film, a Sn-Ga-Zn-O-based oxide semiconductor film, an Al-Ga-Zn-O-based oxide semiconductor film, a Sn-Al-Zn-O-based oxide semiconductor film, an In-Zn-O-based oxide semiconductor film, a Sn-Zn-O-based oxide semiconductor film, an Al-Zn-O-based oxide semiconductor film, an In-O-based oxide semiconductor film, an In-Sn-O-based oxide semiconductor film, a Sn-O-based oxide semiconductor film, or a Zn-O-based oxide semiconductor film.
  • the oxide semiconductor film 393 is formed by a sputtering method with the use of an In-Ga-Zn-O-based metal oxide target. Further, the oxide semiconductor film 393 can be formed by a sputtering method in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or an atmosphere containing a rare gas (typically, argon) and oxygen. In the case of employing a sputtering method, a target containing Si0 2 at 2 wt% to 10 wt% inclusive may be used for film formation.
  • a metal oxide target containing zinc oxide as its main component can be used.
  • the fill rate of the metal oxide target is 90 % to 100 % inclusive, preferably, 95 % to 99.9 % inclusive. With the use of the metal oxide target with high fill rate, the oxide semiconductor film formed is dense.
  • the substrate is held in a treatment chamber kept under reduced pressure, and the substrate is heated to room temperature or a temperature of less than 400 °C. Then, a sputtering gas from which hydrogen and moisture are removed is introduced into the treatment chamber from which remaining moisture is being removed, and the oxide semiconductor film 393 is formed over the substrate 394 with the use of a metal oxide as a target.
  • an entrapment vacuum pump is preferably used.
  • a cryopump, an ion pump, or a titanium sublimation pump is preferably used.
  • an evacuation unit may be a turbo pump provided with a cold trap.
  • a hydrogen atom, a compound containing a hydrogen atom, such as water (H 2 0), (more preferably, also a compound containing a carbon atom), and the like are removed, whereby the concentration of an impurity in the oxide semiconductor film formed in the deposition chamber can be reduced.
  • a substrate temperature when the oxide semiconductor film 393 is formed can be greater than or equal to room temperature and less than 400 °C.
  • the deposition condition is as follows: the distance between the substrate and the target is 60 mm, the pressure is 0.6 Pa, the DC power is 0.5 kW, and the atmosphere is an oxygen atmosphere (the flow rate of oxygen is 100 %). It is preferable that a pulsed DC power source be used because powder substances generated in film formation can be reduced and the film thickness can be uniform.
  • the oxide semiconductor film preferably has a thickness of 5 nm to 30 nm inclusive. Note that 6
  • the appropriate thickness depends on an oxide semiconductor material used and the thickness may be selected as appropriate in accordance with a material.
  • the oxide semiconductor film is processed into an island-shaped oxide semiconductor layer 399 through a second photolithography step (see FIG 10B).
  • a resist mask for forming the island-shaped oxide semiconductor layer 399 may be formed using an ink-jet method. Formation of the resist mask by an ink-jet method needs no photomask; thus, manufacturing cost can be reduced.
  • the step may be performed in forming the oxide semiconductor layer 399.
  • the etching of the oxide semiconductor film 393 may be dry etching, wet etching, or both dry etching and wet etching.
  • etching gas for dry etching a gas containing chlorine (chlorine-based gas such as chlorine (Cl 2 ), boron chloride (BC1 3 ), silicon chloride (SiCl 4 ), or carbon tetrachloride (CC1 4 )) is preferably used.
  • a gas containing fluorine fluorine-based gas such as carbon tetrafluoride (CF 4 ), sulfur fluoride (SF 6 ), nitrogen fluoride (NF 3 ), or trifluoromethane (CHF 3 )), hydrogen bromide (HBr), oxygen (0 2 ), any of these gases to which a rare gas such as helium (He) or argon (Ar) is added, or the like can be used.
  • fluorine-based gas such as carbon tetrafluoride (CF 4 ), sulfur fluoride (SF 6 ), nitrogen fluoride (NF 3 ), or trifluoromethane (CHF 3 )
  • hydrogen bromide HBr
  • oxygen 0. 2
  • any of these gases to which a rare gas such as helium (He) or argon (Ar) is added, or the like can be used.
  • a parallel plate REE (reactive ion etching) method or an ICP (inductively coupled plasma) etching method can be used.
  • the etching condition the amount of electric power applied to a coil-shaped electrode, the amount of electric power applied to an electrode on a substrate side, the temperature of the electrode on the substrate side, or the like.
  • a mixed solution of phosphoric acid, acetic acid, and nitric acid, or the like can be used as an etchant used for wet etching.
  • ITO07N produced by
  • KANTO CHEMICAL CO., INC. may be used.
  • the etchant after the wet etching is removed together with the material etched off by cleaning.
  • the waste liquid including the etchant and the material etched off may be purified and the material may be reused.
  • a material such as indium contained in the oxide semiconductor layer is collected from the waste liquid after the etching and reused, the resources can be efficiently used and the cost can be reduced.
  • the etching condition (such as an etchant, etching time, or temperature) is appropriately adjusted depending on the material so that the material can be etched into a desired shape.
  • the conductive film is formed over the gate insulating layer 397 and the oxide semiconductor layer 399.
  • the conductive film may be formed by a sputtering method or a vacuum evaporation method.
  • a material of the conductive film an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W; an alloy containing any of these elements as its component; an alloy containing any of these elements in combination; and the like can be given.
  • one or more materials selected from manganese, magnesium, zirconium, beryllium, and yttrium may be used.
  • the conductive film may have a single-layer structure or a layered structure of two or more layers.
  • a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked over an aluminum film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order, and the like can be given.
  • a film of one or a plurality of elements selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc) combined with Al, an alloy film containing a plurality of the above elements, or a nitride film thereof may be used.
  • a third photolithography step is performed.
  • a resist mask is formed over the conductive film and selective etching is performed, so that the source and drain electrode layers 395a and 395b are formed. Then, the resist mask is removed (see FIG. IOC).
  • a channel length L of the thin film transistor to be formed later depends on a width of a distance between a bottom portion of the source electrode layer and a bottom portion of the drain electrode layer which are adjacent to each other over the oxide semiconductor layer 399. Note that when light exposure is performed in the case where the channel length L is shorter than 25 nm, extreme ultraviolet with extremely short wavelengths of several nanometers to several tens of nanometers is used for light exposure for forming the resist mask in the third photolithography step. Light exposure with extreme ultraviolet leads to a high resolution and a large depth of focus. Accordingly, the channel length L of the thin film transistor to be formed later can be set to 10 nm to 1000 nm inclusive. Thus, the operation speed of a circuit can be increased, and further, an off current is significantly small, so that low power consumption can be achieved.
  • the material and the etching conditions are adjusted as appropriate so that the oxide semiconductor layer 399 is not removed by etching of the conductive film.
  • a titanium film is used as the conductive film
  • an In-Ga-Zn-O-based oxide semiconductor film is used as the oxide semiconductor layer 399
  • an ammonia hydrogen peroxide solution (a mixture of ammonia, water, and a hydrogen peroxide solution) is used as an etchant.
  • the oxide semiconductor layer 399 may be etched off, whereby an oxide semiconductor layer having a groove (a depression portion) may be formed.
  • a resist mask used for forming the source and drain electrode layers 395a and 395b may be formed by an ink-jet method. Formation of the resist mask by an ink-jet method needs no photomask; thus, manufacturing cost can be reduced.
  • etching may be performed with the use of a resist mask formed using a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. Since a resist mask formed using a multi-tone mask has a plurality of thicknesses and can be further changed in shape by performing etching, the resist mask can be used in a plurality of etching steps to provide different patterns. Therefore, a resist mask corresponding to at least two kinds of different patterns can be formed by using one multi-tone mask. Thus, the number of light-exposure masks can be reduced and the number of corresponding photolithography steps can be also reduced, whereby simplification of a process can be realized.
  • plasma treatment with a gas such as N 2 0, N 2 , or Ar, water or the like adsorbed to a surface of an exposed portion of the oxide semiconductor layer may be removed.
  • plasma treatment may be performed using a mixed gas of oxygen and argon.
  • the oxide insulating layer 396 is formed without exposure to the air as an oxide insulating layer which serves as a protective insulating film and is in contact with part of the oxide semiconductor layer (see FIG 10D).
  • the oxide insulating layer 396 is formed in contact with the oxide semiconductor layer 399 in a region where the oxide semiconductor layer 399 does not overlap with the source electrode layer 395a and the drain electrode layer 395b.
  • the substrate 394 over which layers up to the island-shaped oxide semiconductor layer 399, the source electrode layer 395a, and the drain electrode layer 395b have been formed is heated to room temperature or a temperature of less than 100 °C and a high-purity sputtering gas from which hydrogen and moisture are removed and which contains oxygen is introduced, and a silicon semiconductor target is used, whereby a silicon oxide layer having a defect is formed as the oxide insulating layer 396.
  • the silicon oxide film is formed by a pulsed DC sputtering method in which the purity is 6N, a boron-doped silicon target (the resistivity is 0.01 Qcm) is used, the distance between the substrate and the target (T-S distance) is 89 mm, the pressure is 0.4 Pa, the DC power is 6 kW, and the atmosphere is an oxygen atmosphere (the oxygen flow rate is 100 %).
  • the thickness of the silicon oxide film is 300 nm.
  • quartz preferably, synthetic quartz
  • oxygen or a mixed gas of oxygen and argon is used.
  • the oxide insulating layer 396 is preferably formed removing moisture remaining in the treatment chamber. This is for preventing hydrogen, a hydroxyl group, and moisture from being contained in the oxide semiconductor layer 399 and the oxide insulating layer 396.
  • an entrapment vacuum pump is preferably used.
  • a cryopump, an ion pump, or a titanium sublimation pump is preferably used.
  • an evacuation unit may be a turbo pump provided with a cold trap.
  • a hydrogen atom, a compound containing a hydrogen atom, such as water (H 2 0), and the like are removed, whereby the concentration of an impurity in the oxide insulating layer 396 formed in the deposition chamber can be reduced.
  • oxide insulating layer 396 a silicon oxynitride layer, an aluminum oxide layer, an aluminum oxynitride layer, or the like may be used instead of the silicon oxide layer.
  • heat treatment may be performed at 100 °C to 400 °C while the oxide insulating layer 396 and the oxide semiconductor layer 399 are in contact with each other. Since the oxide insulating layer 396 in this embodiment has a lot of defects, with this heat treatment, an impurity such as hydrogen, moisture, a hydroxyl group, or hydride contained in the oxide semiconductor layer 399 can be diffused to the oxide insulating layer 396 so that the impurity in the oxide semiconductor layer 399 can be further reduced.
  • an impurity such as hydrogen, moisture, a hydroxyl group, or hydride contained in the oxide semiconductor layer 399
  • the thin film transistor 390 including the oxide semiconductor layer 392 in which the concentration of hydrogen, moisture, hydride, or hydroxide is reduced can be formed (see FIG 10E).
  • the oxide semiconductor film can be stable.
  • a protective insulating layer may be provided over the oxide insulating layer.
  • the protective insulating layer 398 is formed over the oxide insulating layer 396.
  • a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, an aluminum nitride oxide film, or the like is used as the protective insulating layer 398.
  • the substrate 394 over which layers up to the oxide insulating layer 396 have been formed is heated to a temperature of 100 °C to 400 °C, a high-purity sputtering gas from which hydrogen and moisture are removed and which contains nitrogen is introduced, and a silicon semiconductor target is used, whereby a silicon nitride film is formed as the protective insulating layer 398.
  • the protective insulating layer 398 is preferably formed removing moisture remaining in a treatment chamber, similarly to the oxide insulating layer 396.
  • the substrate 394 is heated to 100 °C to 400 °C in forming the protective insulating layer 398, whereby hydrogen or moisture contained in the oxide semiconductor layer 399 can be diffused to the oxide insulating layer 396.
  • heat treatment is not necessarily performed after formation of the oxide insulating layer 396.
  • the silicon oxide layer and the silicon nitride layer can be formed with the use of a common silicon target in the same treatment chamber. After a sputtering gas containing oxygen is introduced first, a silicon oxide layer is formed using a silicon target mounted in the treatment chamber, and then, the sputtering gas is switched to a sputtering gas containing nitrogen and the same silicon target is used to form a silicon nitride layer.
  • the silicon oxide layer and the silicon nitride layer can be formed successively without being exposed to the air, impurities such as hydrogen and moisture can be prevented from adsorbing onto a surface of the silicon oxide layer.
  • heat treatment at a temperature of 100 °C to 400 °C for diffusing hydrogen or moisture contained in the oxide semiconductor layer to the oxide insulating layer is preferably performed.
  • heat treatment may be further performed at 100 °C to 200 °C inclusive for one hour to 30 hours inclusive in the air.
  • This heat treatment may be performed at a fixed heating temperature.
  • the following change in the heating temperature may be conducted plural times repeatedly: the heating temperature is increased from a room temperature to a temperature of 100 °C to 200 °C inclusive and then decreased to a room temperature.
  • this heat treatment may be performed under a reduced pressure before formation of the oxide insulating layer 396.
  • the heat treatment is performed under a reduced pressure, the heating time can be shortened. With this heat treatment, the thin film transistor can be normally off. Therefore, reliability of the thin film transistor can be improved.
  • Moisture remaining in a reaction atmosphere is removed in forming the oxide semiconductor layer including a channel formation region over the gate insulating layer, whereby the concentration of hydrogen and hydride in the oxide semiconductor layer can be reduced.
  • 400 °C they can also be applied to manufacturing steps where a glass substrate with a thickness of less than or equal to 1 mm and a side of greater than 1 m is used. In addition, all of the above steps can be performed at a treatment temperature of less than or equal to 400 °C.
  • FIG 11 is a longitudinal cross-sectional view of an inverted staggered thin film transistor which includes an oxide semiconductor.
  • An oxide semiconductor layer 1003 is provided over a gate electrode 1001 with a gate insulating film 1002 therebetween, a source electrode 1004a and a drain electrode 1004b are provided thereover, an oxide insulating layer 1005 is provided over the source electrode 1004a and the drain electrode 1004b, and a conductive layer 1006 is provided over the oxide semiconductor layer 1003 with the oxide insulating layer 1005 therebetween.
  • FIGS. 12 A and 12B are energy band diagrams (schematic diagrams) of an A- A' section illustrated in FIG. 11.
  • FIG 12B illustrates the case where a positive potential with respect to the source is applied to the drain (VD > 0).
  • FIGS. 13A and 13B are energy band diagrams (schematic diagrams) of a B-B' section illustrated in FIG 11.
  • FIG. 13A illustrates an on state in which a positive potential (+VG) is applied to the gate (Gl) and carriers (electrons) flow between the source and the drain.
  • FIG 13B illustrates an off state in which a negative potential (-VG) is applied to the gate (Gl) and minority carriers do not flow.
  • FIG 14 illustrates the relationships between the vacuum level and the work function of a metal ( ⁇ ) and between the vacuum level and the electron affinity ( ⁇ ) of an oxide semiconductor.
  • a Fermi level exists in the conduction band.
  • a conventional oxide semiconductor is typically an n-type semiconductor, in which case the Fermi level (Ef) is away from the intrinsic Fermi level (Ei) located in the middle of a band gap and is located closer to the conduction band.
  • the oxide semiconductor layer contains a certain amount of hydrogen or water, and part of hydrogen or water serves as a donor which supplies electrons, which is known as a factor to make the oxide semiconductor layer n-type.
  • an oxide semiconductor of the present invention is an intrinsic (i-type) or a substantially intrinsic oxide semiconductor which is obtained by removing hydrogen that is an n-type impurity from an oxide semiconductor and highly purifying the oxide semiconductor such that an impurity other than a main component of the oxide semiconductor is prevented from being contained therein as much as possible.
  • a feature is that a highly purified i-type (intrinsic) semiconductor, or a semiconductor close thereto, is obtained not by adding an impurity but by removing an impurity such as hydrogen or water as much as possible. This enables the Fermi level (Ef) to be at the same level as the intrinsic Fermi level (Ei).
  • the electron affinity ( ⁇ ) is said to be 4.3 eV.
  • the work function of titanium (Ti) included in the source electrode and the drain electrode is substantially equal to the electron affinity ( ⁇ ) of the oxide semiconductor. In that case, a Schottky barrier to electrons is not formed at an interface between the metal and the oxide semiconductor.
  • a black circle ( ⁇ ) represents an electron, and when a positive potential is applied to the drain, the electron is injected into the oxide semiconductor over the barrier (h) and flows toward the drain.
  • the height of the barrier (h) changes depends on the gate voltage and the drain voltage; in the case where a positive drain voltage is applied, the height of the barrier (h) is smaller than the height of the barrier in FIG. 12A where no voltage is applied, i.e., 1/2 of the band gap (Eg).
  • the electron moves at the bottom, which is stable in terms of energy, on the oxide semiconductor side at the interface between the gate insulating film and the highly purified oxide semiconductor as illustrated in FIG. 13A.
  • the off current is less than or equal to 10 A and the subthreshold swing (S value) can be 0.1 V/dec (the thickness of the gate insulating film: 100 nm).
  • the off current of the transistor which includes a highly purified oxide semiconductor is less than or equal to 1 x 10 A that is the detection limit of a measurement device as described above.
  • An element for evaluating the characteristics is manufactured and a value of the off current (a value of less than or equal to the detection limit of the measurement device as described above) is obtained with higher accuracy. The result thereof is described below.
  • the measurement system 800 includes a capacitor 802, a transistor 804, a transistor 805, a transistor 806, and a transistor 808.
  • a transistor which is manufactured in accordance with Embodiment 4 is used as each of the transistor 804 and the transistor 808.
  • a voltage VI 1 is input to one of a source and a drain of the transistor 808, and a potential Vext bl is input to a gate of the transistor 808.
  • the potential Vext bl controls the transistor 808 to be turned on or off.
  • One of a source and a drain of the transistor 804 is electrically connected to the other of the source and the drain of the transistor 808, a voltage V12 is input to the other of the source and the drain of the transistor 804, and a potential Vext_b2 is input to a gate of the transistor 804.
  • the potential Vext_b2 controls the transistor 804 to be turned on or off.
  • the capacitor 802 has a first terminal and a second terminal.
  • the first terminal is electrically connected to one of the source and the drain of the transistor 804, and the second terminal is electrically connected to the other of the source and the drain of the transistor 804.
  • a portion where the first terminal of the capacitor 802, the other of the source and the drain of the transistor 808, one of the source and the drain of the transistor 804, and a gate of the transistor 805 are connected to each other is also referred to as a node A.
  • the voltage VI 1 is input to one of a source and a drain of the transistor 806, and a gate of the transistor 806 is electrically connected to one of the source and the drain thereof.
  • One of a source and a drain of the transistor 805 is electrically connected to the other of the source and the drain of the transistor 806, and the voltage VI 2 is input to the other of the source and the drain of the transistor 805.
  • a portion where the other of the source and the drain of the transistor 806 and one of the source and the drain of the transistor 805 are connected to each other is an output terminal.
  • the measurement system 800 outputs a potential Vout through the output terminal.
  • the value of the potential Vext bl is set to a value with which the transistor 808 is turned on, and the transistor 808 is turned on, so that the voltage Vll is applied to the node A.
  • the voltage Vll is a high potential, for example.
  • the transistor 804 is turned off.
  • the potential Vext bl is set to a value with which the transistor 808 is turned off, and the transistor 808 is turned off. Further, after the transistor 808 is turned off, the potential Vll is set to a low potential.
  • the transistor 804 is kept in an off state.
  • the potential V12 is equal to the potential Vll.
  • a measurement period of the off current is briefly described.
  • a potential of one of the source and the drain of the transistor 804 that is, the potential VI 2
  • a potential of the other of the source and the drain of the transistor 808 that is, the potential Vll
  • the potential of the node A is not fixed (in a floating state). Accordingly, electric charge flows through the transistor 804, and the amount of electric charge stored in the node A is changed as time passes.
  • the potential of the node A is changed depending on the change in the amount of electric charge stored in the node A. That is, the potential Vout that is an output potential of the output terminal is also changed.
  • FIG 16 illustrates details (a timing chart) of the relationship between the potentials in the initial period in which the potential difference is generated and the measurement period after the initial period.
  • the potential Vext_b2 is set to a potential (a high potential) with which the transistor 804 is turned on. Therefore, the potential of the node A becomes V12, that is, a low potential (such as VSS). After that, the potential Vext_b2 is set to a potential (a low potential) with which the transistor 804 is turned off, so that the transistor 804 is turned off. Next, the potential Vext bl is set to a potential (a high potential) with which the transistor 808 is turned on. Accordingly, the potential of the node A becomes Vll, that is, a high potential (such as VDD). Then, Vext bl is set to a potential with which the transistor 808 is turned off, which places the node A in a floating state and finishes the initial period.
  • the potential Vll and the potential VI 2 are set such that electric charge flows to the node A or electric charge flows out of the node A.
  • the potential Vll and the potential V12 are low potentials (VSS). Note that at the timing at which the output potential Vout is measured, it is necessary to operate an output circuit and thus temporarily make Vll a high potential (VSS) in some cases.
  • VDD high potential
  • the relationship between a potential V A of the node A and the output potential Vout is obtained before calculation of the off current. With this, the potential V A of the node A can be obtained using the output potential Vout. In accordance with the above relationship, the potential V A of the node A can be expressed as a function of the output potential Vout by the following equation.
  • V A F(Vout)
  • Electric charge Q A of the node A can be expressed by the following equation with the use of the potential V A of the node A, capacitance C A connected to the node A, and a constant (const).
  • the capacitance C A connected to the node A is the sum of the capacitance of the capacitor 802 and other capacitance.
  • the current I A of the node A can be obtained from the capacitance C A connected to the node A and the output potential Vout of the output terminal.
  • the transistor 804 and the transistor 808 were manufactured with the use of a highly purified oxide semiconductor.
  • values of the capacitance of the capacitors 802 were 100 fF, 1 pF, and 3 pF.
  • VDD was 5 V and VSS was 0 V in the measurement of this embodiment.
  • Vout was measured while the potential Vll was basically set to VSS and changed to VDD for 100 msec at intervals of 10 sec to 300 sec. At which was used in calculation of current I which flows through the element was about 30000 sec.
  • FIG 17 shows the relationship between elapsed time Time in measuring the current and the output potential Vout. The potential is changed after about 90 hours.
  • FIG 18 shows the off current which is calculated in the above measurement of the current.
  • the relationship between source-drain voltage V and off current I is shown.
  • the off current was about 40 ⁇ / ⁇ under the condition where the source-drain voltage was 4 V.
  • the off current was less than or equal to 10 ⁇ / ⁇ under the condition where the source-drain voltage was
  • FIG 19 shows the off current which is calculated in the above measurement of the current when the temperature of the transistor is 85 °C.
  • the relationship between source-drain voltage V and off current I at 85 °C is shown. According to FIG 19, the off current was less than or equal to 100 ⁇ / ⁇ under the condition where the source-drain voltage was 3.1 V.
  • the operation of the thin film transistor can be favorable.
  • the capacitor in the voltage regulator circuit according to an embodiment of the present invention can be formed through the same manufacturing steps as the transistor in this embodiment.
  • the number of manufacturing steps can be reduced.
  • the transistor can have stable electric characteristics and high reliability. Since leakage current is small in the transistor, by forming the voltage regulator circuit according to an embodiment of the present invention with the use of the transistor, a speed at which a desired voltage is achieved can be significantly increased. Further, when the voltage regulator circuit according to an embodiment of the present invention is formed with the use of the transistor, the voltage regulator circuit can have stable electric characteristics and high reliability.
  • FIGS. 20A to 20E One embodiment of a thin film transistor and a manufacturing method of the thin film transistor of this embodiment is described with reference to FIGS. 20A to 20E.
  • FIGS. 20 A to 20E illustrate an example of a manufacturing method of a thin film transistor.
  • a thin film transistor 310 illustrated in FIGS. 20A to 20E is one of bottom gate thin film transistors and is also referred to as an inverted staggered thin film transistor.
  • the thin film transistor 310 is described as a single-gate thin film transistor, a multi-gate thin film transistor including a plurality of channel formation regions can be formed when needed.
  • a process for forming the thin film transistor 310 over a substrate 300 is described below with reference to FIGS. 20A to 20E.
  • a conductive film is formed over the substrate 300 having an insulating surface, and a first photolithography step is performed thereon, so that a gate electrode layer 311 is formed.
  • a resist mask may be formed by an ink-jet method. Formation of the resist mask by an ink-jet method needs no photomask; thus, manufacturing costs can be reduced.
  • a substrate that can be used as the substrate 300 having an insulating surface as long as it has at least heat resistance to withstand heat treatment performed later.
  • a glass substrate formed using barium borosilicate glass, aluminoborosilicate glass, or the like can be used.
  • a glass substrate whose strain point is greater than or equal to 730 °C is preferably used.
  • a glass substrate a glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass is used, for example. Note that by containing a larger amount of barium oxide (BaO) than boron oxide (B 2 0 3 ), more practical heat-resistant glass can be obtained. Therefore, a glass substrate containing a larger amount of BaO than B 2 0 3 is preferably used.
  • a substrate formed using an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used.
  • a crystallized glass substrate or the like may be used.
  • a semiconductor substrate of silicon or the like can be used as the substrate.
  • an insulating film serving as a base film may be provided between the substrate 300 and the gate electrode layer 311.
  • the base film has a function of preventing diffusion of an impurity element from the substrate 300, and can be formed to have a single-layer or layered structure using one or more of a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film.
  • the conductive film for forming the gate electrode layer 311 can be formed with a single layer or stacked layers using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material which contains any of these materials as its main component.
  • a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material which contains any of these materials as its main component.
  • a two-layer structure of the gate electrode layer 31 for example, a two-layer structure in which a molybdenum layer is stacked over an aluminum layer, a two-layer structure in which a molybdenum layer is stacked over a copper layer, a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is stacked over a copper layer, a two-layer structure in which a titanium nitride layer and a molybdenum layer are stacked, or a two-layer structure in which a tungsten nitride layer and a tungsten layer are stacked is preferable.
  • a stack of a tungsten layer or a tungsten nitride layer, an alloy layer of aluminum and silicon or an alloy layer of aluminum and titanium, and a titanium nitride layer or a titanium layer is preferable.
  • a gate insulating layer 302 is formed over the gate electrode layer 311.
  • An oxide semiconductor (a highly purified oxide semiconductor) which is made to be i-type or substantially i-type by removal of an impurity is highly sensitive to an interface state and interface electric charge; thus, an interface between the oxide semiconductor and a gate insulating layer is important. Therefore, the gate insulating layer (GI) which is in contact with the highly purified oxide semiconductor layer needs high quality.
  • GI gate insulating layer
  • high-density plasma CVD using microwaves (2.45 GHz) is preferable because a dense high-quality insulating film having high withstanding voltage can be formed. This is because when the highly purified oxide semiconductor layer is closely in contact with the high-quality gate insulating layer, the interface state can be reduced and interface properties can be favorable.
  • a high-density plasma apparatus an apparatus which can realize a plasma density of greater than or equal to 1 x 10 n /cm 3 can be used.
  • plasma is generated by applying a microwave power of 3 kW to 6 kW, and the insulating film is formed.
  • a monosilane gas (SiH 4 ), nitrous oxide (N 2 0), and a rare gas are introduced into a chamber as a source gas to generate high-density plasma at a pressure of 10 Pa to 30 Pa, and the insulating film is formed over a substrate having an insulating surface, such as a glass substrate.
  • the supply of a monosilane gas is stopped, and nitrous oxide (N 2 0) and a rare gas are introduced without exposure to the air, so that plasma treatment may be performed on a surface of the insulating film.
  • the plasma treatment performed on the surface of the insulating film by introducing nitrous oxide (N 2 0) and a rare gas is performed at least after the insulating film is formed.
  • the flow ratio of a monosilane gas (SiH 4 ) to nitrous oxide (N 2 0) which are introduced into the chamber is in the range of 1:10 to 1:200.
  • a rare gas which is introduced into the chamber helium, argon, krypton, xenon, or the like can be used.
  • argon which is inexpensive, is preferably used.
  • any insulating film can be used as long as film quality and properties of an interface with an oxide semiconductor of the gate insulating film are modified by heat treatment performed after deposition.
  • any insulating film can be used as long as film quality as a gate insulating film is high, interface state density with an oxide semiconductor is decreased, and a favorable interface can be formed.
  • BT test gate-bias thermal stress test
  • a single layer or stacked layers can be formed using one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer (also referred to as SiO ⁇ N y , x > y > 0), a silicon nitride oxide layer (also referred to as SiNjOy, x > y > 0), and an aluminum oxide layer.
  • the gate insulating layer 302 can have a structure in which a silicon oxide layer and a silicon nitride layer are stacked.
  • a silicon oxynitride layer with a thickness of 100 nm is formed by a high-density plasma CVD method with a pressure of 30 Pa and a microwave power of 6 kW.
  • the flow ratio of a monosilane gas (SitL ) to nitrous oxide (N 2 0) which are introduced into the chamber is 1:10.
  • an oxide semiconductor film 330 is formed to a thickness of 2 nm to 200 nm inclusive over the gate insulating layer 302.
  • dust attached to a surface of the gate insulating layer 302 is preferably removed by reverse sputtering in which an argon gas is introduced and plasma is generated.
  • an argon atmosphere instead of an argon atmosphere, a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, or the like may be used.
  • any of the following is used as the oxide semiconductor film 330: an In-Ga-Zn-O-based oxide semiconductor film, an In-Sn-Zn-O-based oxide semiconductor film, an In-Al-Zn-O-based oxide semiconductor film, a Sn-Ga-Zn-O-based oxide semiconductor film, an Al-Ga-Zn-O-based oxide semiconductor film, a Sn-Al-Zn-O-based oxide semiconductor film, an In-Zn-O-based oxide semiconductor film, a Sn-Zn-O-based oxide semiconductor film, an Al-Zn-O-based oxide semiconductor film, an In-O-based oxide semiconductor film, an In-Sn-O-based oxide semiconductor film, a Sn-O-based oxide semiconductor film, and a Zn-O-based oxide semiconductor film.
  • the oxide semiconductor film 330 is formed by a sputtering method with the use of an In-Ga-Zn-O-based metal oxide target.
  • a cross-sectional view at this stage corresponds to FIG 20A.
  • the oxide semiconductor film 330 can be formed by a sputtering method in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or an atmosphere containing a rare gas (typically, argon) and oxygen.
  • a target containing Si0 2 at 2 wt to 10 wt inclusive may be used for film formation.
  • a metal oxide target containing zinc oxide as its main component can be used.
  • the fill rate of the metal oxide target is 90 % to 100 % inclusive, preferably, 95 % to 99.9 % inclusive. With the use of the metal oxide target with high fill rate, the oxide semiconductor film formed is dense.
  • a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed to a concentration of several ppm or a concentration of several ppb, as a sputtering gas when the oxide semiconductor film 330 is formed.
  • the substrate is held in a treatment chamber kept under reduced pressure, and the substrate temperature is set to 100 °C to 600 °C inclusive, preferably 200 °C to 400 °C inclusive. Film formation is performed while the substrate is heated, whereby the concentration of an impurity contained in the oxide semiconductor layer formed can be reduced. Further, damages due to sputtering can be reduced. Then, a sputtering gas from which hydrogen and moisture are removed is introduced into the treatment chamber from which remaining moisture is being removed, and the oxide semiconductor film 330 is formed over the substrate 300 with the use of a metal oxide as a target. To remove moisture remaining in the treatment chamber, an entrapment vacuum pump is preferably used.
  • a cryopump for example, a cryopump, an ion pump, or a titanium sublimation pump is preferably used.
  • an evacuation unit may be a turbo pump provided with a cold trap.
  • a hydrogen atom, a compound containing a hydrogen atom, such as water (H 2 0), (more preferably, also a compound containing a carbon atom), and the like are removed, whereby the concentration of an impurity in the oxide semiconductor film formed in the deposition chamber can be reduced.
  • the oxide semiconductor film preferably has a thickness of 5 nm to 30 nm inclusive. Note that the appropriate thickness depends on an oxide semiconductor material used and the thickness may be selected as appropriate in accordance with a material.
  • the oxide semiconductor film 330 is processed into an island-shaped oxide semiconductor layer 331 through a second photolithography step.
  • a resist mask for forming the island-shaped oxide semiconductor layer 331 may be formed by an ink-jet method. Formation of the resist mask by an ink-jet method needs no photomask; thus, manufacturing cost can be reduced.
  • the oxide semiconductor layer is subjected to first heat treatment.
  • first heat treatment dehydration or dehydrogenation of the oxide semiconductor layer can be conducted.
  • the temperature of the first heat treatment is greater than or equal to 400 °C and less than or equal to 750 °C, preferably greater than or equal to 400 °C and less than the strain point of the substrate.
  • the substrate is introduced into an electric furnace which is one of heat treatment apparatuses, heat treatment is performed on the oxide semiconductor layer in a nitrogen atmosphere at 450 °C for one hour, and then, entry of water and hydrogen into the oxide semiconductor layer is prevented; thus, an oxide semiconductor layer 331 is obtained (see FIG 20B).
  • the heat treatment apparatus is not limited to an electric furnace, and may have a device for heating an object to be processed by thermal conduction or thermal radiation from a heating element such as a resistance heating element.
  • a heating element such as a resistance heating element.
  • an RTA (rapid thermal anneal) apparatus such as a GRTA (gas rapid thermal anneal) apparatus, or an LRTA (lamp rapid thermal anneal) apparatus can be used.
  • An LRTA apparatus is an apparatus for heating an object to be processed by radiation of light (an electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp.
  • a GRTA apparatus is an apparatus with which heat treatment is performed using a high-temperature gas.
  • the gas an inert gas which does not react with an object to be processed by heat treatment, like nitrogen or a rare gas such as argon is used.
  • GRTA may be performed as follows.
  • the substrate is transferred and put in an inert gas which has been heated to a high temperature of 650 °C to 700 °C, heated for several minutes, and transferred and taken out of the inert gas which has been heated to a high temperature.
  • GRTA enables a high-temperature heat treatment for a short time.
  • the purity of nitrogen or a rare gas such as helium, neon, or argon which is introduced into the heat treatment apparatus is preferably greater than or equal to 6 N (99.9999 %), more preferably greater than or equal to 7 N (99.99999 ) (i.e., the impurity concentration is preferably less than or equal to 1 ppm, more preferably less than or equal to 0.1 ppm).
  • the oxide semiconductor layer may be crystallized to be a microcrystalline film or a polycrystalline film in some cases.
  • the oxide semiconductor layer may be crystallized to be a microcrystalline oxide semiconductor film having a degree of crystallinity of greater than or equal to 90 %, or greater than or equal to 80 %.
  • the oxide semiconductor layer may be an amorphous oxide semiconductor film containing no crystalline component.
  • the oxide semiconductor layer may become an oxide semiconductor film in which a microcrystalline portion (with a grain diameter of 1 nm to 20 nm inclusive, typically 2 nm to 4 nm inclusive) is mixed into an amorphous oxide semiconductor.
  • the first heat treatment may be performed on the oxide semiconductor film 330 before being processed into the island-like oxide semiconductor layer.
  • the substrate is taken out of the heat treatment apparatus after the first heat treatment, and then a photolithography step is performed.
  • the heat treatment having an effect of dehydration or dehydrogenation of the oxide semiconductor layer may be performed at any of the following timings: after the oxide semiconductor layer is formed; after a source electrode and a drain electrode are formed over the oxide semiconductor layer; and after a protective insulating film is formed over the source electrode and the drain electrode.
  • the formation of the contact hole may be performed before or after the dehydration or dehydrogenation of the oxide semiconductor layer 331.
  • the etching of the oxide semiconductor film may be dry etching, without limitation to wet etching.
  • the etching conditions (such as an etchant, etching time, and temperature) are appropriately adjusted depending on the material so that the material can be etched into a desired shape.
  • the conductive film is formed over the gate insulating layer 302 and the oxide semiconductor layer 331.
  • the conductive film may be formed by a sputtering method or a vacuum evaporation method.
  • a material of the conductive film an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W; an alloy containing any of these elements as its component; an alloy containing any of these elements in combination; and the like can be given.
  • one or more materials selected from manganese, magnesium, zirconium, beryllium, and yttrium may be used.
  • the conductive film may have a single-layer structure or a layered structure of two or more layers.
  • a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked over an aluminum film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order, and the like can be given.
  • a film of one or a plurality of elements selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc) combined with Al, an alloy film containing a plurality of the above elements, or a nitride film thereof may be used.
  • the conductive film preferably has heat resistance high enough to withstand the heat treatment.
  • a third photolithography step is performed.
  • a resist mask is formed over the conductive film and selective etching is performed, so that a source electrode layer 315a and a drain electrode layer 315b are formed. Then, the resist mask is removed (see FIG 20C).
  • a channel length L of the thin film transistor to be formed later depends on a width of a distance between a bottom portion of the source electrode layer and a bottom portion of the drain electrode layer which are adjacent to each other over the oxide semiconductor layer 331. Note that when light exposure is performed in the case where the channel length L is shorter than 25 nm, extreme ultraviolet with extremely short wavelengths of several nanometers to several tens of nanometers is used for light exposure for forming the resist mask in the third photolithography step. Light exposure with extreme ultraviolet leads to a high resolution and a large depth of focus.
  • the channel length L of the thin film transistor to be formed later can be set to 10 nm to 1000 nm inclusive.
  • the operation speed of a circuit can be increased, and further, an off current is significantly small, so that low power consumption can be achieved.
  • each material and etching condition are adjusted as appropriate so that the oxide semiconductor layer 331 is not removed by etching of the conductive film.
  • a titanium film is used as the conductive film
  • an In-Ga-Zn-O-based oxide semiconductor is used as the oxide semiconductor layer 331
  • an ammonia hydrogen peroxide solution (a mixture of ammonia, water, and a hydrogen peroxide solution) is used as an etchant.
  • a resist mask used for forming the source electrode layer 315a and the drain electrode layer 315b may be formed by an ink-jet method. Formation of the resist mask by an ink-jet method needs no photomask; thus, manufacturing cost can be reduced.
  • oxide conductive layers may be formed between the oxide semiconductor layer and the source and drain electrode layers.
  • the oxide conductive layers and the metal layer for forming the source and drain electrode layers can be formed successively.
  • the oxide conductive layers can function as a source region and a drain region.
  • the oxide conductive layers are provided as a source region and a drain region between the oxide semiconductor layer and the source and drain electrode layers, the resistance of the source region and the drain region can be decreased and high-speed operation of the transistor can be realized.
  • etching may be performed with the use of a resist mask formed using a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. Since a resist mask formed using a multi-tone mask has a plurality of thicknesses and can be further changed in shape by performing etching, the resist mask can be used in a plurality of etching steps to provide different patterns. Therefore, a resist mask corresponding to at least two kinds of different patterns can be formed by using a multi-tone mask. Thus, the number of light-exposure masks can be reduced and the number of corresponding photolithography steps can be also reduced, whereby simplification of a process can be realized.
  • plasma treatment is performed using a gas such as N 2 0, N 2 , or Ar. This plasma treatment removes water or the like adsorbed on a surface of the oxide semiconductor layer which is exposed.
  • plasma treatment may be performed using a mixed gas of oxygen and argon.
  • an oxide insulating layer 316 which functions as a protective insulating film which is in contact with part of the oxide semiconductor layer is formed without exposure to air.
  • the oxide insulating layer 316 can be formed to a thickness at least 1 nm by a sputtering method or the like as appropriate, which is a method with which an impurity such as 1 water or hydrogen does not enter the oxide insulating layer 316.
  • a sputtering method or the like as appropriate, which is a method with which an impurity such as 1 water or hydrogen does not enter the oxide insulating layer 316.
  • a 200-nm-thick silicon oxide film is deposited as the oxide insulating layer 316 by a sputtering method.
  • the substrate temperature in film formation may be room temperature to 300 °C inclusive and is 100 °C in this embodiment.
  • the silicon oxide film can be formed by a sputtering method under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or an atmosphere containing a rare gas (typically argon) and oxygen.
  • a silicon oxide target or a silicon target can be used as a target.
  • the silicon oxide film can be formed by a sputtering method using a silicon target in an atmosphere containing oxygen and nitrogen.
  • the oxide insulating layer 316 which is formed in contact with the oxide semiconductor layer in a region which is in an oxygen-deficient state and thus has a lower resistance, i.e., is n-type is formed using an inorganic insulating film that does not contain impurities such as moisture, a hydrogen ion, and OH " and blocks entry of such impurities from the outside, typically, a silicon oxide film, a silicon oxynitride ' film, an aluminum oxide film, or an aluminum oxynitride film.
  • the oxide insulating layer 316 is preferably formed removing moisture remaining in the treatment chamber. This is for preventing hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor layer 331 and the oxide insulating layer 316.
  • an entrapment vacuum pump is preferably used.
  • a cryopump, an ion pump, or a titanium sublimation pump is preferably used.
  • an evacuation unit may be a turbo pump provided with a cold trap.
  • a hydrogen atom, a compound containing a hydrogen atom, such as water (H 2 0), and the like are removed, whereby the concentration of an impurity in the oxide insulating layer 316 formed in the deposition chamber can be reduced.
  • a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed to a concentration of several ppm or a concentration of several ppb, as a sputtering gas when the oxide insulating layer 316 is formed.
  • second heat treatment (preferably 200 °C to 400 °C inclusive, for example, from 250 °C to 350 °C inclusive) may be performed in an inert gas atmosphere or an oxygen gas atmosphere.
  • the second heat treatment is performed in a nitrogen atmosphere at 250 °C for one hour.
  • heat is applied while part of the oxide semiconductor layer (a channel formation region) is in contact with the oxide insulating layer 316.
  • the oxide semiconductor layer comes to be in an oxygen-deficient state and have lower resistance, that is, be n-type when heat treatment for dehydration or dehydrogenation is performed on the formed oxide semiconductor film. Then, the oxide insulating layer is formed in contact with the oxide semiconductor layer. Accordingly, part of the oxide semiconductor layer is selectively in an oxygen excess state. As a result, a channel formation region 313 overlapping with the gate electrode layer 311 becomes i-type.
  • a high-resistance source region 314a which has higher carrier concentration than at least the channel formation region 313 and overlaps with the source electrode layer 315a and a high-resistance drain region 314b which has higher carrier concentration than at least the channel formation region 313 and overlaps with the drain electrode layer 315b are formed in a self-aligned manner.
  • the thin film transistor 310 is formed (see FIG. 20D).
  • the heat treatment may be performed at 100 °C to 200 °C inclusive for one hour to 30 hours inclusive in the air.
  • the heat treatment is performed at 150 °C for 10 hours.
  • This heat treatment may be performed at a fixed heating temperature.
  • the following change in the heating temperature may be conducted plural times repeatedly: the heating temperature is increased from a room temperature to a temperature of 100 °C to 200 °C inclusive and then decreased to a room temperature.
  • this heat treatment may be performed before formation of the oxide insulating film under a reduced pressure.
  • the heat treatment time can be shortened. With such heat treatment, a normally-off thin film transistor can be obtained. Therefore, reliability of the thin film transistor can be improved.
  • the impurity contained in the oxide semiconductor layer can be reduced more effectively by the above heat treatment.
  • the high-resistance drain region 314b (or the high-resistance source region 314a) in part of the oxide semiconductor layer, which overlaps with the drain electrode layer 315b (or the source electrode layer 315a), reliability of the thin film transistor can be improved.
  • a structure can be attained in which conductivity can be varied stepwise from the drain electrode layer 315b to the high-resistance drain region 314b and the channel formation region 313.
  • the high-resistance drain region 314b serves as a buffer and a high electric field is not applied locally even if the high electric field is applied between the gate electrode layer 311 and the drain electrode layer 315b, so that the withstanding voltage of the transistor can be improved.
  • the high-resistance source region or the high-resistance drain region in the oxide semiconductor layer is formed in the entire thickness direction in the case where the thickness of the oxide semiconductor layer is less than or equal to 15 nm.
  • the thickness of the oxide semiconductor layer is 30 nm to 50 nm inclusive, in part of the oxide semiconductor layer, that is, in a region in the oxide semiconductor layer which is in contact with the source electrode layer or the drain electrode layer and the vicinity thereof, the resistance is reduced and a region in the oxide semiconductor layer, which is close to the gate insulating film, can be made to be i-type.
  • a protective insulating layer may be additionally formed over the oxide insulating layer 316.
  • a silicon nitride film is formed by an RF sputtering method.
  • An RF sputtering method has superiority in mass production and thus is a preferable method for forming the protective insulating layer.
  • the protective insulating layer is formed using an inorganic insulating film which does not contain an impurity such as moisture, a hydrogen ion, or OH " and blocks entry of these from the outside; for example, a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, an aluminum nitride oxide film, or the like is used.
  • a protective insulating layer 303 is formed using a silicon nitride film as the protective insulating layer (see FIG 20E).
  • a silicon nitride film is formed by heating the substrate 300 over which layers up to and including the oxide insulating layer 316 are formed, to a temperature of 100 °C to 400 °C, introducing a high-purity sputtering gas which contains nitrogen and from which hydrogen and moisture are removed, and using a target of a silicon semiconductor.
  • the protective insulating layer 303 is preferably formed removing moisture remaining in a treatment chamber, similarly to the oxide insulating layer 316.
  • a planarization insulating layer for planarization may be provided over the protective insulating layer 303.
  • a conductive layer may be formed so as to overlap with the oxide semiconductor layer, over the protective insulating layer 303 (in the case of providing a planarization insulating layer, over the planarization insulating layer).
  • a potential of the conductive layer may be the same as or different from that of the gate electrode layer 311 of the thin film transistor 310.
  • the conductive layer can also function as a second gate electrode layer.
  • the potential of the conductive layer may be a fixed potential such as GND or 0 V.
  • Electric characteristics of the thin film transistor 310 can be controlled by the conductive layer.
  • the capacitor in the voltage regulator circuit according to an embodiment of the present invention can be formed through the same manufacturing steps as the transistor in this embodiment.
  • the number of manufacturing steps can be reduced.
  • the transistor can have stable electric characteristics and high reliability. Since leakage current is small in the transistor, by forming the voltage regulator circuit according to an embodiment of the present invention with the use of the transistor, a speed at which a desired voltage is achieved can be significantly increased. Further, when the voltage regulator circuit according to an embodiment of the present invention is formed with the use of the transistor, the voltage regulator circuit can have stable electric characteristics and high reliability.
  • FIGS. 21A to 21D One embodiment of a thin film transistor and a manufacturing method of the thin film transistor of this embodiment is described with reference to FIGS. 21A to 21D.
  • FIGS. 21A to 21D illustrate an example of a manufacturing method of a thin film transistor.
  • a thin film transistor 360 illustrated in FIGS. 21A to 21D is a kind of bottom-gate structure called a channel-protective type (channel-stop type) and is also called an inverted staggered thin film transistor.
  • the thin film transistor 360 is described as a single-gate thin film transistor, a multi-gate thin film transistor including a plurality of channel formation regions can be formed when needed.
  • a conductive film is formed over the substrate 320 having an insulating surface, and a first photolithography step is performed thereon, so that a gate electrode layer 361 is formed.
  • a resist mask may be formed by an ink-jet method. Formation of the resist mask by an ink-jet method needs no photomask; thus, manufacturing cost can be reduced.
  • the conductive film for forming the gate electrode layer 361 can be formed in a single layer or a stacked layer using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material which contains any of these materials as its main component.
  • a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material which contains any of these materials as its main component.
  • a gate insulating layer 322 is formed over the gate electrode layer 361.
  • An oxide semiconductor (a highly purified oxide semiconductor) which is made to be i-type or substantially i-type by removal of an impurity is highly sensitive to an interface state and interface electric charge; thus, an interface between the oxide semiconductor and a gate insulating layer is important. Therefore, the gate insulating layer (GI) which is in contact with the highly purified oxide semiconductor layer needs high quality.
  • GI gate insulating layer
  • high-density plasma CVD using microwaves (2.45 GHz) is preferable because a dense high-quality insulating film having high withstanding voltage can be formed. This is because when the highly purified oxide semiconductor is closely in contact with the high-quality gate insulating film, the interface state can be reduced and interface properties can be favorable.
  • a high-density plasma apparatus an apparatus which can realize a plasma density of greater than or equal to 1 x 10 n /cm 3 can be used.
  • plasma is generated by applying a microwave power of 3 kW to 6 kW, and the insulating film is formed.
  • a monosilane gas (SiH 4 ), nitrous oxide (N 2 0), and a rare gas are introduced into a chamber as a source gas to generate high-density plasma at a pressure of 10 Pa to 30 Pa, and the insulating film is formed over a substrate having an insulating surface, such as a glass substrate.
  • the supply of a monosilane gas is stopped, and nitrous oxide (N 2 0) and a rare gas are introduced without exposure to the air, so that plasma treatment may be performed on a surface of the insulating film.
  • the plasma treatment performed on the surface of the insulating film by introducing nitrous oxide (N 2 0) and a rare gas is performed at least after the insulating film is formed.
  • the flow ratio of a monosilane gas (S1H 4 ) to nitrous oxide (N 2 0) which are introduced into the chamber is in the range of 1:10 to 1:200.
  • a rare gas which is introduced into the chamber helium, argon, krypton, xenon, or the like can be used.
  • argon which is inexpensive, is preferably used.
  • any insulating film can be used as long as film quality and properties of an interface with an oxide semiconductor of the gate insulating film are modified by heat treatment performed after deposition.
  • any insulating film can be used as long as film quality as a gate insulating film is high, interface state density with an oxide semiconductor is decreased, and a favorable interface can be formed.
  • BT test gate-bias thermal stress test
  • a single layer or stacked layer can be formed using one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer (also referred to as SiO ⁇ N y , J > y > 0), a silicon nitride oxide layer (also referred to as SiNjOy, x > y > 0), and an aluminum oxide layer.
  • the gate insulating layer 322 can have a structure in which a silicon oxide layer and a silicon nitride layer are stacked.
  • a silicon oxynitride layer with a thickness of 100 nm is formed by a high-density plasma CVD method with a pressure of 30 Pa and a microwave power of 6 kW.
  • the flow ratio of a monosilane gas (SiHU) to nitrous oxide (N 2 0) which are introduced into the chamber is 1:10.
  • an oxide semiconductor film is formed to a thickness of 2 nm to 200 nm inclusive over the gate insulating layer 322, and then, the oxide semiconductor film is processed into an island-shaped oxide semiconductor layer through a second photolithography step.
  • the oxide semiconductor film is formed by a sputtering method with the use of an In-Ga-Zn-O-based metal oxide target.
  • the oxide semiconductor film is preferably formed removing moisture remaining in the treatment chamber. This is for preventing hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor film.
  • an entrapment vacuum pump is preferably used.
  • a cryopump, an ion pump, or a titanium sublimation pump is preferably used.
  • an evacuation unit may be a turbo pump provided with a cold trap.
  • a hydrogen atom, a compound containing a hydrogen atom, such as water (H 2 0), and the like are removed, whereby the concentration of an impurity in the oxide semiconductor film formed in the deposition chamber can be reduced.
  • a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed to a concentration of several ppm or a concentration of several ppb, as a sputtering gas when the oxide semiconductor film is formed.
  • the temperature of first heat treatment for dehydration or dehydrogenation is greater than or equal to 400 °C and less than or equal to 750 °C, preferably greater than or equal to 400 °C and less than the strain point of the substrate.
  • the substrate is put in an electric furnace which is a kind of heat treatment apparatus and heat treatment is performed on the oxide semiconductor layer in a nitrogen atmosphere at 450 °C for one hour, and then water or hydrogen is prevented from entering the oxide semiconductor layer. In this manner, an oxide semiconductor layer 332 is obtained (see FIG 21 A).
  • plasma treatment is performed using a gas such as N 2 0, N 2 , or Ar. This plasma treatment removes water or the like adsorbed on a surface of the oxide semiconductor layer which is exposed.
  • plasma treatment may be performed using a mixed gas of oxygen and argon.
  • an oxide insulating layer is formed over the gate insulating layer 322 and the oxide semiconductor layer 332.
  • a resist mask is formed through a third photolithography step, the oxide insulating layer is selectively etched to form an oxide insulating layer 366, and then, the resist mask is removed.
  • a 200-nm-thick silicon oxide film is deposited as the oxide insulating layer 366 by a sputtering method.
  • the substrate temperature in film formation may be room temperature to 300 °C inclusive and is 100 °C in this embodiment.
  • the silicon oxide film can be formed by a sputtering method under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or an atmosphere containing a rare gas (typically argon) and oxygen.
  • a silicon target can be used as a target.
  • the silicon oxide film can be formed by a sputtering method using a silicon target in an atmosphere containing oxygen and nitrogen.
  • the oxide insulating layer 366 which is formed in contact with the oxide semiconductor layer in a region which is in an oxygen-deficient state and thus has a lower resistance, i.e., becomes n-type is formed using an inorganic insulating film that does not contain impurities such as moisture, a hydrogen ion, and OH " and blocks entry of such impurities from the outside, typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film.
  • the oxide insulating layer 366 is preferably formed removing moisture remaining in the treatment chamber. This is for preventing hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor layer 332 and the oxide insulating layer 366.
  • an entrapment vacuum pump is preferably used.
  • a cryopump, an ion pump, or a titanium sublimation pump is preferably used.
  • an evacuation unit may be a turbo pump provided with a cold trap.
  • a hydrogen atom, a compound containing a hydrogen atom, such as water (H 2 0), and the like are removed, whereby the concentration of an impurity in the oxide insulating layer 366 formed in the deposition chamber can be reduced.
  • a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed to a concentration of several ppm or a concentration of several ppb, as a sputtering gas when the oxide insulating layer 366 is formed.
  • second heat treatment may be performed in an inert gas atmosphere or an oxygen gas atmosphere (preferably 200 °C to 400 °C inclusive, for example 250 °C to 350 °C inclusive).
  • the second heat treatment is performed in a nitrogen atmosphere at 250 °C for one hour.
  • heat is applied while part of the oxide semiconductor layer (a channel formation region) is in contact with the oxide insulating layer 366.
  • the oxide semiconductor layer 332 which is partly exposed by providing the oxide insulating layer 366 is further subjected to heat treatment in a nitrogen atmosphere or an inert gas atmosphere or under a reduced pressure.
  • heat treatment in a nitrogen atmosphere or an inert gas atmosphere or under a reduced pressure, the resistance of the exposed region of the oxide semiconductor layer 332, which is not covered by the oxide insulating layer 366, can be decreased.
  • the heat treatment is performed at 250 °C in a nitrogen atmosphere for one hour.
  • the resistance of the exposed region of the oxide semiconductor layer 332 is decreased, so that an oxide semiconductor layer 362 including regions with different resistances (indicated as a shaded region and a white region in FIG. 21B) is formed.
  • a conductive film is formed over the gate insulating layer 322, the oxide semiconductor layer 362, and the oxide insulating layer 366.
  • a resist mask is formed through a fourth photolithography step, the conductive film is selectively etched to form a source electrode layer 365a and a drain electrode layer 365b, and then, the resist mask is removed (see FIG 21C).
  • the source and drain electrode layers 365a and 365b As a material of the source and drain electrode layers 365a and 365b, an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W; an alloy containing any of the above elements as its component; an alloy containing any of these elements in combination; and the like can be given. Further, the conductive film may have a single-layer structure or a stacked-layer structure of two or more layers.
  • the oxide semiconductor layer comes to be in an oxygen-deficient state and thus has a lower resistance, that is, comes to be n-type when heat treatment for dehydration or dehydrogenation is performed on the formed oxide semiconductor film.
  • the oxide insulating layer is formed in contact with the oxide semiconductor layer. Accordingly, part of the oxide semiconductor layer is selectively in an oxygen excess state. As a result, the channel formation region 363 overlapping with the gate electrode layer 361 becomes i-type.
  • a high-resistance source region 364a which has higher carrier concentration than at least the channel formation region 363 and overlaps with the source electrode layer 365a and a high-resistance drain region 364b which has higher carrier concentration than at least the channel formation region 363 and overlaps with the drain electrode layer 365b are formed in a self-aligned manner.
  • the thin film transistor 360 is formed.
  • heat treatment may be performed at 100 °C to 200 °C inclusive for one hour to 30 hours inclusive in air.
  • the heat treatment is performed at 150 °C for 10 hours.
  • This heat treatment may be performed at a fixed heating temperature.
  • the following change in the heating temperature may be conducted plural times repeatedly: the heating temperature is increased from a room temperature to a temperature of 100 °C to 200 °C inclusive and then decreased to a room temperature.
  • this heat treatment may be performed before formation of the oxide insulating film under a reduced pressure. When the heat treatment is performed under the reduced pressure, the heat treatment time can be shortened. With such heat treatment, hydrogen is introduced from the oxide semiconductor layer to the oxide insulating layer; thus, a normally-off thin film transistor can be obtained. Therefore, reliability of the thin film transistor can be improved.
  • the high-resistance drain region 364b (or the high-resistance source region 364a) in part of the oxide semiconductor layer, which overlaps with the drain electrode layer 365b (or the source electrode layer 365a), reliability of the thin film transistor can be improved. Specifically, with the formation of the high-resistance drain region 364b, the conductivity can be gradually varied from the drain electrode layer 365b to the high-resistance drain region 364b and the channel formation region 363.
  • the high-resistant drain region 364b serves as a buffer and a high electric field is not applied locally even if the high electric field is applied between the gate electrode layer 361 and the drain electrode layer 365b, so that the withstanding voltage of the transistor can be improved.
  • a protective insulating layer 323 is formed over the source electrode layer 365a, the drain electrode layer 365b, and the oxide insulating layer 366.
  • the protective insulating layer 323 is formed using a silicon nitride film (see FIG. 21D).
  • An oxide insulating layer may be formed over the source electrode layer 365a, the drain electrode layer 365b, and the oxide insulating layer 366, and the protective insulating layer 323 may be stacked over the oxide insulating layer.
  • the transistor can have stable electric characteristics and high reliability. Since leakage current is small in the transistor, by forming the voltage regulator circuit according to an embodiment of the present invention with the use of the transistor, a speed at which a desired voltage is achieved can be significantly increased. Further, when the voltage regulator circuit according to an embodiment of the present invention is formed with the use of the transistor, the voltage regulator circuit can have stable electric characteristics and high reliability.
  • the capacitor in the voltage regulator circuit according to an embodiment of the present invention can be formed through the same manufacturing steps as the transistor in this embodiment.
  • the number of manufacturing steps can be reduced.
  • FIGS. 22 A to 22D One embodiment of a thin film transistor and a manufacturing method of the thin film transistor of this embodiment is described with reference to FIGS. 22 A to 22D.
  • a thin film transistor 350 is described using a single-gate thin film transistor; a multi-gate thin film transistor including a plurality of channel formation regions can be formed when needed.
  • a manufacturing process of the thin film transistor 350 over a substrate 340 is described below with reference to FIGS. 22A to 22D.
  • a conductive film is formed over the substrate 340 having an insulating surface, and a first photolithography step is performed thereon, so that a gate electrode layer 351 is formed.
  • a 150-nm-thick tungsten film is formed by a sputtering method as the gate electrode layer 351.
  • a gate insulating layer 342 is formed over the gate electrode layer 351.
  • An oxide semiconductor (a highly purified oxide semiconductor) which is made to be i-type or substantially i-type by removal of an impurity is highly sensitive to an interface state and interface electric charge; thus, an interface between the oxide semiconductor and a gate insulating layer is important. Therefore, the gate insulating layer (GI) which is in contact with the highly purified oxide semiconductor needs high quality.
  • GI gate insulating layer
  • high-density plasma CVD using microwaves (2.45 GHz) is preferable because a dense high-quality insulating film having high withstanding voltage can be formed. This is because when the highly purified oxide semiconductor is closely in contact with the high-quality gate insulating film, the interface state can be reduced and interface properties can be favorable.
  • a high-density plasma apparatus an apparatus which can realize a plasma density of greater than or equal to 1 x 10 n /cm 3 can be used.
  • plasma is generated by applying a microwave power of 3 kW to 6 kW, and the insulating film is formed.
  • a monosilane gas (S1H 4 ), nitrous oxide (N 2 0), and a rare gas are introduced into a chamber as a source gas to generate high-density plasma at a pressure of 10 Pa to 30 Pa, and the insulating film is formed over a substrate having an insulating surface, such as a glass substrate.
  • the supply of a monosilane gas is stopped, and nitrous oxide (N 2 0) and a rare gas are introduced without exposure to the air, so that plasma treatment may be performed on a surface of the insulating film.
  • the plasma treatment performed on the surface of the insulating film by introducing nitrous oxide (N 2 0) and a rare gas is performed at least after the insulating film is formed.
  • the flow ratio of a monosilane gas (SiH 4 ) to nitrous oxide (N 2 0) which are introduced into the chamber is in the range of 1:10 to 1:200.
  • a rare gas which is introduced into the chamber helium, argon, krypton, xenon, or the like can be used.
  • argon which is inexpensive, is preferably used.
  • any insulating film can be used as long as film quality and properties of an interface with an oxide semiconductor of the gate insulating film are modified by heat treatment performed after deposition.
  • any insulating film can be used as long as film quality as a gate insulating film is high, interface state density with an oxide semiconductor is decreased, and a favorable interface can be formed.
  • the impurity and the main component of the oxide semiconductor is broken by a high electric field (B: bias) and high temperature (T: temperature), so that a generated dangling bond induces a shift in the threshold voltage (V th ).
  • B bias
  • T temperature
  • V th threshold voltage
  • the impurity in the oxide semiconductor especially, hydrogen, water, or the like is removed as much as possible so that the properties of an interface with the gate insulating layer are favorable as described above. Accordingly, it is possible to obtain a thin film transistor which is stable with respect to the BT test.
  • a single layer or stacked layer can be formed using one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer (also referred to as SiO ⁇ N y , x > y > 0), a silicon nitride oxide layer (also referred to as Si jO y , x > y > 0), and an aluminum oxide layer.
  • the gate insulating layer 342 can have a structure in which a silicon oxide layer and a silicon nitride layer are stacked.
  • a silicon oxynitride layer with a thickness of 100 nm is formed by a high-density plasma CVD method with a pressure of 30 Pa and a microwave power of 6 kW.
  • the flow ratio of a monosilane gas (SiH 4 ) to nitrous oxide (N 2 0) which are introduced into the chamber is 1:10.
  • a conductive film is formed over the gate insulating layer 342.
  • a resist mask is formed over the conductive film through a second photolithography step, the conductive film is selectively etched to form a source electrode layer 355a and a drain electrode layer 355b, and then, the resist mask is removed (see FIG 22A).
  • an oxide semiconductor film 345 is formed (see FIG 22B).
  • the oxide semiconductor film 345 is formed by a sputtering method with the use of an In-Ga-Zn-O-based metal oxide target.
  • the oxide semiconductor film 345 is processed into an island-shaped oxide semiconductor layer through a third photolithography step.
  • the oxide semiconductor film 345 is preferably formed removing moisture remaining in the treatment chamber. This is for preventing hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor film 345.
  • an entrapment vacuum pump is preferably used.
  • a cryopump, an ion pump, or a titanium sublimation pump is preferably used.
  • an evacuation unit may be a turbo pump provided with a cold trap.
  • a hydrogen atom, a compound containing a hydrogen atom, such as water (H 2 0), and the like are removed, whereby the concentration of an impurity in the oxide semiconductor film 345 formed in the deposition chamber can be reduced.
  • a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed to a concentration of several ppm or a concentration of several ppb, as a sputtering gas when the oxide semiconductor film 345 is formed.
  • the temperature of first heat treatment for dehydration or dehydrogenation is greater than or equal to 400 °C and less than or equal to 750 °C, preferably greater than or equal to 400 °C and less than the strain point of the substrate.
  • the substrate is put in an electric furnace which is a kind of heat treatment apparatus and heat treatment is performed on the oxide semiconductor layer in a nitrogen atmosphere at 450 °C for one hour, and then water or hydrogen is prevented from entering the oxide semiconductor layer. In this manner, an oxide semiconductor layer 346 is obtained (see FIG 22C).
  • GRTA may be performed as follows.
  • the substrate is transferred and put in an inert gas which has been heated to a high temperature of 650 °C to 700 °C, heated for several minutes, and transferred and taken out of the inert gas which has been heated to a high temperature.
  • GRTA enables a high-temperature heat treatment for a short time.
  • an oxide insulating layer 356 serving as a protective insulating film is formed in contact with the oxide semiconductor layer 346.
  • the oxide insulating layer 356 has a thickness of at least 1 nm and can be formed by a method by which an impurity such as water or hydrogen does not enter the oxide insulating layer 356, such as a sputtering method, as appropriate.
  • an impurity such as water or hydrogen
  • a sputtering method such as a sputtering method, as appropriate.
  • entry of the hydrogen to the oxide semiconductor layer or extraction of oxygen in the oxide semiconductor layer by the hydrogen is caused, thereby making the resistance of the back channel of the oxide semiconductor layer low (n-type), so that a parasitic channel could be formed. Therefore, it is important that a formation method in which hydrogen is not used is employed such that the oxide insulating layer 356 contains hydrogen as little as possible.
  • a 200-nm-thick silicon oxide film is deposited as the oxide insulating layer 356 by a sputtering method.
  • the substrate temperature in film formation may be room temperature to 300 °C inclusive and is 100 °C in this embodiment.
  • the silicon oxide film can be formed by a sputtering method under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or an atmosphere containing a rare gas (typically argon) and oxygen.
  • a silicon oxide target or a silicon target can be used as a target.
  • the silicon oxide film can be formed by a sputtering method using a silicon target in an atmosphere containing oxygen and nitrogen.
  • the oxide insulating layer 356 which is formed in contact with the oxide semiconductor layer which is changed into an oxygen-deficient state and has lower resistance, that is, becomes an n-type oxide semiconductor layer is formed using an inorganic insulating film that does not contain an impurity such as moisture, a hydrogen ion, or OH ⁇ and blocks entry of such impurity from the outside, typically a silicon oxide film, a silicon oxynitride oxide film, an aluminum oxide film, or an aluminum oxynitride film.
  • the oxide insulating layer 356 is preferably formed removing moisture remaining in the treatment chamber. This is for preventing hydrogen, a hydroxyl group, or moisture from being contained in the oxide semiconductor layer 346 and the oxide insulating layer 356.
  • an entrapment vacuum pump is preferably used.
  • a cryopump, an ion pump, or a titanium sublimation pump is preferably used.
  • an evacuation unit may be a turbo pump provided with a cold trap.
  • a hydrogen atom, a compound containing a hydrogen atom, such as water (H 2 0), and the like are removed, whereby the concentration of an impurity in the oxide insulating layer 356 formed in the deposition chamber can be reduced.
  • a high-purity gas from which an impurity such as hydrogen, water, a hydroxyl group, or hydride is removed to a concentration of several ppm or a concentration of several ppb, as a sputtering gas when the oxide insulating layer 356 is formed.
  • second heat treatment (preferably at 200 °C to 400 °C inclusive, for example, 250 °C to 350 °C inclusive) is performed in an inert gas atmosphere or an oxygen gas atmosphere.
  • the second heat treatment is performed in a nitrogen atmosphere at 250 °C for one hour.

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