WO2000072372A1 - Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same - Google Patents

Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same Download PDF

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Publication number
WO2000072372A1
WO2000072372A1 PCT/US2000/014363 US0014363W WO0072372A1 WO 2000072372 A1 WO2000072372 A1 WO 2000072372A1 US 0014363 W US0014363 W US 0014363W WO 0072372 A1 WO0072372 A1 WO 0072372A1
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trench
layer
polysilicon
oxide layer
oxide
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WO2000072372A8 (en
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Richard K. Williams
Wayne B. Grabowski
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Priority to EP00932771A priority patent/EP1186019B1/en
Priority to DE60044396T priority patent/DE60044396D1/de
Priority to AU50446/00A priority patent/AU5044600A/en
Publication of WO2000072372A1 publication Critical patent/WO2000072372A1/en
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    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H10D30/635—Vertical IGFETs having no inversion channels, e.g. vertical accumulation channel FETs [ACCUFET] or normally-on vertical IGFETs
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/141—VDMOS having built-in components
    • H10D84/148—VDMOS having built-in components the built-in components being breakdown diodes, e.g. Zener diodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/83—FETs having PN junction gate electrodes
    • H10D30/831—Vertical FETs having PN junction gate electrodes
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts

Definitions

  • gate oxide layer 110 consists of a uniform thin layer of oxide along the three sides of the polysilicon gate 104. That is, the portions of gate oxide layer 110 on the sidewalls of the trench and also the curved and linear portions of the gate oxide layer 110 at the bottom of the trench (except for some stress-related and etch-related changes in the oxide thickness that occur at the trench bottom) are generally of a uniform thickness in the range of, for example, 150 A to 1,200 A. There are many variations of this general type of MOSFET. For example,
  • Fig. 4E shows that if one introduces a diode clamp including a deep P+ region, as shown on the right-hand side, the diode will break down at a lower voltage, and avalanche breakdown should not occur at the corner of the trench. If the resistance of the current path through the diode is low enough, then the diode will clamp the maximum voltage of the device. As a result, the voltage will never rise to the point that avalanche breakdown occurs near the corners of the trenches.
  • Figs. 5 A and 5B show the ionization contours in a device 170 having a sharp trench corner and a device 172 having a rounded trench corner.
  • Fig. 5B indicates that rounding the trench corners does reduce the magnitude of the ionization, but ultimately if one drives the device deeply enough into breakdown, the breakdown still occurs at the trench corner, and the device is at risk.
  • Figs. 6A-6C show the electric field strength contours, the equipotential lines and the electric field lines, respectively, in a MOSFET 180.
  • the gate of MOSFET 180 is tied to the source and body and is grounded, and the drain is biased at V D - From Fig. 6B it is evident that the drain voltage V D is divided and spaced out across the region.
  • the equipotential lines are squeezed closer together, and particularly around the trench corner they are squeezed even tighter. This produces electric field lines that are at right angles to the equipotential lines, as shown in Fig. 6C.
  • a high electric field occurs at the trench corner and why rounding the corner does not solve this problem. It is basically a volumetric problem in that there is an electric field that terminates on an electrode having a lower surface area, namely the gate, and so the electric field lines are crowded at the corner.
  • the immobile charge residing within the depletion region namely positive ions on the N-type side of the junction and negative ions on the P-type side of the junction, produces a "built-in" electric field across the junction.
  • the holes drifting across the N-type region add to the positive fixed charge and thereby increase the electric field, further enhancing the impact ionization process.
  • These excess holes make the epitaxial region, which in this example is N-type material, appear more heavily doped because of the increase in the "built-in” field.
  • the net effect is an increase in the electric field, which degrades the breakdown. This effect is shown in the current- voltage characteristics of Fig. 6F where the drain current I D increases dramatically at a certain drain voltage.
  • Fig. 7A is a schematic diagram of a MOSFET 190 having a gate driven by a current source 192 and having resistive load 194.
  • a voltage source 196 connected to the source and drain supplies a voltage V DD resulting in a drain voltage V D at the drain.
  • current source 192 begins to supply a constant current to the gate and the voltage on the gate relative to the source, labeled VQ in Fig. 7C, starts to rise.
  • the input capacitance actually has a number of components, including the gate-to-source capacitance C GS and the gate-to-body capacitance C GB , neither of which exhibits the amplification effect of the gate-to- drain capacitance C GD -
  • the gate-to-drain capacitance C GD is shown in Fig. 7G, around the bottom and side wall of the trench.
  • the equivalent schematic is shown in Fig. 7H. Even if C G D is the same order of magnitude as C GS and C GB , electrically it will look much larger (e.g., 5 to 10 times larger) because it is amplified during the switching process.
  • Figs. 8A-8C illustrate a process for forming a trench with rounded corners.
  • small reaction ions 202 etch the silicon through an opening in a mask 200 at the surface. Ions 200 are accelerated by an electric field in a downward direction such that they etch a trench having essentially a straight side wall. When the trench reaches a certain depth the electric field is relaxed, as shown in Fig. 8B. Alternatively, one could possibly change the chemistry.
  • the electric field is modified so that the etching ions are traveling in all different directions.
  • Figs. 9A-9D show a method that includes creating a mask 210 (Fig. 9A), etching the trench 212 (Fig. 9B), forming an oxide layer 214 on the walls of the trench (Fig. 9C), which may be removed and then re-grown to remove defects (this is called sacrificial oxidation), and then filling the trench with a polysilicon layer 216 (Fig. 9D).
  • Figs. 10A-10F illustrate a typical process of forming a trench MOSFET. The process starts with an N-epitaxial layer 220 grown on an N+ substrate 222
  • a polysilicon-filled trench 224 is formed in N-epi layer 220 (Fig. 10B).
  • the surface may or may not be planar depending on how the surface oxides are made in the process.
  • a P- body 226 is introduced, although the P-body 226 could be introduced prior to the formation of the trench 224 (Fig. 10C). Both process flows are manufacturable, but forming the trench first is preferable because the etching process can influence the doping concentrations in the P-body.
  • the surface is masked and an N+ source region 228 is implanted (Fig. 10D).
  • P+ region 230 is implanted to ohmic contact between the P-body and a metal layer to be deposited later.
  • P+ region 230 can be implanted through an opening in an oxide layer 232 that is deposited across the region and then etched to form a contact mask (Fig. 10E).
  • the contact mask may or may not be used to define the P+ region 232.
  • a metal layer 234 is deposited on the surface to contact the N+ source region 228 and P+ region 230 (Fig. 10F).
  • One process includes the following steps.
  • a trench is etched in the semiconductor material.
  • a directional deposition of a dielectric material is then performed such that the dielectric material is deposited preferentially on horizontal surfaces such as the bottom of the trench. This is done by creating an electric field in the deposition chamber (e.g., a chemical vapor deposition or sputtering chamber) so as to accelerate the charged ions of the dielectric towards the semiconductor material.
  • the trench is filled with a conductive material that will form the gate electrode.
  • Processes in accordance with this invention may include a process for self aligning the trench with a contact to the top surface of the "mesa" between the trenches.
  • a "hard" layer of a material such as silicon nitride is used as a trench mask.
  • the hard mask remains in place until a dielectric layer has been formed over the gate electrode, preferably by oxidizing polysilicon gate.
  • the hard mask is then removed, exposing the entire top surface of the mesa and allowing a contact to be made thereto with a metal layer.
  • the dielectric sidewall spacers provide additional insulation between the later formed gate electrode and the semiconductor material in the mesa.
  • Another group of processes provide a "keyhole" shaped trench, wherein a thick dielectric layer extends some distance upward on the sidewalls of the trench. After the trench has been etched, a relatively thick oxide lining is grown or deposited on the bottom and sidewalls of the trench. The trench is filled with polysilicon, and the polysilicon is then etched back such that only a portion remains at the bottom of the trench, overlying the oxide lining. The exposed oxide lining is removed from the sidewalls of the trench.
  • a masking material such as photoresist is deposited over the oxide lining at the bottom of the trench.
  • An oxide etch is then performed to removed the oxide lining from the sidewalls of the trench, and the masking material is removed from the bottom of the trench.
  • a relatively thin gate oxide layer is grown on the sidewalls of the trench, and the trench is filled with a conductive material such as polysilicon which forms the gate electrode.
  • Fig. 4B is a cross-sectional view showing the electric field contours in a MOSFET having a thin gate oxide layer.
  • Fig. 4F is a graph showing the breakdown voltage as a function of gate oxide thickness in MOSFETs fabricated in epitaxial layers having different doping concentrations.
  • Fig. 5B is a cross-sectional view showing ionization contours in a trench power MOSFET having a rounded trench corner.
  • Fig. 6A is a cross-sectional view showing the electric field contours in a trench power MOSFET having a flat body-drain junction.
  • Fig. 7D is a graph showing how the drain current varies under the conditions of Fig. 7B.
  • Fig. 7G is a cross-sectional view showing the components of the gate capacitance in a trench power MOSFET.
  • Fig. 7H is an equivalent circuit diagram of a trench MOSFET showing the inter-electrode capacitance.
  • Fig. 11 A is a cross-sectional view of a trench power MOSFET having a thick oxide layer at the bottom of the trench.
  • Fig. 1 IB is a cross-sectional view showing the MOSFET of Fig. 11 A having a thick oxide layer patterned on the top surface of the semiconductor.
  • Fig. 12 is a schematic flow diagram showing a number of process sequences in accordance with this invention.
  • Figs. 16A-16E illustrate an alternative process in which a small amount of photoresist is used to mask the thick oxide at the bottom of the trench.
  • Figs. 17A-17F illustrate a process in which the polysilicon is etched to a level near the bottom of the trench and then oxidized.
  • Figs. 18A-18F illustrate an alternative process in which the polysilicon is oxidized.
  • Figs. 21 A-21E illustrate a problem that can occur from undercutting the thin oxide layer below the nitride.
  • Figs. 23A-23G illustrate other problems that can arise in the fabrication of power MOSFETs in accordance with this invention.
  • Figs. 24A-24F illustrate problems that can occur from undercutting a hard mask during the removal of the top oxide in a self-aligned device.
  • Figs. 26A and 26B illustrate a problem that can occur during the formation of the gate oxide layer in a thick bottom oxide device.
  • Figs. 27A-27D illustrate a method of avoiding the problem illustrated in
  • Figs. 35A-35L illustrate cross-sectional views showing the process of Fig. 34.
  • Figs. 36-39 are cross-sectional views showing trench power MOSFETs having "keyhole” shaped gate electrodes.
  • Figs. 40A-40L illustrate a process sequence for fabricating a MOSFET having a keyhole-shaped gate electrode.
  • Figs. 42A-42C illustrate the strength of the electric field in a conventional power MOSFET, a power MOSFET having a thick bottom gate oxide, and a power MOSFET having a keyhole-shaped gate electrode, respectively.
  • Fig. 11 A shows an epitaxial (“epi") layer 242 grown on a substrate 240.
  • a trench 250 is formed in epi layer 242.
  • a gate oxide layer 244 lines the walls of trench 250, and a thick portion 246 of gate oxide layer 244 is located at the bottom of trench 250.
  • Trench 250 is filled with polysilicon 248. Note that there is no oxide layer on top of polysilicon 248.
  • the arrangement of Fig. 11 A could be an intermediate structure; an oxide layer could be formed on top of polysilicon 248 at a later stage of the process.
  • Polysilicon 248 is typically doped to a heavy doping concentration. It maybe formed with a top surface substantially planar, i.e., flat, with the silicon epi surface by a number of means.
  • One method to make the surface flat is to deposit the polysilicon layer to a greater thickness and then etch it back.
  • Another means to produce a flat surface is to deposit the polysilicon to a thickness greater than the amount needed to fill the trench and then chemical mechanically polish the surface flat.
  • a flat surface is desirable to reduce the height of steps which may form later in the fabrication process.
  • Fig. 1 IB shows a structure with an oxide layer 252 on top of polysilicon layer 248. Since the lateral edges of oxide layer 252 do not correspond to the walls of trench 250, oxide layer 252 is most likely formed with a mask and etching step. Oxide layer 252 could be either deposited (e.g., by chemical vapor deposition) or it could be thermally grown or some combination of these steps.
  • Fig. 1 IC shows a top oxide layer 254 that is grown in accordance with the teachings of Application No. 09/296,959, which is incorporated herein by reference in its entirety. The sides of oxide layer 254 are generally aligned with the walls of trench 250 and oxide layer 254 extends down into trench 250. Polysilicon layer 248 is thus embedded in trench 250.
  • Figs. 1 IB and 1 IC both have a thick gate oxide region 246 at the bottom of the trench.
  • Fig. 12 is a schematic diagram of several process flows that can be used to fabricate gate trenches in accordance with this invention. The details of these process flows are shown in Figs. 13-20.
  • Fig. 12 illustrates in block diagram form that the trench may be formed using a photoresist mask or a hard mask sequence, followed by a directed oxide deposition planarized by either a selective etch, a dipback, or a selective oxidization. A selective oxidization can be used without a directed deposition.
  • the trench is filled with polysilicon using a one-step or two-step process.
  • the trench is formed using a mask that is later removed, so that the mask is not available as a reference for other processing steps.
  • the other option is to use a "hard" mask to form the trench, as described in the above-referenced Application No. 09/296,959, which is then employed as a reference later in the process.
  • This option is generally described in Figs. 19 and 20.
  • a sacrificial oxide layer is grown on the walls of the trench and then removed.
  • An oxide lining may then be formed on the walls of the trench. This stage yields a trench having a uniform oxide layer on its walls, with or without a hard mask on the top surface of the silicon.
  • Depositing the polysilicon in a two-stage process may be beneficial to the introduction of dopants into the "mesa" between the trenches, and to make a more lightly doped polysilicon layer available on the surface of the wafer to produce diodes, resistors, and other polysilicon devices.
  • a sacrificial oxide layer 270 has been formed on the surface of the trench. Sacrificial oxide layer 270 is then removed, as shown in Fig. 13C.
  • Sacrificial oxide layer 270 could be from 100 A to 1000 A thick; typically, it would be in the range of 300 A thick. It can be formed by heating the structure at 800° C to 1100° C for 10 minutes to five hours in an oxidizing ambient.
  • the ambient could be either oxygen or it could be oxygen and hydrogen. If the ambient is a combination of oxygen and hydrogen, it is considered a "wet" oxidation because the reaction would produce water vapor and this would affect the consistency and growth rate of the oxide.
  • polysilicon layer 278 is then etched back until it is roughly coplanar with the top surface of epi layer 262.
  • the portions of oxide layer 270 on the surface of epi layer 262 are removed, taking care not to etch too much of the oxide layer 276 on the sidewalls of the trench.
  • the result of this step is shown in Fig. 13K. Avoiding the removal of oxide layer 276 is best performed by having polysilicon layer 278 protrude slightly above the oxide layer 276.
  • the entire top surface of the structure, including the top surface of polysilicon layer 278, has been oxidized to form an oxide layer 280. As shown in Fig.
  • a glass layer 282 is laid down over the surface of oxide layer 280, and glass layer 282 and oxide layer 280 are then patterned and etched to form contact openings to the epi layer 262, yielding the structure shown in Fig. 13N.
  • Figs. 14A-14F show an alternate process flow beginning with the structure shown in Fig. 131.
  • Fig. 14A corresponds to Fig. 141.
  • Polysilicon layer 278 is etched back, as shown in Fig. 14B, and then the top surface of the remaining portion of polysilicon layer 278 is oxidized to form an oxide layer 290, as shown in Fig. 14C.
  • a glass layer 292 is then deposited over the entire surface of the structure, as shown in Fig. 14D.
  • a mask layer 294 is formed on the top surface of glass layer 292, and layers 270 and 292 are etched to form contact openings, as shown in Fig. 14F.
  • Mask layer 294 is then removed.
  • Figs. 15A-15F illustrate yet another alternative process, beginning again with the structure shown in Fig. 131.
  • Fig. 15A corresponds to Fig. 131.
  • Polysilicon layer 278 is etched back to a level inside the trench, as shown in Fig. 15B.
  • a second polysilicon layer 300 is deposited over the entire structure, as shown in Fig. 15C.
  • Polysilicon layer 300 is then etched back, but care is exercised to ensure that the portion of oxide layer 276 at the upper corner of the trench is not exposed.
  • the resulting structure is shown in Fig. 15D.
  • oxide layer 270 is removed, as shown in Fig. 15E, and an oxide layer 302 is formed over the entire surface of the structure.
  • a glass layer 304 is then deposited over oxide layer 302, yielding the structure illustrated in Fig. 15F.
  • Figs. 17A-17F show yet another alternative process sequence, beginning with the structure shown in Fig. 13F.
  • Fig. 17A corresponds to Fig. 13F.
  • a sacrificial polysilicon layer 320 is deposited.
  • Polysilicon layer 320 is etched back until only a small portion 322 remains at the bottom of trench 268.
  • the portion 322 of polysilicon layer 320 is then oxidized.
  • a low temperature oxidation process is used (e.g., 700 to 950 °C), since at a low temperature polysilicon oxidizes more rapidly than single crystal silicon.
  • oxide forms in portion 322 at a faster rate than on the sidewalls of trench 268.
  • the resulting structure is shown in Fig.
  • oxide layer 324 is formed on the sidewalls of trench 268, as shown in Fig. 17F.
  • Figs. 18A-18F show yet another alternative process sequence, beginning with the structure shown in Fig. 13B.
  • Fig. 18A corresponds to Fig. 13D, where oxide lining 272 has just been formed.
  • a sacrificial polysilicon layer 330 is deposited, as shown in Fig. 18B.
  • Polysilicon layer 330 is etched back until only a small portion 332 remains at the bottom of trench 268, as shown in Fig. 18C.
  • the structure is then subjected to a low-temperature oxidation, as described above, converting polysilicon portion 332 into an oxide layer 334, as shown in Fig. 18D.
  • Figs. 19A-19I illustrate a process which contains elements of the super self- aligned process described in the above-referenced Application No. 09/296,959.
  • the structure is formed in an epi layer 342 which is grown on a substrate 340.
  • a thin oxide layer 346 is formed on the surface of epi layer 342, and this is covered by a layer 344 of a hard masking material such as silicon nitride.
  • An opening is etched in nitride layer 344 and oxide layer 346, as shown in Fig. 19 A.
  • a trench 348 is etched in epi layer 342 using a conventional process.
  • a sacrificial oxide layer is (not shown) formed on the walls of trench 348 and then removed.
  • polysilicon layer 358 is then etched back to a level above the surface of the thin oxide layer 346.
  • the thick oxide layer 352 has been removed from above the nitride layer 344, with the polysilicon layer 358 protecting the thin oxide layer 356 at the edges of trench 348.
  • the structure is then annealed such that a portion of polysilicon layer 358 is oxidized to form a thick oxide layer 360 in the upper region of the trench, as shown in Fig. 19K.
  • nitride layer 344 is removed.
  • Figs. 20A-20F show a two-stage polysilicon process with two trenches, one of which is in the active array and the other of which is part of a gate bus.
  • the process starts at the point illustrated in Fig. 19H, with a polysilicon layer 388 filling trenches 374A and 374B.
  • a thick oxide layer 384 has been formed at the bottom of trenches 374A and 374B.
  • a silicon nitride layer 374 overlies the surface of epi layer 372.
  • Nitride layer 374 is covered by an oxide layer 382.
  • Polysilicon layer 388 is etched back as shown in Fig. 20B, and oxide layer 382 is removed.
  • a second polysilicon layer 390 is deposited over polysilicon layer 388, and a "hard" layer 392, formed of nitride or polyimide, for example, is deposited on top of the second polysilicon layer 390.
  • the resulting structure is illustrated in Fig. 20C.
  • polysilicon layer 390 and the hard layer 392 are etched from the region of the active array (trench 374 A), leaving these layers in the region of the gate bus (trench 374B).
  • the structure is then heated to oxidize polysilicon layer 388 in trench 374A producing a thick oxide layer 394 in the upper region of that trench.
  • an oxide layer 396 forms on the exposed edge of second polysilicon layer 390.
  • This structure is shown in Fig. 20E.
  • the exposed portions of the hard layers 374 and 392 are removed, yielding the arrangement shown in Fig. 20F.
  • Figs. 21A-21E and 22A-22C illustrate two problems that need to be avoided.
  • Fig. 21 A shows a sacrificial oxide layer 400 along the walls of the trench and a thin oxide layer 404 and a nitride layer 402 on the top surface of the epi layer.
  • Fig. 21B in the process of removing the sacrificial oxide layer 400, a portion of the thin oxide layer 404 has been removed underneath nitride layer 402.
  • the solution to this problem is to minimize the oxide overetch time or to use an oxide layer 404 that is as thin as possible, even as thin as 15 to 90 A.
  • Figs. 22A-22C illustrate another potential problem area.
  • Fig. 22A shows a device at the same stage that is illustrated in Fig. 19D, with thick oxide layer 352 having been directionally deposited, forming a thick portion 354 at the bottom of the trench.
  • a portion of the thin oxide layer 346 is removed from underneath nitride layer 344.
  • the gate oxide layer 356 is grown, the portion of the oxide layer at the upper corner of the trench is unduly thin, and this can lead to defects in the oxide and shorting between the gate and the epi layer.
  • This problem is illustrated in Fig. 22C.
  • the solution is to minimize any oxide overetch or alternatively to use a plasma etch whose chemistry etches isotropically.
  • Fig. 23 A shows a problem that can result when the polysilicon fills a cavity that is formed under the nitride layer, as shown in Fig. 2 IE.
  • a portion 420A of polysilicon layer 420 extends outside the trench and will form a short to a metal layer deposited later to contact the epi layer. During oxidation, the oxide 422 does not consume the silicon filling under the nitride overhang. Removal of the nitride exposes the gate to a source metal short.
  • Fig. 23B shows a variation in which the portion 420B is separated by oxide from the main polysilicon layer 420.
  • 23C illustrates a case in which polysilicon layer 420 has formed upward projecting spikes 420C, creating the likelihood of a short between the gate polysilicon layer 420 and a later deposited metal layer. Again, the polysilicon filling under the nitride remains after oxidation leaving a possible gate-to-source short.
  • Fig. 23D shows the gate I-V characteristic of a shorted device.
  • the low resistance is referred to as a "hard" short.
  • Fig. 23E shows the characteristics of a
  • the diode-like short can occur within a gate bus region as shown in Fig. 23F.
  • an N+ region or plume is doped into the P body wherever the polysilicon touches the silicon mesa, producing a parasitic diode and MOSFET shown schematically in Fig. 23G.
  • Figs. 24A-24F illustrate the processing mechanism that causes the diode short as an overetch first polysilicon layer or a misshapen, distorted trench.
  • the active cell and gate bus region are filled with a first layer of N+ doped polysilicon and are then etched back to produce the structure shown in Fig. 24B. If the etchback of the polysilicon is nonuniform, one side of the trench oxide may be exposed, as shown in fig. 24C, which then is attacked and etched during dip which removes the top oxide.
  • the second polysilicon layer is deposited and patterned by a mask, leaving the active cell on the left and the gate bus on the right. After top oxidization, shown in Fig.
  • the active cell on the left oxidizes and heals itself, but in the gate bus region the polysilicon touching the silicon dopes an N+ plume leading to the diode-like gate short of Fig. 24F.
  • Uniform etchback of the polysilicon and uniformly shaped trenches avoid this problem.
  • nitride layer 510 is then deposited over the top of the structure, yielding the arrangement shown in Fig. 25C.
  • Nitride layer 510 is etched anisotropically. Since the vertical thickness of nitride layer 510 is much greater near the edges of the ONO sandwich, the anisotropic etch leaves sidewall spacers 512 at the exposed edge of oxide layer 504 and nitride layer 506. This structure, following the removal of oxide layer 508 is shown in Fig. 25D.
  • a trench 514 is then etched, and the typical sacrificial gate oxide layer (not shown) is formed and removed.
  • Fig. 25F shows the structure after the directional deposition of an oxide layer 516, which leaves a thick oxide portion 518 at the bottom of the trench 514. This is done after the formation of a gate oxide layer 520.
  • the trench is then filled with a polysilicon layer 522, which is etched back, taking care not to attack the underlying oxide layer 520.
  • the top region shere the polysilicon and silicon nearly touch will be oxidized further later in the process. Also, some oxide will grow under the nitride sidewall cap, like a "bird's beak".
  • Oxide layer 516 is then removed, producing the embodiment shown in Fig. 25H.
  • Figs. 26A and 26B growing the gate oxide on the sidewalls of the trench can lead to a "kink" in the sidewall of the trench, shown as kink 530 in Fig. 26B.
  • the problem is that, as shown in Fig. 26 A, the oxide grows uniformly on the exposed sidewall 532 of the trench. However, where the thick oxide 534 begins at the bottom of the trench, owing to the geometry of the structure, the oxidation does not proceed in a linear fashion. This creates a reduced thickness of the oxide layer at kink 530.
  • a solution to this problem is illustrated in Figs. 27A-27D. Fig.
  • Figs. 28-33 illustrate various devices that can be fabricated using the principles of this invention.
  • Fig. 28 shows a power MOSFET having a flat-bottomed P-body region and an N buried layer at the interface between the epi layer and substrate.
  • Fig. 28 illustrates a device combining the thick trench bottom oxide with a contact that extends entirely across the mesa between trenches although a contact mask and nonplanar top oxide layer could be utilized.
  • Fig. 29 shows a MOSFET that is similar to the one shown in Fig. 28 except that each MOSFET cell contains a deep P+ region, in accordance with the teachings of U.S. Patent No. 5,072,266 to Bulucea et al. The embodiment of Fig.
  • the trenches extend into the N-buried layer so that only the thick oxide region overlaps the heavily doped buried layer.
  • Fig. 33 is an accumulation mode MOSFET (ACCUFET), such as the one taught in U.S. Patent No. 5,856,692 to Williams et al., which is incorporated herein by reference.
  • ACCUFET accumulation mode MOSFET
  • Fig. 34 is a conceptual drawing showing a process flow for a trench MOSFET using a conventional contact mask and incorporating a thick trench bottom oxide.
  • the steps of the process generally include the formation of the drain and body regions, the etching of the trench and formation of the gate, the implantation of the body and source regions, and the opening of contacts and deposition of a metal layer.
  • the boxes with the corners clipped represent optional steps.
  • the introduction of a deeper body region by implant or by implant and diffusion is consistent with this process This process is illustrated in Figs. 35A-35L.
  • a trench 552 is formed in an
  • N epi layer 550 using an oxide layer 554 as a mask.
  • An oxide lining 556 is formed on the walls of the trench 552 (Fig. 35B), and a directional oxide deposition is carried out as described above, forming an oxide layer 558 having a thick portion 560 at the bottom of the trench (Fig. 35C).
  • the sidewalls of trench 552 are then etched (Fig. 35D), and a gate oxide layer is thermally grown on the walls of trench 552 (Fig. 35E).
  • a polysilicon layer 564 is then deposited to fill the trench 552 (Fig. 35F). Polysilicon layer 564 is etched back into the trench (Fig. 35G). An oxide layer 566 is deposited over the top surface of the structure and extends down into the trench to the top surface of polysilicon layer 564 (Fig. 35H). Oxide layer 566 is then etched back (Fig. 351), and a P-type dopant such as boron is implanted to form P body region 568. The top surface is then masked (not shown), and an N-type dopant such as arsenic or phosphorus is implanted to form N+ source regions 570. Another oxide layer 572 is deposited on the top surface and patterned, yielding the structure shown in Fig. 35L. The contact can then be filled by the top metal or alternatively filled with a planarizing metal such as tungsten first, or with a barrier metal such as Ti/TiN.
  • a planarizing metal such as tungsten first, or with
  • Figs. 36-39 illustrate several embodiments in which the polysilicon gate is "keyhole" shaped in cross-section.
  • the thicker gate oxide extends not only along the bottom of the trench but also along the sidewalls of the trench towards the junction between the P body region and the N epi layer.
  • the thickened gate oxide along the sidewalls of the trench helps to soften the electric field at that junction.
  • Fig. 36 shows a MOSFET having flat-bottomed P body regions and a diode cell incorporated at periodic intervals among the MOSFET cells.
  • a keyhole-shaped gate is employed.
  • Fig. 37 shows an embodiment where the P body does not extend to the surface but instead is contacted in the third dimension.
  • a shallow P+ region is shown within the mesa at a depth greater than the N+ source regions.
  • Fig. 38 shows an embodiment wherein the trenches extend into an N buried layer formed at the interface between the epi layer and the substrate.
  • Fig. 39 shows an embodiment where the P body is contacted in the third dimension, and the trenches extend into an N buried layer.
  • FIGs. 40A-40L A process sequence for forming a device having a keyhole shaped trench is illustrated in Figs. 40A-40L.
  • the process starts with an epi layer 602 grown on a substrate 600.
  • An oxide layer 604 is formed at the top surface of epi layer 602, as shown in Fig. 40A.
  • Oxide layer 604 is patterned and a trench 606 is etched, as shown in Fig. 40B.
  • a sacrificial oxide layer (not shown) is formed on the walls of the trench and removed.
  • An oxide lining 608 is then grown on the walls of trench 606 (as shown in Fig. 40C). As shown in Figs.
  • a polysilicon layer 610 is deposited to fill the trench 606 and then etched back such that a portion 612 remains at the bottom of the trench.
  • the oxide lining 608 is then etched from the walls of the trench 606, as shown in Fig. 40F.
  • An anisotropic silicon etch is then performed to depress the top surface of polysilicon portion 612 below the top surface of oxide lining 608, as shown in Fig. 40G.
  • a thermal oxidation process is then applied, forming an oxide layer 616 on the walls of the trench 606 and an oxide layer 618 at the top surface of polysilicon portion 612. The result is shown in Fig. 40H.
  • FIGs. 41 A-41F A variation of this process is illustrated in Figs. 41 A-41F.
  • a photoresist layer is applied, developed, and washed away, leaving only a portion 630 at the bottom of the trench 606. This is shown in Fig. 41 A.
  • Oxide lining 608 is then etched from the walls of the trench 606, as shown in Fig. 41B and the portion 630 of the photoresist layer is removed from the bottom of the trench. This yields the structure shown in Fig. 41 C.
  • a gate oxide layer 632 is thermally grown on the walls of trench 606, and trench 606 is filled with a polysilicon layer 634, as shown in Figs.
  • Fig. 41D and 41E Polysilicon layer 634 is etched back to the level of the top surface of the epi layer 602. Polysilicon layer 634 is then oxidized thermally to produce the device shown in Fig. 41F.
  • Figs. 42A-42C show a comparison of the strength of the electric field along the sidewall of the trench in a prior art trench device with the strength of the electric field in embodiments of this invention.
  • Fig. 41 A shows that in the prior art device the electric field has two sharp peaks which occur, respectively, at the body- drain junction and the bottom of the gate electrode.
  • Fig. 42B shows a device having a thick oxide layer on the bottom of the trench.
  • Fig. 42C shows a device having a keyhole shaped gate electrode. In this case, the electric field still reaches a peak at the body-drain junction, but the sharp peak at the bottom of the gate electrode is eliminated.

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  • Electrodes Of Semiconductors (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Drying Of Semiconductors (AREA)
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US20050215012A1 (en) 2005-09-29
EP2020681B1 (en) 2011-09-14
WO2000072372A8 (en) 2002-09-26
JP2003509836A (ja) 2003-03-11
AU5044600A (en) 2000-12-12
EP1186019B1 (en) 2010-05-12
CN1205658C (zh) 2005-06-08
US20050215027A1 (en) 2005-09-29
US7238568B2 (en) 2007-07-03
DE60044396D1 (de) 2010-06-24
US6291298B1 (en) 2001-09-18
US20010026961A1 (en) 2001-10-04
EP2020681A3 (en) 2009-06-10
US7276411B2 (en) 2007-10-02
KR100700322B1 (ko) 2007-03-29
JP4834228B2 (ja) 2011-12-14
EP1186019A4 (en) 2004-05-26
EP2020681A2 (en) 2009-02-04
EP1186019A1 (en) 2002-03-13
US20040203200A1 (en) 2004-10-14
US6900100B2 (en) 2005-05-31
CN1360735A (zh) 2002-07-24
US20050215013A1 (en) 2005-09-29
US7282412B2 (en) 2007-10-16
KR20020037726A (ko) 2002-05-22

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