WO2000014778A1 - Diffusion barrier layers and methods of forming same - Google Patents

Diffusion barrier layers and methods of forming same Download PDF

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Publication number
WO2000014778A1
WO2000014778A1 PCT/US1999/020053 US9920053W WO0014778A1 WO 2000014778 A1 WO2000014778 A1 WO 2000014778A1 US 9920053 W US9920053 W US 9920053W WO 0014778 A1 WO0014778 A1 WO 0014778A1
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platinum
electrode
ruthenium
alloy
layer
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English (en)
French (fr)
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Eugene P. Marsh
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Micron Technology Inc
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Micron Technology Inc
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Priority to AU57996/99A priority Critical patent/AU5799699A/en
Priority to JP2000569428A priority patent/JP5328065B2/ja
Publication of WO2000014778A1 publication Critical patent/WO2000014778A1/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising transition metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto

Definitions

  • the present invention relates to semiconductor devices and the fabrication thereof. More particularly, the present invention pertains to diffusion barrier layers.
  • conductive layers are used.
  • DRAMs dynamic random access memories
  • SRAMs static random access memories
  • FE ferroelectric memories
  • conductive materials are used in the formation of storage cell capacitors and also may be used in interconnection structures, e.g., conductive layers in contact holes, vias, etc. In many applications, it is preferable that the material used provide effective diffusion barrier characteristics.
  • conductive materials used in the formation of storage cell capacitors of memory devices e.g., DRAMs.
  • memory devices As memory devices become more dense, it is necessary to decrease the size of circuit components forming such devices.
  • One way to retain storage capacity of storage cell capacitors of the memory devices and at the same time decrease the memory device size is to increase the dielectric constant of the dielectric layer of the storage cell capacitor. Therefore, high dielectric constant materials are used in such applications interposed between two electrodes.
  • One or more layers of various conductive materials may be used as the electrode material. However, generally, one or more of the layers of the conductive materials used for the electrodes (particularly the lower electrode of a cell capacitor) must have certain barrier properties and oxidation resistance properties.
  • Such properties are particularly required when high dielectric constant materials are used for the dielectric layer of the storage cell capacitor because of the processes used for forming such high dielectric materials, e.g., deposition of high dielectric materials usually occurs at high temperatures (generally greater than about 500° C) in an oxygen-containing atmosphere.
  • the electrode barrier structure includes layers of platinum :rhodium alloy, in addition to platinum :rhodium oxide layers, to form electrodes with diffusion barrier properties.
  • Such alloy layers are formed using physical vapor deposition (PVD) processing, e.g., reactive RF sputtering processes.
  • the storage cell capacitors are formed using high aspect ratio openings.
  • the storage cell capacitors include a lower electrode that is formed by deposition of a conductive material within a small high aspect ratio opening.
  • sputtering does not provide a sufficiently conformal layer adequate for formation of an electrode within such a small high aspect ratio opening.
  • barrier layers for use in other applications, e.g., interconnec! application:-., is also desirable.
  • diffusion barriers are commonly used to prevent undesirable reactions in contact openings.
  • a method for use in the fabrication of integrated circuits according to the present invention includes providing a substrate assembly having a surface and forming a barrier layer over at least a portion of the surface.
  • the barrier layer is formed of a platinum(x):ruthenium(l-x) alloy, where x is in the range of about 0.60 to about 0.995.
  • x is in the range of about 0.90 to about 0.98, and more preferably, x is about 0.95.
  • the barrier layer is formed by chemical vapor deposition.
  • the portion of the surface upon which the barrier layer is formed is a silicon containing surface.
  • Another method for use in the formation of a capacitor according to the present invention includes forming a first electrode on a portion of a substrate assembly.
  • a high dielectric material is formed over at least a portion of the first electrode and a second electrode is formed over the high dielectric material.
  • At least one of the first and second electrodes comprises a layer of a platinum rruthenium alloy.
  • at least one of the first electrode and second electrode includes the layer of platinum(x):ruthenium(l-x) alloy and one or more additional conductive layers.
  • the method includes providing a substrate assembly including at least one active device and forming a capacitor relative to the at least one active device.
  • the capacitor comprises at least one electrode including a barrier layer of platinum(x):ruthenium(l-x) alloy.
  • a semiconductor device structure according to the present invention includes a substrate assembly including a surface and a barrier layer over at least a portion of the surface.
  • the barrier layer is formed of a platinum(x):ruthenium(l-x) alloy, wherein x is in the range of about 0.60 to about 0.995.
  • a capacitor structure according to the present invention includes a first electrode, a dielectric material on at least a portion of the first electrode, and a second electrode on the dielectric material. At least one of the first and second electrodes comprises a barrier layer of platinum(x):ruthenium(l-x) alloy.
  • a memory cell structure includes a substrate assembly including at least one active device and a capacitor formed relative to the at least one active device.
  • the capacitor comprises at least one electrode including a barrier layer formed of platinum(x):ruthenium(l-x) alloy.
  • Another integrated circuit structure includes a substrate assembly including at least one active device and an interconnect formed relative to the at least one active device.
  • the interconnect including a barrier layer formed of platinum(x):ruthenium(l-x) alloy.
  • Figure 1 shows a device structure including a platinum:ruthenium alloy layer according to the present invention.
  • Figure 2 shows a structure including a platinum :ruthenium alloy layer according to the present invention as part of a multiple conductive layer stack.
  • Figure 3 is a structure including a high dielectric capacitor including an electrode having a platinum:ruthenium alloy layer according to the present invention.
  • Figure 4 illustrates the use of a platinum:ruthenium alloy layer in a storage cell capacitor application.
  • Figure 5 illustrates the use of a platinum :ruthenium alloy layer in an interconnect application.
  • Figures 6A-6C show the results of an example wherein a layer of platinum :ruthenium alloy material is deposited.
  • Figure 6A shows a depth profile of the deposited platinum :ruthenium alloy layer before an oxygen anneal
  • Figure 6B shows a depth profile of the deposited platinum :ruthenium alloy layer after an oxygen anneal
  • Figure 6C shows an XPS montage display showing the Si signal during profile through the platinum :ruthenium layer after annealing in oxygen.
  • Figure 1 illustrates a structure 10 including a substrate assembly 12 and a platinum:ruthenium alloy layer 14 according to the present invention formed on a surface 13 of the substrate assembly 12, e.g., a silicon containing surface.
  • the structure 10 is illustrative of the use of a platinum :ruthenium alloy layer for any application requiring an effective barrier layer.
  • the platinum:ruthenium alloy layer 14 may be used in the fabrication of semiconductor devices wherever it is necessar' ⁇ prevent the diffusion of one material to an adjacent material.
  • the substrate assembly 12 may be representative of a contact structure having an opening extending to a silicon containing surface.
  • the platinum:ruthenium alloy barrier layer 14 may be used in the formation of storage cell capacitors for use in semiconductor devices, e.g., memory devices. As further described herein, the platinum :ruthenium alloy barrier layer 14 may be used alone as an electrode in such storage cell capacitors or within a stack of layers forming an electrode of a capacitor.
  • substrate assembly refers to either a semiconductor substrate such as the base semiconductor layer, e.g., the lowest layer of a silicon material in a wafer, or a silicon layer deposited on another material, such as silicon on sapphire, or a semiconductor substrate having one or more layers or structures formed thereon or regions formed therein.
  • various process steps may have been previously used to form or define regions, junctions, various structures or features, and openings such as vias, contact openings, high aspect ratio openings, etc.
  • the platinum:ruthenium alloy layer 14 includes an atomic composition of platinum(x):ruthenium(l-x), where preferably, x is in the range of about 0.60 to about 0.995. In other words, the amount of ruthenium necessary in the platinum layer to accomplish barrier characteristics for semiconductor devices is minimal, i.e., in the range of about 40% to about .5%. More preferably, x is in the range of about 0.90 to about 0.98; and, yet more preferably, x is about 0.95, i.e., about 5% ruthenium in the layer is suitable to provide barrier characteristics. In other words, preferably, the atomic composition of the platinumrruthenium alloy layer 14 is about 95% platinum and 5% ruthenium.
  • the thickness of the platinum:ruthenium alloy layer 14 is dependent upon the application for which it is used. Preferably, the thickness is in the range of about 10 A to about 10,000 A. More preferably, the thickness of the platinum :ruthenium alloy layer 14 is in the range of about 100 A to about 500 A. For example, this preferred thickness range of about 100 A to about 500 A is applicable to a single platinum:ruthenium alloy layer forming an electrode of a capacitor.
  • the platinum:ruthenium alloy layer 14 formed on the surface 13 of substrate assembly 12 may be formed by one or more various processes.
  • the formation of the platinum:ruthenium alloy layer 14 may be accomplished by the simultaneous evaporation of the metals from respective sources, i.e., co-evaporation; may be sputter deposited from a single deposition target of platinum:ruthenium alloy; may be deposited by the simultaneous co- sputtering from two targets (i.e., one target including platinum and the other target including ruthenium); or may be deposited by chemical vapor deposition (CVD), for example, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or any other chemical vapor deposition technique.
  • CVD chemical vapor deposition
  • the formation of the platinum:ruthenium alloy layer 14 is attained by CVD.
  • the process may be carried out in a chemical vapor deposition reactor, such as a reaction chamber available under the trade designation of 7000 from Genus, Inc., (Sunnyvale, CA), or available under the trade designation of 5000 from Applied Materials, Inc., (Santa Clara, CA), or available under the trade designation of Prism from Novelus, Inc., (San Jose, CA).
  • a chemical vapor deposition reactor such as a reaction chamber available under the trade designation of 7000 from Genus, Inc., (Sunnyvale, CA), or available under the trade designation of 5000 from Applied Materials, Inc., (Santa Clara, CA), or available under the trade designation of Prism from Novelus, Inc., (San Jose, CA).
  • any reaction chamber suitable for performing CVD may be used.
  • Chemical vapor deposition is defined as the formation of a nonvolatile solid film on a substrate by the reaction of vapor phase reactants, i.e., reactant gases, that contain desired components.
  • the reactant gases are introduced into the reaction chamber.
  • the gases decompose and react at a heated wafer surface to form the desired layer.
  • Chemical vapor deposition is just one process of providing thin layers on semiconductor wafers, such as films of elemental metals or compounds, e.g., platir ⁇ um:rutheniu ⁇ n alloy layers. Chemical vapor deposition processes are favored in many respects because of the process capability to provide highly conformal layers even within deep contacts and other openings.
  • CVD processing is preferably used to provide highly conformal layers within deep contacts and other openings such as for lower electrodes of storage cell capacitors. It will be readily apparent to one skilled in the art that although CVD is the preferred process, that the CVD process may be enhanced by various related techniques such as plasma assistance, photo assistance, laser assistance, as well as other techniques.
  • the co-deposition of platinum and ruthenium is conducted using a CVD process wherein a ruthenium precursor is delivered to a reaction chamber along with a platinum precursor.
  • the method is carried out in the presence of an oxidizing reactant gas, such as O 2 , NO, N 2 O, O 3 , hydrogen peroxide, organic peroxides such as T-butyl peroxide, or any other oxidizing agent.
  • a liquid precursor is contained in a bubbler reservoir through which a carrier gas, such as helium or any other inert, i.e..
  • nonreactive gas e.g., nitrogen, argon, neon, and xenon
  • a flow of carrier gas having a flow in the range of about one seem to about 100 seem of a nonreactive gas, i.e., nonreactive with other gases of the process is used in a bubbler having a pressure in the range of about 0.5 to about 50 torr and a temperature in the range of about 30° C to about 70° C to deliver a platinum precursor to the reaction chamber.
  • a carrier gas i.e., a nonreactive gas
  • a carrier gas having a flow in a range of about one seem to about 10 seem
  • a bubbler containing a ruthenium precursor at the conditions of about 0.5 torr to about 100 torr and a temperature of about 20° C to about 50° C to deliver the ruthenium precursor to the reaction chamber.
  • the reactant oxidizing gas is provided to the reaction chamber at a flow of about 0 seem to about 500 seem.
  • the manner in which the gases are introduced into the reaction chamber may include one of various techniques.
  • the introduction may be accomplished with the use of .-ompounds v hich are gases at room temperature or by heating a volatile compound and delivering the volatile compound to the reaction chamber using a carrier gas.
  • solid precursors and various methods of vaporizing such solid precursors may also be used for introduction of reactant compounds into the chamber.
  • the present invention is not limited to any particular technique.
  • the reactant gases are admitted at separate inlet ports.
  • a dilution gas i.e., a gas that is non-reactive with the reactant gases
  • argon gas may be introduced into the chamber at a varied flow rate.
  • the reactant gas mixture in the reaction chamber includes at least the ruthenium precursor gas, the platinum precursor gas, and optionally the oxygen reactant gas and/or a dilution gas.
  • the partial pressure of ruthenium precursor gas is kept sufficiently low such that the ruthenium deposited is within the ranges described for forming the preferred platinum:ruthenium composition of the alloy layer 14 described above.
  • This partial pressure may be controlled by controlling the flow of the inert gas, e.g., helium, through the bubbler containing the ruthenium precursor or through control of other parameters of the process, such as temperature and pressure of the bubbler.
  • the reaction chamber pressure is preferably maintained at a deposition pressure of about 0.5 torr to about 5 torr.
  • the deposition temperature at the wafer surface upon which the platinumrruthenium alloy layer 14 is deposited is held at a temperature in a range of about 200° C to about 400° C. Any ruthenium-containing precursor and platinum-containing precursor may be used in accordance with the present invention.
  • the ruthenium precursors are liquid ruthenium complexes of the following formula (Formula I): (diene)Ru(CO) 3 wherein: “diene” refers to linear, bran, lied, or cycl - dienes, bicyclic dienes, tricyclic dienes, fluorinated derivatives thereof, combinations thereof, and derivatives thereof additionally containing heteroatoms such as halide, Si, S, Se, P, As, or N.
  • diiene refers to linear, bran, lied, or cycl - dienes, bicyclic dienes, tricyclic dienes, fluorinated derivatives thereof, combinations thereof, and derivatives thereof additionally containing heteroatoms such as halide, Si, S, Se, P, As, or N.
  • the ruthenium precursors used according to the present invention include one of C 6 H 8 Ru(CO) 3 , bis(cyclopentadienyl) ruthenium (II), triruthenium dodecacarbonyl, and cyclopentadienyl dicarbonyl ruthenium (II) dimer.
  • Figure 2 shows a structure 20 including substrate assembly 22 and a stack 24.
  • the stack 24 includes conductive layers 31-34.
  • One or more of the conductive layers 31-34 are platinum:ruthenium alloy layers according to the present invention.
  • the one or more conductive layers may include conductive layers formed of various conductive materials.
  • the conductive layers may include, but are clearly not limited to, layers formed from metals such as platinum, paladium, rhodium, ruthenium, osmium, and iridium; metal alloys such as platinum:rhodium, platinum:ruthenium, and platinum:iridium; metal oxides such as ruthenium oxide, rhodium oxide, and iridium oxide; metal alloy oxides such as platinum: rhodium oxide, platinum:ruthenium oxide, and platinum:iridium oxide; metal nitrides such as titanium nitride, tungsten nitride, and tantalum nitride; metal suicides such as titanium suicide, ruthenium suicide, rhodium suicide, and iridium suicide.
  • the stack 24 may be used for one or numerous applications, e.g., interconnection applications, capacitor applications, etc.
  • stack 24 may be used as an electrode for a storage cell capacitor with substrate assembly 22 including a silicon containing surface 23.
  • the barrier properties of the stack 24 must prevent silicon diffusion from silicon-containing surface 23.
  • the layer 31 may be formed as a platinum:ruthenium alloy layer to prevent diffusion of silicon from silicon- containing surface 23 through stack 24 to adjacent layer or layers 29.
  • layer 34 or one of the other layers may also be formed as a platinum :ruthenium alloy barrier layer according to the present invention.
  • platinum :ruthenium alloy layer according to the present invention may be used in a stack of layers for a variety of applications and the stack may include one or more platinum:ruthenium alloy layers. Further, the composition of such platinum:ruthenium layers used in the same stack may differ.
  • Figure 3 shows a structure 50 including substrate assembly 52 and capacitor structure 54.
  • Capacitor structure 54 includes a first electrode 56, a second electrode 60, and a high dielectric constant layer 58 interposed therebetween.
  • the dielectric layer may be any suitable material having a desirable dielectric constant, such as Ta 2 O 5 , Ba x Sr (1.x) TiO 3 [BST], BaTiO 3 , SrTiO 3 , PbTiO 3 , Pb(Zr,Ti)O 3 [PZT], (Pb,La)(Zr,Ti)O 3 [PLZT], (Pb,La)TiO 3 [PLT], KNO 3 , and LiNbO 3 .
  • diffusion barrier properties of the electrodes is particularly important.
  • the electrode layer or electrode stack must act as an effective barrier to the diffusion of oxygen, particularly due to the processes used to form the high dielectric constant materials.
  • Such diffusion barrier properties are particularly required when the substrate assembly 52 includes a silicon-containing surface 53 upon which the capacitor is formed, e.g., polysilicon, silicon substrate material, N- doped silicon, P-doped silicon, etc., since oxidation of the diffused silicon may result in degraded capacitance, e.g., capacitance for a memory device.
  • the co- deposition of the platinum with the ruthenium enhances the barrier properties of the layer formed and thus provides a significant improvement over pure platinum for electrode applications.
  • either of the electrodes 56, 60 may be formed as a single layer of platinum:ruthenium alloy material. Further, such electrodes 56, 60 may be formed as a stack such as described with reference to Figure 2 including one or more layers of a platinum:ruthenium alloy material and one or more additional conductive layers.
  • CMOS devices memory devices, logic devices, etc.
  • the platinum :ruthenium alloy barrier layer may be used for any application requiring diffusion barrier characteristics, particularly those for preventing diffusion of oxygen and silicon into adjacent layers.
  • a device structure 100 is fabricated in accordance with conventional processing techniques through the formation of an opening 184 prior to depositing a bottom electrode structure on the surfaces 185, 186 defining the opening 184.
  • a platinum:ruthenium alloy bottom electrode is then formed in opening 184.
  • the device structure 100 includes field oxide regions 105 and active regions, i.e., those regions of the substrate 107 not covered by field oxide.
  • Suitable source/drain regions 125, 130 are created in silicon substrate 107.
  • An insulative layer of oxide material 140 is formed over regions of FET 122 and word line 121.
  • Polysilicon plug 165 is formed to provide electrical communication between substrate 107 and the storage cell capacitor to be formed thereover.
  • Various layers are formed over the polysilicon plug 165, including layers 167 and 175.
  • such layers may be titanium nitride, tungsten nitride, or any other metal nitride which acts as a barrier, and may also include one or more platinum :ruthenium alloy barrier layers as described herein. Thereafter, another insulative layer 183 is formed and an opening 184 is defined therein.
  • the opening 184 is a small high aspect ratio opening.
  • small high aspect ratio openings have feature sizes or critical dimensions below about 1 micron (e.g., such as a diameter or width of an opening being less than about 1 micron) and aspect ratios greater than about 1.
  • Such aspect ratios are applicable to contact holes, vias, trenches, and any other configured openings.
  • a trench having an opening of 1 micron and depth of 3 microns has an aspect ratio of 3.
  • the present invention is particularly beneficial for forming diffusion barrier layers in small high aspect ratio features due to the use of CVD processes for forming conformal layers of the platinum :ruthenium alloy material over step structures.
  • a platinum:ruthenium alloy barrier layer 187 is formed on the bottom surface 185 and the one or more side walls 186 defining opening 184.
  • a layer of platinum:ruthenium alloy material is first co-deposited over the entire structure including the bottom surface 185 and sidewalls 186 and then formed into lower electrode 187. For example, the layer may be etched or planarized to remove the desired regions for forming the bottom electrode 187.
  • dielectric layer 191 is then formed relative to the platinum:ruthenium alloy diffusion barrier layer 187. Further thereafter, the second electrode 192 is formed relative to the dielectric material 191.
  • such an electrode may be of any conductive material such as the platinum:ruthenium alloy barrier material as described herein, tungsten nitride, titanium nitride, tantalum nitride, ruthenium, rhodium, iridium, ruthenium oxide, iridium oxide, any combination thereof, or any other conductive material typically used as an electrode of a storage cell capacitor.
  • the bottom electrode formed of platjr.u-n:rutheniurrj alloy material is conformally formed of uniform thickness using CVD within opening 184 providing a desired resistivity and barrier properties.
  • container capacitors typically includes electrodes formed on surfaces requiring conformal formation of a bottom electrode.
  • Such a container capacitor storage cell is described in U.S. Patent No. 5,270,241 to Dennison, et al., entitled “Optimized Container Stack Capacitor DRAM Cell Utilizing Sacrificial Oxide Deposition and Chemical Mechanical Polishing,” issued December 14, 1993.
  • the bottom electrode 187 may include a stack of layers with one or more of the layers being a platinum:ruthenium alloy barrier layer as described previously herein.
  • device structure 200 is fabricated in accordance with conventional processing techniques through the formation of contact opening 259 prior to metahzation of the contact area 255 of substrate 207.
  • the device structure 200 includes field oxide regions 205 and active areas, i.e., those regions of substrate 207 not covered by field oxide.
  • word line 221 and FET 222 are Formed relative to the field oxide regions 205 in the active areas.
  • doped source/drain regions 225, 230 are formed as known to one skilled in the art.
  • a conformal layer of oxide material 240 is formed thereover and contact opening 259 is defined therein to the contact area 255 of doped region 230 of silicon substrate 207. Thereafter, one or more metahzation or conductive layers are formed in the contact opening 259 for providing electrical connection to substrate region 230.
  • various materials may be formed in contact opening 259, such as titanium nitride or other diffusion barrier materials.
  • contact liner 285 is formed of platinum:ruthenium alloy material according to the present invention on bottom surface 260 and the one or more side walls 261 defining the opening 259. The platinum:ruthenium alloy layers are generally deposited over the entire substrate assembly and then planarized to form the contact liner 285. Thereafter, a conductive material 276 is formed in the contact opening for providing connection to doped region 230 of substrate 207.
  • Figures 6A and 6B show depth profiles of a co-deposited platinum :ruthenium layer before and after an oxygen anneal, respectively.
  • the small lab scale reaction CVD chamber was built by MDC Vaccuum Products Corp. (Hayward, CA) and the glass research bubbler is from Technical Glass Service (Boise, ID).
  • the conditions used for the co-deposition of the platinum:ruthenium layer include:
  • Platinum Carrier Gas for use through Bubbler 5 seem of helium.
  • Ruthenium Carrier Gas for use through Bubbler 10 seem of helium.
  • Reaction Chamber Conditions pressure of 5 torr, deposition temperature of 300 ° C at wafer surface.
  • Oxygen Reaction Gas 10 seem.
  • the depth profile was attained by using an XPS device available under the trade designation of Phi ( ⁇ ) 5600 from Physical Electronics (Eden Prairie, MN).
  • Sputtering was performed with a 4 keV Argon ion beam rastored over a 3 mm area.
  • the sputter time for the depth profile of Figure 6 A was 13 minutes and the sputter time for the depth profile of Figure 6B was 14.3 minutes.
  • the co-deposited platinum :ruthenium layer deposited according to the above conditions is shown therein including at a depth of 200 A a platinum composition of about 70% and a ruthenium composition of about 15%.
  • Figure 6B shows the co-deposited platinum:ruthenium layer after being subjected to a rapid thermal oxidation anneal at 750° C for a period of 30 seconds.
  • Figure 6C shows an XPS montage display showing the i signal during profile through the platinum :ruthenium layer, after annealing in oxygen. The peak shape shows the lack of SiO 2 at the interface and only traces of Si at the surface. There appears to be no silicon diffusion or oxygen diffusion through the barrier layer and therefore, no silicon dioxide formation.

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AU57996/99A AU5799699A (en) 1998-09-03 1999-08-31 Diffusion barrier layers and methods of forming same
JP2000569428A JP5328065B2 (ja) 1998-09-03 1999-08-31 拡散バリアー層及びその製造方法

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US09/146,866 US6323081B1 (en) 1998-09-03 1998-09-03 Diffusion barrier layers and methods of forming same
US09/146,866 1998-09-03

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