USRE44251E1 - Circuit board for mounting electronic parts - Google Patents

Circuit board for mounting electronic parts Download PDF

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Publication number
USRE44251E1
USRE44251E1 US10/839,813 US83981304A USRE44251E US RE44251 E1 USRE44251 E1 US RE44251E1 US 83981304 A US83981304 A US 83981304A US RE44251 E USRE44251 E US RE44251E
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United States
Prior art keywords
connection terminal
terminal group
layer
substrate
board according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US10/839,813
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English (en)
Inventor
Motoo Asai
Yoichiro Kawamura
Yoji Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
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Filing date
Publication date
Priority claimed from US09/412,877 external-priority patent/US6384344B1/en
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to US10/839,813 priority Critical patent/USRE44251E1/en
Application granted granted Critical
Publication of USRE44251E1 publication Critical patent/USRE44251E1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
    • H01R12/50—Fixed connections
    • H01R12/51—Fixed connections for rigid printed circuits or like structures
    • H01R12/52—Fixed connections for rigid printed circuits or like structures connecting to other rigid printed circuits or like structures
    • H01R12/523—Fixed connections for rigid printed circuits or like structures connecting to other rigid printed circuits or like structures by an interconnection through aligned holes in the boards or multilayer board
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/114—Pad being close to via, but not surrounding the via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0212—Resin particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09727—Varying width along a single conductor; Conductors or pads having different widths
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
    • H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
    • H05K3/184—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method using masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor

Definitions

  • the present invention relates to a board that has connection terminals formed on both the top and back surfaces thereof and on which electronic circuit parts are to be mounted.
  • a wiring board 21 for mounting electronic circuit parts is known as one conventional printed circuit board for mounting a bare chip like a flip chip or a package like a BGA (Bump Grid Array).
  • This type of wiring board 21 has a substrate 22 that has conductor layers formed on both the top and back surfaces by mainly a subtractive method.
  • a parts mounting area is provided in the center of the top surface of the substrate 22 .
  • Formed densely in this area are multiple pads 23 which constitute a first pad group.
  • the individual pads 23 correspond to bumps BP positioned on the bottom of a bare chip C 1 .
  • Multiple pads 24 which constitute a second pad group are formed on the peripheral portion of the back of the substrate 22 . Formed on those pads 24 are bumps 25 as projecting electrodes for connection to a mother board.
  • Multiple through holes 26 are formed through the substrate 22 at the peripheral portion of the substrate 22 . Those through holes 26 are connected to the pads 23 on the top surface via a conductor pattern 27 , which is formed on the top surface of the substrate 22 . The through holes 26 are also connected to the pads 24 on the back surface via a conductor pattern 28 , which is formed on the back surface of the substrate 22 . Accordingly, the first group of pads 23 are electrically connected to the second group of pads 24 respectively on this wiring board 21 .
  • the through holes 26 may be formed in the center portion of the board, not the peripheral portion thereof. In this case, however, dead space where wiring is not possible is formed in the portion where the through holes 26 are formed. Thus, to secure wiring space, the board itself would inevitably become larger.
  • signal lines 62 connected to pads 61 have a given width irrespective of the positions of the signal lines. In this case, it is necessary to set the widths of the signal lines 62 smaller, so that the wiring resistance is likely to increase and line disconnection is apt to occur. This reduces the reliability of the wiring board 60 .
  • each signal line 62 consists of a first wiring pattern 62 b with a predetermined width and a second wiring pattern 62 a having a width greater than that of the first wiring pattern 62 b, as shown by two-dot chain lines in FIG. 9 .
  • the first wiring patterns 62 b are arranged at a high wiring-density portion and the second wiring patterns 62 a are arranged at a low wiring-density portion to facilitate the wiring and suppress the occurrence of line disconnection.
  • first wiring pattern 62 b is directly connected to the associated second wiring pattern 62 a in this case, two sharp corners are formed at the connected portion. Stress is apt to concentrate on those corners, which raises another problem that cracks 64 are easily formed in a permanent resist 63 near the corners as shown in FIG. 10 .
  • the present invention has been accomplished, and it is a primary objective of the present invention to improve the wiring efficiency while avoiding the enlargement of the entire board. Further, it is another objective of this invention to improve the wiring efficiency while suppressing an increase in the wiring resistance and the occurrence of line disconnection and preventing the occurrence of cracks in a permanent resist.
  • a board for mounting electronic circuit parts comprises:
  • the first connection terminals are densely formed on the substrate and the second connection terminals are formed discretely.
  • the first connection terminals are connected to the second connection terminals via the via holes as well as the through holes. It is therefore possible to shorten the wires without producing dead space and improve the wiring efficiency.
  • This feature can provide a device which is equipped with electronic circuit parts and has an improved processing speed.
  • a board for mounting electronic circuit parts comprising a plurality of connection terminals and a plurality of signal lines formed on an insulator layer.
  • the plurality of connection terminals are formed densely and are respectively connected to said signal lines.
  • Each of the signal lines include a plurality of wiring patterns with different widths and a taper-shaped pattern connecting said wiring patterns with the different widths so as to have a continuously changing width.
  • Each of the signal lines has a smaller width at an area having a relatively high wiring density than at an area having a relatively low wiring density.
  • each signal line is so formed that it has a smaller width at an area having a relatively high wiring density than at an area having a relatively low wiring density, it is possible to form a wiring pattern having narrow line widths in the high wiring density area and having wide line widths in the low wiring density area. This suppresses the resistance and prevents line disconnection. It is also possible to secure the insulation between patterns in the high wiring density area.
  • wiring patterns with different widths can be connected by the taper-shaped pattern, insulation between signal lines can be secured without causing cracks in the permanent resist and the wiring resistance is not increased.
  • FIG. 1 is a schematic cross-sectional view of a wiring board according to the first embodiment of this invention
  • FIG. 2 is a schematic cross-sectional view of a wiring board according to a modification of the first embodiment
  • FIG. 3 is a partial plan view of a wiring board according to the second embodiment of this invention.
  • FIG. 4 is a cross-sectional perspective view showing parts of signal lines used on the wiring board in FIG. 3 ;
  • FIGS. 5A through 5C are partial plan views illustrating some variations of the signal lines in FIG. 3 ;
  • FIG. 6 is a partly enlarged plan view showing an array of pads used for the wiring board in FIG. 3 ;
  • FIG. 7 is a partial plan view of a wiring board according to a modification of the second embodiment.
  • FIG. 8 is a schematic cross-sectional view of a conventional wiring board
  • FIG. 9 is a partial plan view showing a conventional wiring board corresponding to the wiring board in FIG. 3 ;
  • FIG. 10 is a cross-sectional perspective view depicting parts of signal lines used on the wiring board in FIG. 9 .
  • a wiring board 1 for mounting electronic circuit parts has a substrate 2 whose top surface S 1 and back surface S 2 are both usable.
  • the substrate 2 has conductor layers 3 and 4 formed on both the top surface S 1 and back surface S 2 of a base material 5 of resin by a subtractive method.
  • a plurality of through holes 6 are formed in the substrate 2 to permit the conductor layers 3 and 4 to pass through the substrate 2 and over both the top and back surfaces of the substrate 2 . Those through holes 6 are filled with a heat-resistant resin 7 .
  • build-up multilayer interconnection layers B 1 and B 2 each having interlayer dielectric films 8 a hand 8 b and conductor layers 9 a and 9 b alternately stacked one on another.
  • a permanent resist 10 of a photosensitive resin is locally formed on the top of the first interlayer dielectric film 8 a which is close to the top surface S 1 .
  • the inner conductor layer 9 a is formed in the portion where the permanent resist 10 is not formed.
  • This inner conductor layer 9 a is electrically connected to the inner conductor layer 3 on the top surface S 1 of the substrate 2 by via holes 11 formed in the first interlayer dielectric film 8 a.
  • another permanent resist 10 is locally formed on the second interlayer dielectric film 8 b provided on the first interlayer dielectric film 8 a.
  • the outer conductor layer 9 b is formed where this permanent resist 10 is not formed.
  • the outer conductor layer 9 b is electrically connected to the inner conductor layer 9 a by via holes 11 formed in the second interlayer dielectric film 8 b.
  • the center portion of the top surface of the second interlayer dielectric film 8 b, on the top surface (S 1 ) side or the center portion of the first surface of the substrate 1 forms an area where an LSI bare chip C 1 as electronic circuit parts is to be mounted.
  • Multiple pads 12 A and 12 B, which constitute a first connection terminal group or a pad group, are formed densely in this area. Those pads 12 A and 12 B correspond to bumps BP formed at the bottom of the chip C 1 .
  • the outermost pads in the first pad group are called “external pads 12 B”.
  • the pads located in the center portion in the first pad group or the pads located inward of the external pads 12 B are called “internal pads 12 A”.
  • this embodiment has only one outermost row of external pads 12 B, the first to fifth rows of external pads starting from the outermost row can be used as external pads.
  • the pads excluding those external pads are the internal pads 12 A.
  • a permanent resist 10 is locally formed on the top of the first interlayer dielectric film 8 a, which is close to the back surface S 2 .
  • the inner conductor layer 9 a is formed where the permanent resist 10 is not formed.
  • This inner conductor layer 9 a is electrically connected to the inner conductor layer 4 on the back surface S 2 of the substrate 2 by via holes 11 formed in the first interlayer dielectric film 8 a.
  • another permanent resist 10 is locally formed on the second interlayer dielectric film 8 b provided on the first interlayer dielectric film 8 a on the back surface S 2 .
  • the outer conductor layer 9 b is formed where this permanent resist 10 is not formed.
  • the outer conductor layer 9 b is electrically connected to the inner conductor layer 9 a by via holes 11 formed in the second interlayer dielectric film 8 b on the back surface S 2 .
  • Multiple pads 13 which constitute a second connection terminal group or a pad group, are arranged discretely on the outer peripheral portion of the second interlayer dielectric film 8 b on the back surface side, or on the outer peripheral portion, of the second surface of the wiring board 1 . Formed on those pads 13 are bumps 14 as projecting electrodes to make electric connection to an unillustrated mother board.
  • the external pads 12 B in the first pad group are electrically connected to the associated via holes 11 by way of the outer conductor layer 9 b, which extends toward the board's outer peripheral portion.
  • the internal pads 12 A are constituted of the via holes 11 , which are made by forming metal films on the side walls and bottom walls of holes formed in the interlayer dielectric film 8 b and connecting the conductor layers 9 b and 9 a by those metal films.
  • Solder SL is filled in each via hole 11 and protrudes from the hole 11 to constitute a so-called solder bump.
  • the bumps of the solder SL are connected to the bare chip C 1 .
  • the internal pads 12 A it is unnecessary to lead wires out toward the periphery of the board and is possible to shorten the wire lengths and increase the wire density.
  • the via holes 11 of the second interlayer dielectric film 8 b are further electrically connected to the associated through holes 6 by the inner conductor layer 9 a, the via holes 11 and the inner conductor layer 3 .
  • the inner conductor layer 4 which is connected to the through holes 6 , is electrically connected to the pads 13 in the second pad group by way of the via holes 11 , the inner conductor layer 9 a and the outer conductor layer 9 b.
  • the inner conductor layers 3 , 4 and 9 a and the outer conductor layer 9 b, which connect the first pad group to the second pad group, are laid out and extend in a direction from the center portion toward the board's outer peripheral portion, that is, in the radial direction.
  • solder resists 19 are formed on the surfaces of the build-up multilayer interconnection layers and on the connecting surface to the mother board.
  • the solder resists 19 are provided to protect the conductor layers and prevent melted solder from flowing out to cause short-circuiting between patterns.
  • the interlayer dielectric films 8 a, 8 b constituting the respective build-up layers B 1 , B 2 are preferably formed using a mixture of (a) a photosensitive resin which is hardly soluble in acids or oxidizing agents and (b) cured heat-resistant resin particles which are soluble in acids or oxidizing agents.
  • the reason for this is that interlayer dielectric films containing such cured heat-resistant resin particles can facilitate developing treatment, and even if there are residues of developed portions on the substrate, such residual portions can be removed in a roughening treatment. Accordingly, even when the via holes 11 are of a high aspect ratio, such residual developed portions are hard to form. In the case where a photosensitive resin only is used, formation of via holes 11 having a diameter of about 80 ⁇ m or less becomes difficult.
  • the interlayer dielectric films 8 a, 8 b are preferably formed using a mixture obtained by adding (b) cured heat-resistant resin particles which are soluble in acids or oxidizing agents to a composite resin including (a1) a resin hardly soluble in acids or oxidizing agents, which is obtained by photosensitizing a heat-curing resin and (a2) a thermoplastic resin.
  • the acids or oxidizing agents referred to herein mean chromic acid, chromates, permanganates, hydrochloric acid, phosphoric acid, formic acid sulfuric acid and hydrofluoric acid.
  • the resin (a1) hardly soluble in these acids or oxidizing agents, which is obtained by photosensitizing the heat-curing resin, is preferably at least one resin selected from epoxyacrylates and photosensitive polyimides (photosensitive PI). The reason is that these resins have high heat resistance and high strength.
  • the thermoplastic resin (a2) is preferably at least one resin selected from polyethersulfones (PES), polysulfones (PSF), phenoxy resins and polyethylenes (PE).
  • PES polyethersulfones
  • PSF polysulfones
  • PE polyethylenes
  • the granular heat-resistant resin (b) is preferably at least one selected from amino resin particles and epoxy resin particles (EP resins).
  • EP resins epoxy resin particles
  • an epoxy resin cured by an amine type curing agent has a hydroxyether structure, and grains of such resin have a property of being dissolved, easily in the resin (a1) or (a2), advantageously.
  • the amino resin can be selected, for example, from melamine resins, urea resins and guanamine resins. Selection of a melamine resin is preferred among others not only for its electrical properties but also because properties to be determined by PCT (pressure cooker test) and HHBT (high humidity bias test) can be improved.
  • the heat-resistant particles (b) preferably has a size of 10 ⁇ m or less. This is because the thickness of the interlayer dielectric films can be reduced, and fine patterns can be formed.
  • the heat-resistant resin particles can be selected from various shapes such as spheres, splinters and aggregates.
  • the thus constituted wiring board 1 can be produced, for example, according to the following procedures.
  • an adhesive to be employed for forming the interlayer dielectric films 8 a, 8 b by means of the additive method can be prepared as follows. This adhesive contains a component which is hardly soluble in acids or oxidizing agents and a component which is soluble in them.
  • the mixing ratio of the components is as follows:
  • TOREPAL EP-B trade name, manufactured by Toray Industries, Inc.
  • both surfaces of a substrate 2 having conductor layers 3 , 4 , through holes 6 and a heat-resistant resin 7 are entirely coated with this adhesive, followed successively by vacuum drying at 25° C. or air drying at 80° C., formation of openings for via holes by ultraviolet curing and developing treatments, and heat curing.
  • a first interlayer dielectric film 8 a is formed on each surface. 5.
  • the surface of each first interlayer dielectric film 8 a is treated with a roughening agent such as chromic acid to form a rough surface having a multiplicity of anchoring pits. 6.
  • the via holes 11 are formed by covering the wall surface and the bottom of each hole defined in the layer insulating material with a plating film so as to electrically connect the lower and upper conductor layers 9 a and 9 b.
  • the wall surface of each hole is roughened (not shown) so that the plating will adhere intimately therewith and can hardly separate therefrom. 7.
  • the same adhesive is applied to the thus treated first interlayer dielectric film 8 a and then cured to form a second interlayer dielectric film 8 b on each side. 8.
  • the surface of the resulting second interlayer dielectric film 8 b is then treated with a roughening agent to form a rough surface. Subsequently, application of catalyst nuclei, formation of permanent resist 10 , activating treatment and electroless copper plating are carried out to form outer conductor layers 9 b, pads 12 A, 12 B and 13 and via holes 11 at predetermined positions.
  • a photosensitive resin is applied on each surface of the thus treated board, and the resulting board is subjected to light exposure and developing treatments to form a solder resist 19 , with the pads 12 A, 12 B and 13 being exposed. 9. A solder layer SL is formed on these pads 12 A, 12 B and 13 .
  • a nickel-gold plating (not shown) is applied to the pads 12 A, 12 B and 13 , and then a solder paste is printed thereon by means of the printing method and is subjected to fusing to form solder bumps, or a film having a solder pattern formed thereon is superposed onto the pads 12 A, 12 B and 13 to transfer the solder pattern thereto with heating and form solder layers (solder bumps).
  • the desired wiring board 1 is completed by going through the procedures described above. If a bare chip C 1 is mounted on the thus formed wiring board 1 , an electronic-circuit-parts mounted device M 1 as shown in FIG. 1 can be obtained.
  • none of the internal pads 12 A located in the center portion in the first pad group are connected to the outer conductor layer 9 b, but the via holes 11 serve as the internal pads 12 A to be electrically connected directly to the inner conductor layer 9 a. That is, the individual internal pads 12 A are electrically connected to the inner conductor layer 9 a via the associated via holes 11 .
  • an adhesive which is of a mixture of a photosensitive resin hardly soluble in acids or oxidizing agents and heat-resistant resin particles soluble in acids or oxidizing agents, is employed when forming the interlayer dielectric films 8 a, 8 b constituting the build-up multilayer interconnection layers B 1 , B 2 . Therefore, when the interlayer dielectric films 8 a, 8 b are subjected to ultraviolet exposure so as to form via holes, residues of developed portions scarcely remain at the positions where the via holes are formed.
  • the reason for it is not clarified, it is surmised that in the case where the heat-resistant resin particles are present, the total amount of resin to be dissolved is smaller than in the case where the photosensitive resin only is to be dissolved, and even if residues of developed portions are present, the heat-resistant resin particles-and the photosensitive resin are dissolved together when the heat-resistant resin particles are to be dissolved by the roughening treatment.
  • the inner conductor layers 3 , 4 and 9 a and the outer conductor layer 9 b, which connect the first pad group 12 to the second pad group 13 are connected by the via holes 11 and are laid out in the radial direction (from the center portion toward the board's outer peripheral portion).
  • This structure differs from the conventional structure shown in FIG. 8 in which wires led out to the outer peripheral portion are led back toward the center portion.
  • the wires connecting the pads 12 to the pads 13 become shorter by the elimination of such conventional led-back wires, thus positively improving the wiring efficiency. It is therefore possible to accomplish a faster processing speed.
  • the wiring board 1 of this embodiment is also characterized in that wires are formed on the conductor layers 9 a and 9 b of the build-up multilayer interconnection layers B 1 and B 2 as well as on the conductor layers 3 and 4 of the substrate 2 . Even though the through holes 6 are formed in the substrate 2 , such formation does not affect the wiring, and the space on the substrate 2 can be used effectively. This means that the enlargement of the board 1 for mounting electronic circuit parts can be avoided.
  • the build-up multilayer interconnection layers B 1 and B 2 having substantially the same thicknesses are respectively provided on the top surface S 1 and the back surface S 2 .
  • stresses to be applied on both sides of the substrate 2 become substantially equal to each other to cancel each other.
  • the wiring board 1 is therefore not easily deformed.
  • the wiring board 1 can be made more compact with higher density as compared with the case where the build-up multilayer interconnection layers are formed only on, for example, the top surface S 1 .
  • This embodiment may be modified as follows.
  • FIG. 2 illustrates an electronic-circuit-parts mounted device M 2 which has the bare chip C 1 mounted on another wiring board 18 .
  • This wiring board 18 is provided with a three-layered build-up multilayer interconnection layer B 3 only on the top surface S 1 .
  • the pads 13 forming the second pad group are connected to the conductor layer 4 formed on the back surface S 2 .
  • the conductor layer 4 on the back surface S 2 is entirely covered with the solder resist 19 .
  • This structure also has the same function and advantages as the above-described embodiment.
  • the number of stacked layers in each of the build-up multilayer interconnection layers B 1 -B 3 i.e., the number of the interlayer dielectric films 8 a and 8 b is not limited to two or three, but may be set to other numbers as well. Further, the number of stacked layers on the top surface S 1 should not be necessarily equal to the number of stacked layers on the back surface S 2 .
  • a multilayer substrate including four to eight layers may be used as the substrate. From the viewpoint of reducing the cost, it is advantageous to select a single-layer substrate 2 , whereas to achieve a higher density and a smaller size, a multilayer substrate is advantageous.
  • pins may be provided on the pads 13 that constitute the second connection terminal group. It is also possible to eliminate the provision of either the bumps 14 or the pins. Unlike in the above-described embodiments, there may be a plurality of parts mounting areas.
  • the pads 13 constituting the second pad group may be provided entirely on the build-up multilayer interconnection layer B 2 on the back surface S 2 . This structure allows more pads 13 to be provided.
  • the conductor layers 9 a and 9 b constituting the build-up multilayer interconnection layers B 1 -B 3 may be formed by metal plating (e.g., electroless nickel plating or electroless gold plating) other than electroless copper plating.
  • metal plating e.g., electroless nickel plating or electroless gold plating
  • metal layers that are formed by a physical thin film forming method like sputtering may be selected.
  • Electronic circuit parts to be mounted on the wiring board 1 may be a semiconductor package, such as a BGA (Bump Grid Array), QFN (Quatro Flat Non-Leaded Array) or PGA (Pin Grid Array) having short pins, as alternatives to the bare chip 2 in the above-described embodiment.
  • a semiconductor package such as a BGA (Bump Grid Array), QFN (Quatro Flat Non-Leaded Array) or PGA (Pin Grid Array) having short pins, as alternatives to the bare chip 2 in the above-described embodiment.
  • the internal pads 12 A may not be connected to directly to the top surfaces of the via holes 11 , but may be connected to the via holes 11 by way of the outer conductor layer 9 b, which does not extend to the outer peripheral portion of the board.
  • thermoplastic resin obtained by sensitizing a heat-curing resin
  • thermoplastic resin thermoplastic resin
  • heat-resistant resin a1+a2+b
  • FIG. 3 shows approximately a quarter of a wiring board 51 for mounting electronic circuit parts.
  • the wiring board 51 has a glass epoxy substrate 54 as a core material. It is also possible to employ substrates other than the glass epoxy substrate 54 , such as a polyimide substrate and a BT (bismaleimidotriazine) resin substrate.
  • An adhesive layer (dielectric film) 55 is formed on each surface of the substrate 54 using an adhesive specific to the additive method. The surface of each adhesive layer 55 is roughened so as to have a multiplicity of anchoring pits.
  • the adhesive employable here a mixture of a photosensitive resin, which can be made hardly soluble in acids or oxidizing agents by a curing treatment, and a cured granular heat-resistant resin soluble in acids or oxidizing agents is employed.
  • the adhesive having such composition is suitable for forming fine images with high accuracy. Details of the composition of the adhesive are the same as in the foregoing embodiment.
  • Each adhesive layer 55 has a permanent resist 56 which is of a photosensitive resin formed on the roughened surface thereof.
  • the portions having no permanent resist 56 have a conductor layer such as pads 53 formed by electroless copper plating.
  • Another conductor layer (not shown) is formed on the rear side of the wiring board 51 , i.e., the surface opposed to the mother board.
  • a parts mounting area A 1 is defined approximately in the center of the top surface of the wiring board 51 where a chip is to be mounted.
  • a plurality of signal lines 52 and a plurality of circular pads 53 are formed on the top surface of the wiring board 51 at the peripheral portion of the parts mounting area A 1 .
  • Those pads 53 are grouped into four rows of pads L 1 to L 4 at the peripheral portion of the parts mounting area A 1 , which are arranged in a zigzag fashion.
  • One signal line 52 is connected to each pad 53 . Most of the signal lines 52 extend radially toward the board's outer peripheral portion.
  • One of the ends of such signal lines 52 are respectively connected to a plurality of pads (not shown), which are discretely arranged on the back surface of the board 51 by way of through holes (not shown) formed discretely at the board's outer peripheral portion. Some of the signal lines 52 are very short and are connected to adjoining interstitial via holes 57 .
  • each signal line 52 has a first wiring pattern 58 having a predetermined width, a second wiring pattern 59 wider than the first wiring pattern 58 , and a nearly-trapezoidal taper-shaped pattern 60 which connects both wiring patterns 58 and 59 .
  • the first wiring pattern 58 is located in substantially the center portion of the board, which has a relatively high wiring density and is connected to the associated pad 53 .
  • the second wiring pattern 59 is located in the outer peripheral portion of the board which has a relatively low wiring density. Therefore, the width of each signal line 52 varies in accordance with a change in wiring density.
  • the first wiring pattern 58 and the second wiring pattern 59 are connected together along a common center line CL by the taper-shaped pattern 60 .
  • Both side edges T 1 of the taper-shaped pattern 60 are inclined to the center line CL and both side edges of each wiring pattern 59 by a predetermined angle ⁇ (see FIG. 5 ).
  • the width of the taper-shaped pattern 60 is so set as to increase toward the width of the second wiring pattern 59 from the width of the first wiring pattern 58 .
  • the angle ⁇ should range from 10° to 45°, preferably from 15° to 40°, particularly from 20° to 35°.
  • the angle ⁇ if set to 10° to 45°, is convenient in the case where automatic wiring is done by a CAD (Computer Aided Design) system. If the angle ⁇ is less than 10° as exemplified in FIG. 5C , the taper-shaped pattern 60 becomes long, which may lead to some difficulty in accomplishing the wiring. If the angle ⁇ exceeds 45°, as exemplified in FIG. 5B , however, it may not be possible to prevent the occurrence of cracks in the permanent resist 56 .
  • portions C 1 and C 2 of the taper-shaped pattern 60 which are side edges to be coupled to the first and second wiring patterns 58 and 59 , are rounded to remove the sharp corners.
  • the sizes W 1 to W 9 of the individual parts on the wiring board 51 in this embodiment are set in the following ranges.
  • the pitch between the pads 53 indicated by W 1 in FIG. 6 is in the range of 11 mils to 17 mils, and the pitch between the pads 53 indicated by W 2 is in the range of 5.5 mils to 8.5 mils.
  • the pitch between the pads 53 indicated by W 3 ranges from 8 mils to 12 mils.
  • the maximum inside diameter of the interstitial via holes 57 indicated by W 4 is in the range of 4 mils to 6 mils.
  • the diameter of the pads 53 is equal to this inside diameter.
  • the minimum inside diameter of the interstitial via holes 57 indicated by W 5 ranges from 3 mils to 4 mils.
  • the width of the first wiring pattern 58 indicated by W 6 ranges from 1.3 mils to 2 mils.
  • the space between the first wiring patterns 58 indicated by W 7 ranges from 1.3 mils to 2 mils.
  • the width of the second wiring pattern 59 indicated by W 8 in FIG. 3 ranges from 2.8 mils to 5.8 mils, and the space between the second wiring patterns 59 indicated by W 9 ranges from 1.8 mils to 3.8 mils. It is to be noted that 1 mil is one thousandth of an inch, which is equivalent to approximately 25.4 ⁇ .
  • the narrower first wiring pattern 58 formed in the center portion of the board is connected to the wider second wiring pattern 59 formed at the outer peripheral portion of the board by the taper-shaped pattern 60 .
  • the width W 6 of the signal line 52 is set narrower in nearly the center portion of the board, which has a relatively high wiring density. It is thus possible to sufficiently secure the space W 7 between the first wiring patterns 58 to relatively easily provide a suitable insulation interval. This can overcome the difficulty of providing wiring on an area with a relatively high wiring density. More specifically, even if the pads 53 are formed close to each other, a plurality of signal lines 52 can be laid out between the pads 53 .
  • the width W 8 of the signal line 52 is made wider at the board's outer peripheral portion, which has a low wiring density as shown in FIG. 3 .
  • the wiring resistance therefore becomes smaller than that of the conventional structure (see FIG. 9 ), which simply uses the signal lines 62 having narrow and uniform widths, so that a circuit malfunction is unlikely to occur.
  • the first wiring pattern 58 and the second wiring pattern 59 which have different widths, are connected together by the taper-shaped pattern 60 , the width of which continuously changes. Stress is therefore unlikely to concentrate on a specific portion of the permanent resist 56 as compared with the prior art (see FIG. 9 ), which directly connects the second wiring pattern 62 a to the first wiring pattern 62 b. It is thus possible to prevent the occurrence of cracks 64 in the permanent resist 63 , which occur in the prior art indicated in FIG. 10 .
  • the wiring board 51 for mounting electronic circuit parts according to this embodiment therefore has excellent reliability.
  • the second embodiment may be modified as follows.
  • the first and second wiring patterns 58 and 59 are connected together by the taper-shaped pattern 66 .
  • the connected portion 66 in this example has a first side edge 66 a extending in parallel to the center lines CL 1 and CL 2 of both wiring patterns 58 and 59 , and a second side edge 66 b inclined to both center lines CL 1 and CL 2 .
  • This structure also has the same function and advantages of the second embodiment. In this case, the number of intersections where stress is likely to concentrate is reduced, so that cracks are less likely to occur in this structure than in the second embodiment shown in FIG. 3 .
  • each signal line 52 The types of the wiring patterns 58 and 59 constituting each signal line 52 are not limited to two as shown in the second embodiment, but the wiring width may be increased in three or more stages in accordance with the wiring density on the board's surface.
  • this invention can achieve the higher density and compact size of a wiring board, which facilitates to designing interconnection.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
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US10/839,813 1996-09-12 2004-05-06 Circuit board for mounting electronic parts Expired - Lifetime USRE44251E1 (en)

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PCT/JP1996/002608 WO1998011605A1 (fr) 1995-06-19 1996-09-12 Carte de circuit permettant le montage de pieces electroniques
US6848198A 1998-05-11 1998-05-11
US09/412,877 US6384344B1 (en) 1995-06-19 1999-10-05 Circuit board for mounting electronic parts
US10/839,813 USRE44251E1 (en) 1996-09-12 2004-05-06 Circuit board for mounting electronic parts

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US20170354035A1 (en) * 2014-08-04 2017-12-07 Minebea Co., Ltd. Flexible printed circuit board
US9942982B2 (en) 1997-08-04 2018-04-10 Continental Circuits, Llc Electrical device with teeth joining layers and method for making the same
US20190223290A1 (en) * 2018-01-16 2019-07-18 Toshiba Electronic Devices & Storage Corporation Interposer substrate and multilayer printed substrate

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EP0883173A4 (de) 2001-05-09
EP1397031A2 (de) 2004-03-10
DE69637246D1 (de) 2007-10-25
EP0883173A1 (de) 1998-12-09
EP1397031A3 (de) 2005-01-19
KR100327887B1 (ko) 2002-10-19
EP0883173B1 (de) 2007-09-12
WO1998011605A1 (fr) 1998-03-19
KR19990067487A (ko) 1999-08-25

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