EP0539075A1 - Halbleiteranordnung mit einem isolierenden Substrat - Google Patents

Halbleiteranordnung mit einem isolierenden Substrat Download PDF

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Publication number
EP0539075A1
EP0539075A1 EP92309278A EP92309278A EP0539075A1 EP 0539075 A1 EP0539075 A1 EP 0539075A1 EP 92309278 A EP92309278 A EP 92309278A EP 92309278 A EP92309278 A EP 92309278A EP 0539075 A1 EP0539075 A1 EP 0539075A1
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EP
European Patent Office
Prior art keywords
resin substrate
holes
semiconductor element
semiconductor device
connection terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP92309278A
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English (en)
French (fr)
Inventor
Kaneyuki Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of EP0539075A1 publication Critical patent/EP0539075A1/de
Withdrawn legal-status Critical Current

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Definitions

  • the present invention relates to a semiconductor device.
  • FIG. 1A An example of a conventional semiconductor device is shown in FIG. 1A.
  • a semiconductor element 1 is placed in a hole 6 which is formed on the central portion of the upper surface of a resin substrate 8.
  • its bottom surface is adhered to the bottom of the hole 6 by means of a bonding agent 5.
  • the semiconductor element 1 is covered with an enclosure resin 2.
  • a plurality of through-holes 10, each of which extends to the lower face of the resin substrate 8 through the resin substrate 8, are formed in two square circumferential rows along the outer periphery of the upper surface of the resin substrate 8 in such a manner as to surround the hole 6.
  • Lead pins 9 for external connection are inserted one by one in the through-holes 10.
  • a resin stopping frame 4 for preventing the enclosure resin 2 from flowing into the through-holes 10 is provided on the upper surface of the resin substrate 8 between the hole 6 and the lead pins 9 in such a manner as to surround the hole 6.
  • a plurality of element connection terminals 7 are provided on the upper surface of the resin substrate 8 between the hole 6 and the lead pins 9 in such a manner as to surround the hole 6 as shown in FIG. 1B.
  • connection between the signal input/output pads (not shown) of the semiconductor element 1 and the lead pins 9 is established by means of a plurality of connecting lines 3 and a plurality of wiring patterns 61.
  • the connecting lines 3 electrically connect the signal input/output pads of the semiconductor element 1 and the element connection terminals 7 one by one to each other.
  • the wiring patterns 61 which are formed on the upper surface of the resin substrate 8 electrically connect the element connection terminals 7 and the lead pins 9 one by one to each other.
  • the conventional semiconductor device described above has the problem that special specifications are required in order to mount the semiconductor element 1 of a larger size.
  • the size of the hole 6 must be increased in order to mount a larger semiconductor element 1. Since the through-holes 10 for receiving the lead pins 9 one by one therein are provided at the circumferential portion of the upper surface of the resin substrate 8, if the outer peripheral edge of the hole 6 comes to the outer side with respect to the positions of the through-holes 10 on the inner circumferential row shown in FIG.
  • the through-holes 10 on the inner circumferential row must be displaced to positions on the outer side with respect to the through-holes 10 on the outer circumferential row shown in FIG. 1A.
  • the size of the outer profile of the semiconductor device must be increased.
  • semiconductor devices of the type mentioned since the outer profile sizes are standardized according to the number of lead pins for the external connection by the JEDEC (Joint Electron Device Engineering Council) or the EIAJ (Electronic Industries Association of Japan), there is a problem that, when the standardized outer profile sizes cannot be satisfied, special specifications must be employed.
  • An object of the present invention is to provide a semiconductor device which allows mounting of a large semiconductor element while maintaining a standardized outer profile size.
  • a semiconductor device which comprises: a semiconductor element, a resin substrate having the semiconductor element placed on its upper surface, a plurality of element connection terminals provided on the upper surface of the resin substrate, and a plurality of through-holes formed from the upper surface of the resin substrate, in which the element connection terminals are provided on the outer side with respect to all or some of the through-holes.
  • FIG. 2A there is shown a semiconductor device of the first preferred embodiment of the present invention.
  • a semiconductor element 11 having a plurality of signal input/output pads (not shown) is placed on an insulator sheet 16 which is provided between the bottom surface of the semiconductor element 11 and the upper surface of a resin substrate 18.
  • the bottom surface of the element is adhered to the insulator sheet 16 by means of a bonding agent 15.
  • the semiconductor element 11 is covered with an enclosure resin 12.
  • a plurality of through-holes 20, each of which extends to the lower surface of the resin substrate 18 through the resin substrate 18, are formed in two square circumferential rows in the central portion of the upper surface of the resin substrate 18 along the side faces of the resin substrate 18 in an opposing relationship to (i.e. underneath) the bottom surface of the semiconductor element 11.
  • Lead pins 19 for external connection are inserted one by one into the through-holes 20.
  • a resin stopping frame 14 for preventing the enclosure resin 12 from flowing out of position is provided at the ends of the upper surface of the resin substrate 18 along the side faces of the resin substrate 18.
  • a plurality of element connection terminals 17 are provided on the upper surface of the resin substrate 18 on the outside of the through-holes and between the through-holes 20 and the resin stopping frame 14 along the side faces of the resin substrate 18 as shown in FIG. 2B.
  • Electric connection between the signal input/output pads of the semiconductor element 11 and the lead pins 19 is established by means of a plurality of connecting lines 13 and a plurality of wiring patterns 21.
  • the connecting lines 13 electrically connect the signal input/output pads and the element connection terminals 17 one by one to each other.
  • the wiring patterns 21 which are formed on the upper surface of the resin substrate 18 electrically connect the element connection terminals 17 and the lead pins 19 one by one to each other.
  • the resin substrate 18 may be formed from a laminate of glass epoxy, glass triazine, or glass polyimide. Copper is provided on the upper and lower surfaces of the resin substrate 18, and the wiring patterns 21 are formed by etching the copper.
  • Each through-hole 20 is plated with copper so that the copper on the upper surface of the resin substrate 18 and the copper on the lower surface of the resin substrate are electrically connected to each other by way of the plated copper of the through-hole 20.
  • Each lead pin 19 is formed from phosphor bronze, covar, or 42-alloy (iron alloy containing 42 % of nickel) with solder plating applied to the surface of the pin.
  • a semiconductor element 11 may be mounted even if the element is of somewhat larger outer profile size by suitably changing the positions at which the element connection terminals 17 are formed on the semiconductor device while maintaining its outer profile size as specified by existing standards.
  • the semiconductor device of the present embodiment has through-holes 20 formed in two circumferential rows along the side faces of the resin substrate 18, the through-holes 20 may also be formed in any other suitable number of rows and need not necessarily be formed along the side faces of the resin substrate 18.
  • FIG. 3A there is shown a semiconductor device of the second preferred embodiment of the present invention.
  • a semiconductor element 31 having a plurality of signal input/output pads (not shown) is placed on an insulator sheet 36 which is provided between the bottom surface of the semiconductor element 31 and the upper surface of a resin substrate 38.
  • the bottom surface of the semiconductor element 31 is adhered to the insulator sheet 36 by means of a bonding agent 35.
  • the semiconductor element 31 is covered with an enclosure resin 32.
  • a plurality of first through-holes 401 each of which extends to the lower surface of the resin substrate 38 through the resin substrate 38, are formed in a single square circumferential row in the central portion of the upper surface of the resin substrate 38 along the side faces of the resin substrate 38 in an opposing relationship to the bottom surface of the semiconductor element 31.
  • Lead pins 39 for external connection are inserted one by one into the first and second through-holes 401 and 402.
  • a resin stopping frame 34 for preventing the enclosure resin 32 from flowing out of position is provided at the ends of the upper surface of the resin substrate 38 along the side faces of the resin substrate 38.
  • a plurality of element connection terminals 37 are provided on the upper surface of the resin substrate 38 between the first through-holes 401 and the second through-holes 402 along the side faces of the resin substrate 38 as shown in FIG. 3B.
  • Electric connection between the signal input/output pads of the semiconductor element 31 and the lead pins 39 is established by means of a plurality of connecting lines 33 and a plurality of wiring patterns 41.
  • the connecting lines 33 electrically connect the signal input/output pads and element connection terminals 37 one by one to each other.
  • the wiring patterns 41 which are formed on the upper surface of the resin substrate 38 electrically connect the element connection terminals 37 and the lead pins 39 one by one to each other.
  • a semiconductor element 31 of somewhat larger outer profile size can still be mounted by suitably changing the positions at which the element connection terminals 37 are formed on the semiconductor device while maintaining its outer profile size as specified by existing standards.
  • the semiconductor device of the present embodiment has the first through-holes 401 formed in a single circumferential row along the side faces of the resin substrate 38 and the second through-holes 402 formed in a single circumferential row along the side faces of the resin substrate 38, the first and second through-holes 401 and 402 may also be formed in any other suitable number of rows and need not necessarily be formed along the side faces of the resin substrate 38.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
EP92309278A 1991-10-21 1992-10-12 Halbleiteranordnung mit einem isolierenden Substrat Withdrawn EP0539075A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3271629A JPH05109922A (ja) 1991-10-21 1991-10-21 半導体装置
JP271629/91 1991-10-21

Publications (1)

Publication Number Publication Date
EP0539075A1 true EP0539075A1 (de) 1993-04-28

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EP92309278A Withdrawn EP0539075A1 (de) 1991-10-21 1992-10-12 Halbleiteranordnung mit einem isolierenden Substrat

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Country Link
EP (1) EP0539075A1 (de)
JP (1) JPH05109922A (de)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0664562A1 (de) * 1994-01-12 1995-07-26 AT&T Corp. Plastikgehäuse für Träger mit Kontaktgitter
WO1996038860A1 (de) * 1995-06-01 1996-12-05 Siemens Aktiengesellschaft Grundplatte für einen integrierten elektrischen schaltungsbaustein
US5625944A (en) * 1992-12-30 1997-05-06 Interconnect Systems, Inc. Methods for interconnecting integrated circuits
EP0883173A1 (de) * 1996-09-12 1998-12-09 Ibiden Co., Ltd. Leiterplatte zur montage elektronischer bauelemente
US6384344B1 (en) 1995-06-19 2002-05-07 Ibiden Co., Ltd Circuit board for mounting electronic parts
EP1814153A2 (de) * 1996-09-12 2007-08-01 Ibiden Co., Ltd. Leiterplatte zum Montieren von Elektronikteilen

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100437437B1 (ko) * 1994-03-18 2004-06-25 히다치 가세고교 가부시끼가이샤 반도체 패키지의 제조법 및 반도체 패키지
JP4029910B2 (ja) * 1994-03-18 2008-01-09 日立化成工業株式会社 半導体パッケ−ジの製造法及び半導体パッケ−ジ

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0351184A2 (de) * 1988-07-15 1990-01-17 Advanced Micro Devices, Inc. Packungsstruktur mit einem Steckerstift-Gitter
EP0351581A1 (de) * 1988-07-22 1990-01-24 Oerlikon-Contraves AG Hochintegrierte Schaltung sowie Verfahren zu deren Herstellung
WO1990013991A1 (en) * 1989-05-01 1990-11-15 Motorola, Inc. Method of grounding an ultra high density pad array chip carrier

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61177759A (ja) * 1985-02-04 1986-08-09 Hitachi Micro Comput Eng Ltd 半導体装置
JPH02168662A (ja) * 1988-09-07 1990-06-28 Hitachi Ltd チップキャリア

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0351184A2 (de) * 1988-07-15 1990-01-17 Advanced Micro Devices, Inc. Packungsstruktur mit einem Steckerstift-Gitter
EP0351581A1 (de) * 1988-07-22 1990-01-24 Oerlikon-Contraves AG Hochintegrierte Schaltung sowie Verfahren zu deren Herstellung
WO1990013991A1 (en) * 1989-05-01 1990-11-15 Motorola, Inc. Method of grounding an ultra high density pad array chip carrier

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5625944A (en) * 1992-12-30 1997-05-06 Interconnect Systems, Inc. Methods for interconnecting integrated circuits
US5712768A (en) * 1992-12-30 1998-01-27 Interconnect Systems, Inc. Space-saving assemblies for connecting integrated circuits to circuit boards
EP0664562A1 (de) * 1994-01-12 1995-07-26 AT&T Corp. Plastikgehäuse für Träger mit Kontaktgitter
US5926696A (en) * 1994-01-12 1999-07-20 Lucent Technologies Inc. Ball grid array plastic package
WO1996038860A1 (de) * 1995-06-01 1996-12-05 Siemens Aktiengesellschaft Grundplatte für einen integrierten elektrischen schaltungsbaustein
US6384344B1 (en) 1995-06-19 2002-05-07 Ibiden Co., Ltd Circuit board for mounting electronic parts
EP0883173A1 (de) * 1996-09-12 1998-12-09 Ibiden Co., Ltd. Leiterplatte zur montage elektronischer bauelemente
EP0883173A4 (de) * 1996-09-12 2001-05-09 Ibiden Co Ltd Leiterplatte zur montage elektronischer bauelemente
EP1814153A2 (de) * 1996-09-12 2007-08-01 Ibiden Co., Ltd. Leiterplatte zum Montieren von Elektronikteilen
EP1814153A3 (de) * 1996-09-12 2008-09-24 Ibiden Co., Ltd. Leiterplatte zum Montieren von Elektronikteilen
USRE44251E1 (en) 1996-09-12 2013-06-04 Ibiden Co., Ltd. Circuit board for mounting electronic parts

Also Published As

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